1 /* MN2WS0050 processor initialisation
2 *
3 * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11 #include <linux/sched.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16
17 #include <asm/processor.h>
18 #include <asm/uaccess.h>
19 #include <asm/io.h>
20 #include <linux/atomic.h>
21 #include <asm/smp.h>
22 #include <asm/pgalloc.h>
23 #include <asm/busctl-regs.h>
24 #include <unit/timex.h>
25 #include <asm/fpu.h>
26 #include <asm/rtc.h>
27
28 #define MEMCONF __SYSREGC(0xdf800400, u32)
29
30 /*
31 * initialise the on-silicon processor peripherals
32 */
processor_init(void)33 asmlinkage void __init processor_init(void)
34 {
35 int loop;
36
37 /* set up the exception table first */
38 for (loop = 0x000; loop < 0x400; loop += 8)
39 __set_intr_stub(loop, __common_exception);
40
41 __set_intr_stub(EXCEP_ITLBMISS, itlb_miss);
42 __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss);
43 __set_intr_stub(EXCEP_IAERROR, itlb_aerror);
44 __set_intr_stub(EXCEP_DAERROR, dtlb_aerror);
45 __set_intr_stub(EXCEP_BUSERROR, raw_bus_error);
46 __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault);
47 __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled);
48 __set_intr_stub(EXCEP_SYSCALL0, system_call);
49
50 __set_intr_stub(EXCEP_NMI, nmi_handler);
51 __set_intr_stub(EXCEP_WDT, nmi_handler);
52 __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler);
53 __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler);
54 __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler);
55 __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler);
56 __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler);
57 __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler);
58 __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler);
59
60 IVAR0 = EXCEP_IRQ_LEVEL0;
61 IVAR1 = EXCEP_IRQ_LEVEL1;
62 IVAR2 = EXCEP_IRQ_LEVEL2;
63 IVAR3 = EXCEP_IRQ_LEVEL3;
64 IVAR4 = EXCEP_IRQ_LEVEL4;
65 IVAR5 = EXCEP_IRQ_LEVEL5;
66 IVAR6 = EXCEP_IRQ_LEVEL6;
67
68 #ifndef CONFIG_MN10300_HAS_CACHE_SNOOP
69 mn10300_dcache_flush_inv();
70 mn10300_icache_inv();
71 #endif
72
73 /* disable all interrupts and set to priority 6 (lowest) */
74 #ifdef CONFIG_SMP
75 for (loop = 0; loop < GxICR_NUM_IRQS; loop++)
76 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
77 #else /* !CONFIG_SMP */
78 for (loop = 0; loop < NR_IRQS; loop++)
79 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
80 #endif /* !CONFIG_SMP */
81
82 /* clear the timers */
83 TM0MD = 0;
84 TM1MD = 0;
85 TM2MD = 0;
86 TM3MD = 0;
87 TM4MD = 0;
88 TM5MD = 0;
89 TM6MD = 0;
90 TM6MDA = 0;
91 TM6MDB = 0;
92 TM7MD = 0;
93 TM8MD = 0;
94 TM9MD = 0;
95 TM10MD = 0;
96 TM11MD = 0;
97 TM12MD = 0;
98 TM13MD = 0;
99 TM14MD = 0;
100 TM15MD = 0;
101
102 calibrate_clock();
103 }
104
105 /*
106 * determine the memory size and base from the memory controller regs
107 */
get_mem_info(unsigned long * mem_base,unsigned long * mem_size)108 void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size)
109 {
110 unsigned long memconf = MEMCONF;
111 unsigned long size = 0; /* order: MByte */
112
113 *mem_base = 0x90000000; /* fixed address */
114
115 switch (memconf & 0x00000003) {
116 case 0x01:
117 size = 256 / 8; /* 256 Mbit per chip */
118 break;
119 case 0x02:
120 size = 512 / 8; /* 512 Mbit per chip */
121 break;
122 case 0x03:
123 size = 1024 / 8; /* 1 Gbit per chip */
124 break;
125 default:
126 panic("Invalid SDRAM size");
127 break;
128 }
129
130 printk(KERN_INFO "DDR2-SDRAM: %luMB x 2 @%08lx\n", size, *mem_base);
131
132 *mem_size = (size * 2) << 20;
133 }
134