1/* 2 * Device tree source for the Emerson/Artesyn MVME2500 3 * 4 * Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * Based on: P2020 DS Device Tree Source 12 * Copyright 2009 Freescale Semiconductor Inc. 13 */ 14 15/include/ "p2020si-pre.dtsi" 16 17/ { 18 model = "MVME2500"; 19 compatible = "artesyn,MVME2500"; 20 21 aliases { 22 serial2 = &serial2; 23 serial3 = &serial3; 24 serial4 = &serial4; 25 serial5 = &serial5; 26 }; 27 28 memory { 29 device_type = "memory"; 30 }; 31 32 soc: soc@ffe00000 { 33 ranges = <0x0 0 0xffe00000 0x100000>; 34 35 i2c@3000 { 36 hwmon@4c { 37 compatible = "adi,adt7461"; 38 reg = <0x4c>; 39 }; 40 41 rtc@68 { 42 compatible = "dallas,ds1337"; 43 reg = <0x68>; 44 interrupts = <8 1 0 0>; 45 }; 46 47 eeprom@54 { 48 compatible = "atmel,24c64"; 49 reg = <0x54>; 50 }; 51 52 eeprom@52 { 53 compatible = "atmel,24c512"; 54 reg = <0x52>; 55 }; 56 57 eeprom@53 { 58 compatible = "atmel,24c512"; 59 reg = <0x53>; 60 }; 61 62 eeprom@50 { 63 compatible = "atmel,24c02"; 64 reg = <0x50>; 65 }; 66 67 }; 68 69 spi0: spi@7000 { 70 fsl,espi-num-chipselects = <2>; 71 72 flash@0 { 73 compatible = "atmel,at25df641"; 74 reg = <0>; 75 spi-max-frequency = <10000000>; 76 }; 77 flash@1 { 78 compatible = "atmel,at25df641"; 79 reg = <1>; 80 spi-max-frequency = <10000000>; 81 }; 82 }; 83 84 usb@22000 { 85 dr_mode = "host"; 86 phy_type = "ulpi"; 87 }; 88 89 enet0: ethernet@24000 { 90 tbi-handle = <&tbi0>; 91 phy-handle = <&phy1>; 92 phy-connection-type = "rgmii-id"; 93 }; 94 95 mdio@24520 { 96 phy1: ethernet-phy@1 { 97 compatible = "brcm,bcm54616S"; 98 interrupts = <6 1 0 0>; 99 reg = <0x1>; 100 }; 101 102 phy2: ethernet-phy@2 { 103 compatible = "brcm,bcm54616S"; 104 interrupts = <6 1 0 0>; 105 reg = <0x2>; 106 }; 107 108 phy3: ethernet-phy@3 { 109 compatible = "brcm,bcm54616S"; 110 interrupts = <5 1 0 0>; 111 reg = <0x3>; 112 }; 113 114 phy7: ethernet-phy@7 { 115 compatible = "brcm,bcm54616S"; 116 interrupts = <7 1 0 0>; 117 reg = <0x7>; 118 }; 119 120 tbi0: tbi-phy@11 { 121 reg = <0x11>; 122 device_type = "tbi-phy"; 123 }; 124 }; 125 126 enet1: ethernet@25000 { 127 tbi-handle = <&tbi1>; 128 phy-handle = <&phy7>; 129 phy-connection-type = "rgmii-id"; 130 }; 131 132 mdio@25520 { 133 tbi1: tbi-phy@11 { 134 reg = <0x11>; 135 device_type = "tbi-phy"; 136 }; 137 }; 138 139 enet2: ethernet@26000 { 140 tbi-handle = <&tbi2>; 141 phy-handle = <&phy3>; 142 phy-connection-type = "rgmii-id"; 143 }; 144 145 mdio@26520 { 146 tbi2: tbi-phy@11 { 147 reg = <0x11>; 148 device_type = "tbi-phy"; 149 }; 150 }; 151 }; 152 153 lbc: localbus@ffe05000 { 154 reg = <0 0xffe05000 0 0x1000>; 155 156 ranges = <0x0 0x0 0x0 0xfff00000 0x00080000 157 0x1 0x0 0x0 0xffc40000 0x00010000 158 0x2 0x0 0x0 0xffc50000 0x00010000 159 0x3 0x0 0x0 0xffc60000 0x00010000 160 0x4 0x0 0x0 0xffc70000 0x00010000 161 0x6 0x0 0x0 0xffc80000 0x00010000 162 0x5 0x0 0x0 0xffdf0000 0x00008000>; 163 164 serial2: serial@1,0 { 165 device_type = "serial"; 166 compatible = "ns16550"; 167 reg = <0x1 0x0 0x100>; 168 clock-frequency = <1843200>; 169 interrupts = <11 2 0 0>; 170 }; 171 172 serial3: serial@2,0 { 173 device_type = "serial"; 174 compatible = "ns16550"; 175 reg = <0x2 0x0 0x100>; 176 clock-frequency = <1843200>; 177 interrupts = <1 2 0 0>; 178 }; 179 180 serial4: serial@3,0 { 181 device_type = "serial"; 182 compatible = "ns16550"; 183 reg = <0x3 0x0 0x100>; 184 clock-frequency = <1843200>; 185 interrupts = <2 2 0 0>; 186 }; 187 188 serial5: serial@4,0 { 189 device_type = "serial"; 190 compatible = "ns16550"; 191 reg = <0x4 0x0 0x100>; 192 clock-frequency = <1843200>; 193 interrupts = <3 2 0 0>; 194 }; 195 196 mram@0,0 { 197 compatible = "everspin,mram", "mtd-ram"; 198 reg = <0x0 0x0 0x80000>; 199 bank-width = <2>; 200 }; 201 202 board-control@5,0 { 203 compatible = "artesyn,mvme2500-fpga"; 204 reg = <0x5 0x0 0x01000>; 205 }; 206 207 cpld@6,0 { 208 compatible = "artesyn,mvme2500-cpld"; 209 reg = <0x6 0x0 0x10000>; 210 interrupts = <9 1 0 0>; 211 }; 212 }; 213 214 pci0: pcie@ffe08000 { 215 reg = <0 0xffe08000 0 0x1000>; 216 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 217 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 218 pcie@0 { 219 ranges = <0x2000000 0x0 0x80000000 220 0x2000000 0x0 0x80000000 221 0x0 0x20000000 222 223 0x1000000 0x0 0x0 224 0x1000000 0x0 0x0 225 0x0 0x10000>; 226 }; 227 }; 228 229 pci1: pcie@ffe09000 { 230 reg = <0 0xffe09000 0 0x1000>; 231 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 232 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 233 pcie@0 { 234 ranges = <0x2000000 0x0 0xa0000000 235 0x2000000 0x0 0xa0000000 236 0x0 0x20000000 237 238 0x1000000 0x0 0x0 239 0x1000000 0x0 0x0 240 0x0 0x10000>; 241 }; 242 243 }; 244 245 pci2: pcie@ffe0a000 { 246 reg = <0 0xffe0a000 0 0x1000>; 247 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 248 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 249 pcie@0 { 250 ranges = <0x2000000 0x0 0xc0000000 251 0x2000000 0x0 0xc0000000 252 0x0 0x20000000 253 254 0x1000000 0x0 0x0 255 0x1000000 0x0 0x0 256 0x0 0x10000>; 257 }; 258 }; 259}; 260 261/include/ "p2020si-post.dtsi" 262 263/ { 264 soc@ffe00000 { 265 serial@4600 { 266 status = "disabled"; 267 }; 268 269 i2c@3100 { 270 status = "disabled"; 271 }; 272 273 sdhc@2e000 { 274 compatible = "fsl,p2020-esdhc", "fsl,esdhc"; 275 non-removable; 276 }; 277 278 }; 279 280}; 281