1 /*
2 * Copyright IBM Corporation 2001, 2005, 2006
3 * Copyright Dave Engebretsen & Todd Inglett 2001
4 * Copyright Linas Vepstas 2005, 2006
5 * Copyright 2001-2012 IBM Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
22 */
23
24 #include <linux/delay.h>
25 #include <linux/debugfs.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
28 #include <linux/list.h>
29 #include <linux/pci.h>
30 #include <linux/iommu.h>
31 #include <linux/proc_fs.h>
32 #include <linux/rbtree.h>
33 #include <linux/reboot.h>
34 #include <linux/seq_file.h>
35 #include <linux/spinlock.h>
36 #include <linux/export.h>
37 #include <linux/of.h>
38
39 #include <linux/atomic.h>
40 #include <asm/debug.h>
41 #include <asm/eeh.h>
42 #include <asm/eeh_event.h>
43 #include <asm/io.h>
44 #include <asm/iommu.h>
45 #include <asm/machdep.h>
46 #include <asm/ppc-pci.h>
47 #include <asm/rtas.h>
48
49
50 /** Overview:
51 * EEH, or "Extended Error Handling" is a PCI bridge technology for
52 * dealing with PCI bus errors that can't be dealt with within the
53 * usual PCI framework, except by check-stopping the CPU. Systems
54 * that are designed for high-availability/reliability cannot afford
55 * to crash due to a "mere" PCI error, thus the need for EEH.
56 * An EEH-capable bridge operates by converting a detected error
57 * into a "slot freeze", taking the PCI adapter off-line, making
58 * the slot behave, from the OS'es point of view, as if the slot
59 * were "empty": all reads return 0xff's and all writes are silently
60 * ignored. EEH slot isolation events can be triggered by parity
61 * errors on the address or data busses (e.g. during posted writes),
62 * which in turn might be caused by low voltage on the bus, dust,
63 * vibration, humidity, radioactivity or plain-old failed hardware.
64 *
65 * Note, however, that one of the leading causes of EEH slot
66 * freeze events are buggy device drivers, buggy device microcode,
67 * or buggy device hardware. This is because any attempt by the
68 * device to bus-master data to a memory address that is not
69 * assigned to the device will trigger a slot freeze. (The idea
70 * is to prevent devices-gone-wild from corrupting system memory).
71 * Buggy hardware/drivers will have a miserable time co-existing
72 * with EEH.
73 *
74 * Ideally, a PCI device driver, when suspecting that an isolation
75 * event has occurred (e.g. by reading 0xff's), will then ask EEH
76 * whether this is the case, and then take appropriate steps to
77 * reset the PCI slot, the PCI device, and then resume operations.
78 * However, until that day, the checking is done here, with the
79 * eeh_check_failure() routine embedded in the MMIO macros. If
80 * the slot is found to be isolated, an "EEH Event" is synthesized
81 * and sent out for processing.
82 */
83
84 /* If a device driver keeps reading an MMIO register in an interrupt
85 * handler after a slot isolation event, it might be broken.
86 * This sets the threshold for how many read attempts we allow
87 * before printing an error message.
88 */
89 #define EEH_MAX_FAILS 2100000
90
91 /* Time to wait for a PCI slot to report status, in milliseconds */
92 #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
93
94 /*
95 * EEH probe mode support, which is part of the flags,
96 * is to support multiple platforms for EEH. Some platforms
97 * like pSeries do PCI emunation based on device tree.
98 * However, other platforms like powernv probe PCI devices
99 * from hardware. The flag is used to distinguish that.
100 * In addition, struct eeh_ops::probe would be invoked for
101 * particular OF node or PCI device so that the corresponding
102 * PE would be created there.
103 */
104 int eeh_subsystem_flags;
105 EXPORT_SYMBOL(eeh_subsystem_flags);
106
107 /*
108 * EEH allowed maximal frozen times. If one particular PE's
109 * frozen count in last hour exceeds this limit, the PE will
110 * be forced to be offline permanently.
111 */
112 int eeh_max_freezes = 5;
113
114 /* Platform dependent EEH operations */
115 struct eeh_ops *eeh_ops = NULL;
116
117 /* Lock to avoid races due to multiple reports of an error */
118 DEFINE_RAW_SPINLOCK(confirm_error_lock);
119
120 /* Lock to protect passed flags */
121 static DEFINE_MUTEX(eeh_dev_mutex);
122
123 /* Buffer for reporting pci register dumps. Its here in BSS, and
124 * not dynamically alloced, so that it ends up in RMO where RTAS
125 * can access it.
126 */
127 #define EEH_PCI_REGS_LOG_LEN 8192
128 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
129
130 /*
131 * The struct is used to maintain the EEH global statistic
132 * information. Besides, the EEH global statistics will be
133 * exported to user space through procfs
134 */
135 struct eeh_stats {
136 u64 no_device; /* PCI device not found */
137 u64 no_dn; /* OF node not found */
138 u64 no_cfg_addr; /* Config address not found */
139 u64 ignored_check; /* EEH check skipped */
140 u64 total_mmio_ffs; /* Total EEH checks */
141 u64 false_positives; /* Unnecessary EEH checks */
142 u64 slot_resets; /* PE reset */
143 };
144
145 static struct eeh_stats eeh_stats;
146
eeh_setup(char * str)147 static int __init eeh_setup(char *str)
148 {
149 if (!strcmp(str, "off"))
150 eeh_add_flag(EEH_FORCE_DISABLED);
151 else if (!strcmp(str, "early_log"))
152 eeh_add_flag(EEH_EARLY_DUMP_LOG);
153
154 return 1;
155 }
156 __setup("eeh=", eeh_setup);
157
158 /*
159 * This routine captures assorted PCI configuration space data
160 * for the indicated PCI device, and puts them into a buffer
161 * for RTAS error logging.
162 */
eeh_dump_dev_log(struct eeh_dev * edev,char * buf,size_t len)163 static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
164 {
165 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
166 u32 cfg;
167 int cap, i;
168 int n = 0, l = 0;
169 char buffer[128];
170
171 n += scnprintf(buf+n, len-n, "%04x:%02x:%02x:%01x\n",
172 edev->phb->global_number, pdn->busno,
173 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
174 pr_warn("EEH: of node=%04x:%02x:%02x:%01x\n",
175 edev->phb->global_number, pdn->busno,
176 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
177
178 eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
179 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
180 pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
181
182 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);
183 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
184 pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
185
186 /* Gather bridge-specific registers */
187 if (edev->mode & EEH_DEV_BRIDGE) {
188 eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
189 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
190 pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
191
192 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
193 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
194 pr_warn("EEH: Bridge control: %04x\n", cfg);
195 }
196
197 /* Dump out the PCI-X command and status regs */
198 cap = edev->pcix_cap;
199 if (cap) {
200 eeh_ops->read_config(pdn, cap, 4, &cfg);
201 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
202 pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
203
204 eeh_ops->read_config(pdn, cap+4, 4, &cfg);
205 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
206 pr_warn("EEH: PCI-X status: %08x\n", cfg);
207 }
208
209 /* If PCI-E capable, dump PCI-E cap 10 */
210 cap = edev->pcie_cap;
211 if (cap) {
212 n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
213 pr_warn("EEH: PCI-E capabilities and status follow:\n");
214
215 for (i=0; i<=8; i++) {
216 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
217 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
218
219 if ((i % 4) == 0) {
220 if (i != 0)
221 pr_warn("%s\n", buffer);
222
223 l = scnprintf(buffer, sizeof(buffer),
224 "EEH: PCI-E %02x: %08x ",
225 4*i, cfg);
226 } else {
227 l += scnprintf(buffer+l, sizeof(buffer)-l,
228 "%08x ", cfg);
229 }
230
231 }
232
233 pr_warn("%s\n", buffer);
234 }
235
236 /* If AER capable, dump it */
237 cap = edev->aer_cap;
238 if (cap) {
239 n += scnprintf(buf+n, len-n, "pci-e AER:\n");
240 pr_warn("EEH: PCI-E AER capability register set follows:\n");
241
242 for (i=0; i<=13; i++) {
243 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
244 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
245
246 if ((i % 4) == 0) {
247 if (i != 0)
248 pr_warn("%s\n", buffer);
249
250 l = scnprintf(buffer, sizeof(buffer),
251 "EEH: PCI-E AER %02x: %08x ",
252 4*i, cfg);
253 } else {
254 l += scnprintf(buffer+l, sizeof(buffer)-l,
255 "%08x ", cfg);
256 }
257 }
258
259 pr_warn("%s\n", buffer);
260 }
261
262 return n;
263 }
264
eeh_dump_pe_log(void * data,void * flag)265 static void *eeh_dump_pe_log(void *data, void *flag)
266 {
267 struct eeh_pe *pe = data;
268 struct eeh_dev *edev, *tmp;
269 size_t *plen = flag;
270
271 /* If the PE's config space is blocked, 0xFF's will be
272 * returned. It's pointless to collect the log in this
273 * case.
274 */
275 if (pe->state & EEH_PE_CFG_BLOCKED)
276 return NULL;
277
278 eeh_pe_for_each_dev(pe, edev, tmp)
279 *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
280 EEH_PCI_REGS_LOG_LEN - *plen);
281
282 return NULL;
283 }
284
285 /**
286 * eeh_slot_error_detail - Generate combined log including driver log and error log
287 * @pe: EEH PE
288 * @severity: temporary or permanent error log
289 *
290 * This routine should be called to generate the combined log, which
291 * is comprised of driver log and error log. The driver log is figured
292 * out from the config space of the corresponding PCI device, while
293 * the error log is fetched through platform dependent function call.
294 */
eeh_slot_error_detail(struct eeh_pe * pe,int severity)295 void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
296 {
297 size_t loglen = 0;
298
299 /*
300 * When the PHB is fenced or dead, it's pointless to collect
301 * the data from PCI config space because it should return
302 * 0xFF's. For ER, we still retrieve the data from the PCI
303 * config space.
304 *
305 * For pHyp, we have to enable IO for log retrieval. Otherwise,
306 * 0xFF's is always returned from PCI config space.
307 *
308 * When the @severity is EEH_LOG_PERM, the PE is going to be
309 * removed. Prior to that, the drivers for devices included in
310 * the PE will be closed. The drivers rely on working IO path
311 * to bring the devices to quiet state. Otherwise, PCI traffic
312 * from those devices after they are removed is like to cause
313 * another unexpected EEH error.
314 */
315 if (!(pe->type & EEH_PE_PHB)) {
316 if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
317 severity == EEH_LOG_PERM)
318 eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
319
320 /*
321 * The config space of some PCI devices can't be accessed
322 * when their PEs are in frozen state. Otherwise, fenced
323 * PHB might be seen. Those PEs are identified with flag
324 * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
325 * is set automatically when the PE is put to EEH_PE_ISOLATED.
326 *
327 * Restoring BARs possibly triggers PCI config access in
328 * (OPAL) firmware and then causes fenced PHB. If the
329 * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
330 * pointless to restore BARs and dump config space.
331 */
332 eeh_ops->configure_bridge(pe);
333 if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
334 eeh_pe_restore_bars(pe);
335
336 pci_regs_buf[0] = 0;
337 eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
338 }
339 }
340
341 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
342 }
343
344 /**
345 * eeh_token_to_phys - Convert EEH address token to phys address
346 * @token: I/O token, should be address in the form 0xA....
347 *
348 * This routine should be called to convert virtual I/O address
349 * to physical one.
350 */
eeh_token_to_phys(unsigned long token)351 static inline unsigned long eeh_token_to_phys(unsigned long token)
352 {
353 pte_t *ptep;
354 unsigned long pa;
355 int hugepage_shift;
356
357 /*
358 * We won't find hugepages here(this is iomem). Hence we are not
359 * worried about _PAGE_SPLITTING/collapse. Also we will not hit
360 * page table free, because of init_mm.
361 */
362 ptep = __find_linux_pte_or_hugepte(init_mm.pgd, token,
363 NULL, &hugepage_shift);
364 if (!ptep)
365 return token;
366
367 pa = pte_pfn(*ptep);
368
369 /* On radix we can do hugepage mappings for io, so handle that */
370 if (!hugepage_shift)
371 hugepage_shift = PAGE_SHIFT;
372
373 pa <<= PAGE_SHIFT;
374 pa |= token & ((1ul << hugepage_shift) - 1);
375 return pa;
376 }
377
378 /*
379 * On PowerNV platform, we might already have fenced PHB there.
380 * For that case, it's meaningless to recover frozen PE. Intead,
381 * We have to handle fenced PHB firstly.
382 */
eeh_phb_check_failure(struct eeh_pe * pe)383 static int eeh_phb_check_failure(struct eeh_pe *pe)
384 {
385 struct eeh_pe *phb_pe;
386 unsigned long flags;
387 int ret;
388
389 if (!eeh_has_flag(EEH_PROBE_MODE_DEV))
390 return -EPERM;
391
392 /* Find the PHB PE */
393 phb_pe = eeh_phb_pe_get(pe->phb);
394 if (!phb_pe) {
395 pr_warn("%s Can't find PE for PHB#%d\n",
396 __func__, pe->phb->global_number);
397 return -EEXIST;
398 }
399
400 /* If the PHB has been in problematic state */
401 eeh_serialize_lock(&flags);
402 if (phb_pe->state & EEH_PE_ISOLATED) {
403 ret = 0;
404 goto out;
405 }
406
407 /* Check PHB state */
408 ret = eeh_ops->get_state(phb_pe, NULL);
409 if ((ret < 0) ||
410 (ret == EEH_STATE_NOT_SUPPORT) ||
411 (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) ==
412 (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) {
413 ret = 0;
414 goto out;
415 }
416
417 /* Isolate the PHB and send event */
418 eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED);
419 eeh_serialize_unlock(flags);
420
421 pr_err("EEH: PHB#%x failure detected, location: %s\n",
422 phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
423 dump_stack();
424 eeh_send_failure_event(phb_pe);
425
426 return 1;
427 out:
428 eeh_serialize_unlock(flags);
429 return ret;
430 }
431
432 /**
433 * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
434 * @edev: eeh device
435 *
436 * Check for an EEH failure for the given device node. Call this
437 * routine if the result of a read was all 0xff's and you want to
438 * find out if this is due to an EEH slot freeze. This routine
439 * will query firmware for the EEH status.
440 *
441 * Returns 0 if there has not been an EEH error; otherwise returns
442 * a non-zero value and queues up a slot isolation event notification.
443 *
444 * It is safe to call this routine in an interrupt context.
445 */
eeh_dev_check_failure(struct eeh_dev * edev)446 int eeh_dev_check_failure(struct eeh_dev *edev)
447 {
448 int ret;
449 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
450 unsigned long flags;
451 struct pci_dn *pdn;
452 struct pci_dev *dev;
453 struct eeh_pe *pe, *parent_pe, *phb_pe;
454 int rc = 0;
455 const char *location = NULL;
456
457 eeh_stats.total_mmio_ffs++;
458
459 if (!eeh_enabled())
460 return 0;
461
462 if (!edev) {
463 eeh_stats.no_dn++;
464 return 0;
465 }
466 dev = eeh_dev_to_pci_dev(edev);
467 pe = eeh_dev_to_pe(edev);
468
469 /* Access to IO BARs might get this far and still not want checking. */
470 if (!pe) {
471 eeh_stats.ignored_check++;
472 pr_debug("EEH: Ignored check for %s\n",
473 eeh_pci_name(dev));
474 return 0;
475 }
476
477 if (!pe->addr && !pe->config_addr) {
478 eeh_stats.no_cfg_addr++;
479 return 0;
480 }
481
482 /*
483 * On PowerNV platform, we might already have fenced PHB
484 * there and we need take care of that firstly.
485 */
486 ret = eeh_phb_check_failure(pe);
487 if (ret > 0)
488 return ret;
489
490 /*
491 * If the PE isn't owned by us, we shouldn't check the
492 * state. Instead, let the owner handle it if the PE has
493 * been frozen.
494 */
495 if (eeh_pe_passed(pe))
496 return 0;
497
498 /* If we already have a pending isolation event for this
499 * slot, we know it's bad already, we don't need to check.
500 * Do this checking under a lock; as multiple PCI devices
501 * in one slot might report errors simultaneously, and we
502 * only want one error recovery routine running.
503 */
504 eeh_serialize_lock(&flags);
505 rc = 1;
506 if (pe->state & EEH_PE_ISOLATED) {
507 pe->check_count++;
508 if (pe->check_count % EEH_MAX_FAILS == 0) {
509 pdn = eeh_dev_to_pdn(edev);
510 if (pdn->node)
511 location = of_get_property(pdn->node, "ibm,loc-code", NULL);
512 printk(KERN_ERR "EEH: %d reads ignored for recovering device at "
513 "location=%s driver=%s pci addr=%s\n",
514 pe->check_count,
515 location ? location : "unknown",
516 eeh_driver_name(dev), eeh_pci_name(dev));
517 printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n",
518 eeh_driver_name(dev));
519 dump_stack();
520 }
521 goto dn_unlock;
522 }
523
524 /*
525 * Now test for an EEH failure. This is VERY expensive.
526 * Note that the eeh_config_addr may be a parent device
527 * in the case of a device behind a bridge, or it may be
528 * function zero of a multi-function device.
529 * In any case they must share a common PHB.
530 */
531 ret = eeh_ops->get_state(pe, NULL);
532
533 /* Note that config-io to empty slots may fail;
534 * they are empty when they don't have children.
535 * We will punt with the following conditions: Failure to get
536 * PE's state, EEH not support and Permanently unavailable
537 * state, PE is in good state.
538 */
539 if ((ret < 0) ||
540 (ret == EEH_STATE_NOT_SUPPORT) ||
541 ((ret & active_flags) == active_flags)) {
542 eeh_stats.false_positives++;
543 pe->false_positives++;
544 rc = 0;
545 goto dn_unlock;
546 }
547
548 /*
549 * It should be corner case that the parent PE has been
550 * put into frozen state as well. We should take care
551 * that at first.
552 */
553 parent_pe = pe->parent;
554 while (parent_pe) {
555 /* Hit the ceiling ? */
556 if (parent_pe->type & EEH_PE_PHB)
557 break;
558
559 /* Frozen parent PE ? */
560 ret = eeh_ops->get_state(parent_pe, NULL);
561 if (ret > 0 &&
562 (ret & active_flags) != active_flags)
563 pe = parent_pe;
564
565 /* Next parent level */
566 parent_pe = parent_pe->parent;
567 }
568
569 eeh_stats.slot_resets++;
570
571 /* Avoid repeated reports of this failure, including problems
572 * with other functions on this device, and functions under
573 * bridges.
574 */
575 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
576 eeh_serialize_unlock(flags);
577
578 /* Most EEH events are due to device driver bugs. Having
579 * a stack trace will help the device-driver authors figure
580 * out what happened. So print that out.
581 */
582 phb_pe = eeh_phb_pe_get(pe->phb);
583 pr_err("EEH: Frozen PHB#%x-PE#%x detected\n",
584 pe->phb->global_number, pe->addr);
585 pr_err("EEH: PE location: %s, PHB location: %s\n",
586 eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe));
587 dump_stack();
588
589 eeh_send_failure_event(pe);
590
591 return 1;
592
593 dn_unlock:
594 eeh_serialize_unlock(flags);
595 return rc;
596 }
597
598 EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
599
600 /**
601 * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
602 * @token: I/O address
603 *
604 * Check for an EEH failure at the given I/O address. Call this
605 * routine if the result of a read was all 0xff's and you want to
606 * find out if this is due to an EEH slot freeze event. This routine
607 * will query firmware for the EEH status.
608 *
609 * Note this routine is safe to call in an interrupt context.
610 */
eeh_check_failure(const volatile void __iomem * token)611 int eeh_check_failure(const volatile void __iomem *token)
612 {
613 unsigned long addr;
614 struct eeh_dev *edev;
615
616 /* Finding the phys addr + pci device; this is pretty quick. */
617 addr = eeh_token_to_phys((unsigned long __force) token);
618 edev = eeh_addr_cache_get_dev(addr);
619 if (!edev) {
620 eeh_stats.no_device++;
621 return 0;
622 }
623
624 return eeh_dev_check_failure(edev);
625 }
626 EXPORT_SYMBOL(eeh_check_failure);
627
628
629 /**
630 * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
631 * @pe: EEH PE
632 *
633 * This routine should be called to reenable frozen MMIO or DMA
634 * so that it would work correctly again. It's useful while doing
635 * recovery or log collection on the indicated device.
636 */
eeh_pci_enable(struct eeh_pe * pe,int function)637 int eeh_pci_enable(struct eeh_pe *pe, int function)
638 {
639 int active_flag, rc;
640
641 /*
642 * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
643 * Also, it's pointless to enable them on unfrozen PE. So
644 * we have to check before enabling IO or DMA.
645 */
646 switch (function) {
647 case EEH_OPT_THAW_MMIO:
648 active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED;
649 break;
650 case EEH_OPT_THAW_DMA:
651 active_flag = EEH_STATE_DMA_ACTIVE;
652 break;
653 case EEH_OPT_DISABLE:
654 case EEH_OPT_ENABLE:
655 case EEH_OPT_FREEZE_PE:
656 active_flag = 0;
657 break;
658 default:
659 pr_warn("%s: Invalid function %d\n",
660 __func__, function);
661 return -EINVAL;
662 }
663
664 /*
665 * Check if IO or DMA has been enabled before
666 * enabling them.
667 */
668 if (active_flag) {
669 rc = eeh_ops->get_state(pe, NULL);
670 if (rc < 0)
671 return rc;
672
673 /* Needn't enable it at all */
674 if (rc == EEH_STATE_NOT_SUPPORT)
675 return 0;
676
677 /* It's already enabled */
678 if (rc & active_flag)
679 return 0;
680 }
681
682
683 /* Issue the request */
684 rc = eeh_ops->set_option(pe, function);
685 if (rc)
686 pr_warn("%s: Unexpected state change %d on "
687 "PHB#%d-PE#%x, err=%d\n",
688 __func__, function, pe->phb->global_number,
689 pe->addr, rc);
690
691 /* Check if the request is finished successfully */
692 if (active_flag) {
693 rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
694 if (rc < 0)
695 return rc;
696
697 if (rc & active_flag)
698 return 0;
699
700 return -EIO;
701 }
702
703 return rc;
704 }
705
eeh_disable_and_save_dev_state(void * data,void * userdata)706 static void *eeh_disable_and_save_dev_state(void *data, void *userdata)
707 {
708 struct eeh_dev *edev = data;
709 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
710 struct pci_dev *dev = userdata;
711
712 /*
713 * The caller should have disabled and saved the
714 * state for the specified device
715 */
716 if (!pdev || pdev == dev)
717 return NULL;
718
719 /* Ensure we have D0 power state */
720 pci_set_power_state(pdev, PCI_D0);
721
722 /* Save device state */
723 pci_save_state(pdev);
724
725 /*
726 * Disable device to avoid any DMA traffic and
727 * interrupt from the device
728 */
729 pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
730
731 return NULL;
732 }
733
eeh_restore_dev_state(void * data,void * userdata)734 static void *eeh_restore_dev_state(void *data, void *userdata)
735 {
736 struct eeh_dev *edev = data;
737 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
738 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
739 struct pci_dev *dev = userdata;
740
741 if (!pdev)
742 return NULL;
743
744 /* Apply customization from firmware */
745 if (pdn && eeh_ops->restore_config)
746 eeh_ops->restore_config(pdn);
747
748 /* The caller should restore state for the specified device */
749 if (pdev != dev)
750 pci_restore_state(pdev);
751
752 return NULL;
753 }
754
755 /**
756 * pcibios_set_pcie_slot_reset - Set PCI-E reset state
757 * @dev: pci device struct
758 * @state: reset state to enter
759 *
760 * Return value:
761 * 0 if success
762 */
pcibios_set_pcie_reset_state(struct pci_dev * dev,enum pcie_reset_state state)763 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
764 {
765 struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
766 struct eeh_pe *pe = eeh_dev_to_pe(edev);
767
768 if (!pe) {
769 pr_err("%s: No PE found on PCI device %s\n",
770 __func__, pci_name(dev));
771 return -EINVAL;
772 }
773
774 switch (state) {
775 case pcie_deassert_reset:
776 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
777 eeh_unfreeze_pe(pe, false);
778 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
779 eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
780 eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
781 break;
782 case pcie_hot_reset:
783 eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
784 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
785 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
786 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
787 eeh_ops->reset(pe, EEH_RESET_HOT);
788 break;
789 case pcie_warm_reset:
790 eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
791 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
792 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
793 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
794 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
795 break;
796 default:
797 eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED);
798 return -EINVAL;
799 };
800
801 return 0;
802 }
803
804 /**
805 * eeh_set_pe_freset - Check the required reset for the indicated device
806 * @data: EEH device
807 * @flag: return value
808 *
809 * Each device might have its preferred reset type: fundamental or
810 * hot reset. The routine is used to collected the information for
811 * the indicated device and its children so that the bunch of the
812 * devices could be reset properly.
813 */
eeh_set_dev_freset(void * data,void * flag)814 static void *eeh_set_dev_freset(void *data, void *flag)
815 {
816 struct pci_dev *dev;
817 unsigned int *freset = (unsigned int *)flag;
818 struct eeh_dev *edev = (struct eeh_dev *)data;
819
820 dev = eeh_dev_to_pci_dev(edev);
821 if (dev)
822 *freset |= dev->needs_freset;
823
824 return NULL;
825 }
826
827 /**
828 * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second
829 * @pe: EEH PE
830 *
831 * Assert the PCI #RST line for 1/4 second.
832 */
eeh_reset_pe_once(struct eeh_pe * pe)833 static void eeh_reset_pe_once(struct eeh_pe *pe)
834 {
835 unsigned int freset = 0;
836
837 /* Determine type of EEH reset required for
838 * Partitionable Endpoint, a hot-reset (1)
839 * or a fundamental reset (3).
840 * A fundamental reset required by any device under
841 * Partitionable Endpoint trumps hot-reset.
842 */
843 eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
844
845 if (freset)
846 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
847 else
848 eeh_ops->reset(pe, EEH_RESET_HOT);
849
850 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
851 }
852
853 /**
854 * eeh_reset_pe - Reset the indicated PE
855 * @pe: EEH PE
856 *
857 * This routine should be called to reset indicated device, including
858 * PE. A PE might include multiple PCI devices and sometimes PCI bridges
859 * might be involved as well.
860 */
eeh_reset_pe(struct eeh_pe * pe)861 int eeh_reset_pe(struct eeh_pe *pe)
862 {
863 int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
864 int i, state, ret;
865
866 /* Mark as reset and block config space */
867 eeh_pe_state_mark(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
868
869 /* Take three shots at resetting the bus */
870 for (i = 0; i < 3; i++) {
871 eeh_reset_pe_once(pe);
872
873 /*
874 * EEH_PE_ISOLATED is expected to be removed after
875 * BAR restore.
876 */
877 state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
878 if ((state & flags) == flags) {
879 ret = 0;
880 goto out;
881 }
882
883 if (state < 0) {
884 pr_warn("%s: Unrecoverable slot failure on PHB#%d-PE#%x",
885 __func__, pe->phb->global_number, pe->addr);
886 ret = -ENOTRECOVERABLE;
887 goto out;
888 }
889
890 /* We might run out of credits */
891 ret = -EIO;
892 pr_warn("%s: Failure %d resetting PHB#%x-PE#%x\n (%d)\n",
893 __func__, state, pe->phb->global_number, pe->addr, (i + 1));
894 }
895
896 out:
897 eeh_pe_state_clear(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
898 return ret;
899 }
900
901 /**
902 * eeh_save_bars - Save device bars
903 * @edev: PCI device associated EEH device
904 *
905 * Save the values of the device bars. Unlike the restore
906 * routine, this routine is *not* recursive. This is because
907 * PCI devices are added individually; but, for the restore,
908 * an entire slot is reset at a time.
909 */
eeh_save_bars(struct eeh_dev * edev)910 void eeh_save_bars(struct eeh_dev *edev)
911 {
912 struct pci_dn *pdn;
913 int i;
914
915 pdn = eeh_dev_to_pdn(edev);
916 if (!pdn)
917 return;
918
919 for (i = 0; i < 16; i++)
920 eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);
921
922 /*
923 * For PCI bridges including root port, we need enable bus
924 * master explicitly. Otherwise, it can't fetch IODA table
925 * entries correctly. So we cache the bit in advance so that
926 * we can restore it after reset, either PHB range or PE range.
927 */
928 if (edev->mode & EEH_DEV_BRIDGE)
929 edev->config_space[1] |= PCI_COMMAND_MASTER;
930 }
931
932 /**
933 * eeh_ops_register - Register platform dependent EEH operations
934 * @ops: platform dependent EEH operations
935 *
936 * Register the platform dependent EEH operation callback
937 * functions. The platform should call this function before
938 * any other EEH operations.
939 */
eeh_ops_register(struct eeh_ops * ops)940 int __init eeh_ops_register(struct eeh_ops *ops)
941 {
942 if (!ops->name) {
943 pr_warn("%s: Invalid EEH ops name for %p\n",
944 __func__, ops);
945 return -EINVAL;
946 }
947
948 if (eeh_ops && eeh_ops != ops) {
949 pr_warn("%s: EEH ops of platform %s already existing (%s)\n",
950 __func__, eeh_ops->name, ops->name);
951 return -EEXIST;
952 }
953
954 eeh_ops = ops;
955
956 return 0;
957 }
958
959 /**
960 * eeh_ops_unregister - Unreigster platform dependent EEH operations
961 * @name: name of EEH platform operations
962 *
963 * Unregister the platform dependent EEH operation callback
964 * functions.
965 */
eeh_ops_unregister(const char * name)966 int __exit eeh_ops_unregister(const char *name)
967 {
968 if (!name || !strlen(name)) {
969 pr_warn("%s: Invalid EEH ops name\n",
970 __func__);
971 return -EINVAL;
972 }
973
974 if (eeh_ops && !strcmp(eeh_ops->name, name)) {
975 eeh_ops = NULL;
976 return 0;
977 }
978
979 return -EEXIST;
980 }
981
eeh_reboot_notifier(struct notifier_block * nb,unsigned long action,void * unused)982 static int eeh_reboot_notifier(struct notifier_block *nb,
983 unsigned long action, void *unused)
984 {
985 eeh_clear_flag(EEH_ENABLED);
986 return NOTIFY_DONE;
987 }
988
989 static struct notifier_block eeh_reboot_nb = {
990 .notifier_call = eeh_reboot_notifier,
991 };
992
993 /**
994 * eeh_init - EEH initialization
995 *
996 * Initialize EEH by trying to enable it for all of the adapters in the system.
997 * As a side effect we can determine here if eeh is supported at all.
998 * Note that we leave EEH on so failed config cycles won't cause a machine
999 * check. If a user turns off EEH for a particular adapter they are really
1000 * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
1001 * grant access to a slot if EEH isn't enabled, and so we always enable
1002 * EEH for all slots/all devices.
1003 *
1004 * The eeh-force-off option disables EEH checking globally, for all slots.
1005 * Even if force-off is set, the EEH hardware is still enabled, so that
1006 * newer systems can boot.
1007 */
eeh_init(void)1008 int eeh_init(void)
1009 {
1010 struct pci_controller *hose, *tmp;
1011 struct pci_dn *pdn;
1012 static int cnt = 0;
1013 int ret = 0;
1014
1015 /*
1016 * We have to delay the initialization on PowerNV after
1017 * the PCI hierarchy tree has been built because the PEs
1018 * are figured out based on PCI devices instead of device
1019 * tree nodes
1020 */
1021 if (machine_is(powernv) && cnt++ <= 0)
1022 return ret;
1023
1024 /* Register reboot notifier */
1025 ret = register_reboot_notifier(&eeh_reboot_nb);
1026 if (ret) {
1027 pr_warn("%s: Failed to register notifier (%d)\n",
1028 __func__, ret);
1029 return ret;
1030 }
1031
1032 /* call platform initialization function */
1033 if (!eeh_ops) {
1034 pr_warn("%s: Platform EEH operation not found\n",
1035 __func__);
1036 return -EEXIST;
1037 } else if ((ret = eeh_ops->init()))
1038 return ret;
1039
1040 /* Initialize EEH event */
1041 ret = eeh_event_init();
1042 if (ret)
1043 return ret;
1044
1045 /* Enable EEH for all adapters */
1046 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1047 pdn = hose->pci_data;
1048 traverse_pci_dn(pdn, eeh_ops->probe, NULL);
1049 }
1050
1051 /*
1052 * Call platform post-initialization. Actually, It's good chance
1053 * to inform platform that EEH is ready to supply service if the
1054 * I/O cache stuff has been built up.
1055 */
1056 if (eeh_ops->post_init) {
1057 ret = eeh_ops->post_init();
1058 if (ret)
1059 return ret;
1060 }
1061
1062 if (eeh_enabled())
1063 pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
1064 else
1065 pr_warn("EEH: No capable adapters found\n");
1066
1067 return ret;
1068 }
1069
1070 core_initcall_sync(eeh_init);
1071
1072 /**
1073 * eeh_add_device_early - Enable EEH for the indicated device node
1074 * @pdn: PCI device node for which to set up EEH
1075 *
1076 * This routine must be used to perform EEH initialization for PCI
1077 * devices that were added after system boot (e.g. hotplug, dlpar).
1078 * This routine must be called before any i/o is performed to the
1079 * adapter (inluding any config-space i/o).
1080 * Whether this actually enables EEH or not for this device depends
1081 * on the CEC architecture, type of the device, on earlier boot
1082 * command-line arguments & etc.
1083 */
eeh_add_device_early(struct pci_dn * pdn)1084 void eeh_add_device_early(struct pci_dn *pdn)
1085 {
1086 struct pci_controller *phb;
1087 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1088
1089 if (!edev)
1090 return;
1091
1092 if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE))
1093 return;
1094
1095 /* USB Bus children of PCI devices will not have BUID's */
1096 phb = edev->phb;
1097 if (NULL == phb ||
1098 (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid))
1099 return;
1100
1101 eeh_ops->probe(pdn, NULL);
1102 }
1103
1104 /**
1105 * eeh_add_device_tree_early - Enable EEH for the indicated device
1106 * @pdn: PCI device node
1107 *
1108 * This routine must be used to perform EEH initialization for the
1109 * indicated PCI device that was added after system boot (e.g.
1110 * hotplug, dlpar).
1111 */
eeh_add_device_tree_early(struct pci_dn * pdn)1112 void eeh_add_device_tree_early(struct pci_dn *pdn)
1113 {
1114 struct pci_dn *n;
1115
1116 if (!pdn)
1117 return;
1118
1119 list_for_each_entry(n, &pdn->child_list, list)
1120 eeh_add_device_tree_early(n);
1121 eeh_add_device_early(pdn);
1122 }
1123 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
1124
1125 /**
1126 * eeh_add_device_late - Perform EEH initialization for the indicated pci device
1127 * @dev: pci device for which to set up EEH
1128 *
1129 * This routine must be used to complete EEH initialization for PCI
1130 * devices that were added after system boot (e.g. hotplug, dlpar).
1131 */
eeh_add_device_late(struct pci_dev * dev)1132 void eeh_add_device_late(struct pci_dev *dev)
1133 {
1134 struct pci_dn *pdn;
1135 struct eeh_dev *edev;
1136
1137 if (!dev || !eeh_enabled())
1138 return;
1139
1140 pr_debug("EEH: Adding device %s\n", pci_name(dev));
1141
1142 pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
1143 edev = pdn_to_eeh_dev(pdn);
1144 if (edev->pdev == dev) {
1145 pr_debug("EEH: Already referenced !\n");
1146 return;
1147 }
1148
1149 /*
1150 * The EEH cache might not be removed correctly because of
1151 * unbalanced kref to the device during unplug time, which
1152 * relies on pcibios_release_device(). So we have to remove
1153 * that here explicitly.
1154 */
1155 if (edev->pdev) {
1156 eeh_rmv_from_parent_pe(edev);
1157 eeh_addr_cache_rmv_dev(edev->pdev);
1158 eeh_sysfs_remove_device(edev->pdev);
1159 edev->mode &= ~EEH_DEV_SYSFS;
1160
1161 /*
1162 * We definitely should have the PCI device removed
1163 * though it wasn't correctly. So we needn't call
1164 * into error handler afterwards.
1165 */
1166 edev->mode |= EEH_DEV_NO_HANDLER;
1167
1168 edev->pdev = NULL;
1169 dev->dev.archdata.edev = NULL;
1170 }
1171
1172 if (eeh_has_flag(EEH_PROBE_MODE_DEV))
1173 eeh_ops->probe(pdn, NULL);
1174
1175 edev->pdev = dev;
1176 dev->dev.archdata.edev = edev;
1177
1178 eeh_addr_cache_insert_dev(dev);
1179 }
1180
1181 /**
1182 * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus
1183 * @bus: PCI bus
1184 *
1185 * This routine must be used to perform EEH initialization for PCI
1186 * devices which are attached to the indicated PCI bus. The PCI bus
1187 * is added after system boot through hotplug or dlpar.
1188 */
eeh_add_device_tree_late(struct pci_bus * bus)1189 void eeh_add_device_tree_late(struct pci_bus *bus)
1190 {
1191 struct pci_dev *dev;
1192
1193 list_for_each_entry(dev, &bus->devices, bus_list) {
1194 eeh_add_device_late(dev);
1195 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1196 struct pci_bus *subbus = dev->subordinate;
1197 if (subbus)
1198 eeh_add_device_tree_late(subbus);
1199 }
1200 }
1201 }
1202 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
1203
1204 /**
1205 * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus
1206 * @bus: PCI bus
1207 *
1208 * This routine must be used to add EEH sysfs files for PCI
1209 * devices which are attached to the indicated PCI bus. The PCI bus
1210 * is added after system boot through hotplug or dlpar.
1211 */
eeh_add_sysfs_files(struct pci_bus * bus)1212 void eeh_add_sysfs_files(struct pci_bus *bus)
1213 {
1214 struct pci_dev *dev;
1215
1216 list_for_each_entry(dev, &bus->devices, bus_list) {
1217 eeh_sysfs_add_device(dev);
1218 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1219 struct pci_bus *subbus = dev->subordinate;
1220 if (subbus)
1221 eeh_add_sysfs_files(subbus);
1222 }
1223 }
1224 }
1225 EXPORT_SYMBOL_GPL(eeh_add_sysfs_files);
1226
1227 /**
1228 * eeh_remove_device - Undo EEH setup for the indicated pci device
1229 * @dev: pci device to be removed
1230 *
1231 * This routine should be called when a device is removed from
1232 * a running system (e.g. by hotplug or dlpar). It unregisters
1233 * the PCI device from the EEH subsystem. I/O errors affecting
1234 * this device will no longer be detected after this call; thus,
1235 * i/o errors affecting this slot may leave this device unusable.
1236 */
eeh_remove_device(struct pci_dev * dev)1237 void eeh_remove_device(struct pci_dev *dev)
1238 {
1239 struct eeh_dev *edev;
1240
1241 if (!dev || !eeh_enabled())
1242 return;
1243 edev = pci_dev_to_eeh_dev(dev);
1244
1245 /* Unregister the device with the EEH/PCI address search system */
1246 pr_debug("EEH: Removing device %s\n", pci_name(dev));
1247
1248 if (!edev || !edev->pdev || !edev->pe) {
1249 pr_debug("EEH: Not referenced !\n");
1250 return;
1251 }
1252
1253 /*
1254 * During the hotplug for EEH error recovery, we need the EEH
1255 * device attached to the parent PE in order for BAR restore
1256 * a bit later. So we keep it for BAR restore and remove it
1257 * from the parent PE during the BAR resotre.
1258 */
1259 edev->pdev = NULL;
1260 dev->dev.archdata.edev = NULL;
1261 if (!(edev->pe->state & EEH_PE_KEEP))
1262 eeh_rmv_from_parent_pe(edev);
1263 else
1264 edev->mode |= EEH_DEV_DISCONNECTED;
1265
1266 /*
1267 * We're removing from the PCI subsystem, that means
1268 * the PCI device driver can't support EEH or not
1269 * well. So we rely on hotplug completely to do recovery
1270 * for the specific PCI device.
1271 */
1272 edev->mode |= EEH_DEV_NO_HANDLER;
1273
1274 eeh_addr_cache_rmv_dev(dev);
1275 eeh_sysfs_remove_device(dev);
1276 edev->mode &= ~EEH_DEV_SYSFS;
1277 }
1278
eeh_unfreeze_pe(struct eeh_pe * pe,bool sw_state)1279 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state)
1280 {
1281 int ret;
1282
1283 ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
1284 if (ret) {
1285 pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n",
1286 __func__, ret, pe->phb->global_number, pe->addr);
1287 return ret;
1288 }
1289
1290 ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
1291 if (ret) {
1292 pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n",
1293 __func__, ret, pe->phb->global_number, pe->addr);
1294 return ret;
1295 }
1296
1297 /* Clear software isolated state */
1298 if (sw_state && (pe->state & EEH_PE_ISOLATED))
1299 eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
1300
1301 return ret;
1302 }
1303
1304
1305 static struct pci_device_id eeh_reset_ids[] = {
1306 { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */
1307 { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */
1308 { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */
1309 { 0 }
1310 };
1311
eeh_pe_change_owner(struct eeh_pe * pe)1312 static int eeh_pe_change_owner(struct eeh_pe *pe)
1313 {
1314 struct eeh_dev *edev, *tmp;
1315 struct pci_dev *pdev;
1316 struct pci_device_id *id;
1317 int flags, ret;
1318
1319 /* Check PE state */
1320 flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
1321 ret = eeh_ops->get_state(pe, NULL);
1322 if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT)
1323 return 0;
1324
1325 /* Unfrozen PE, nothing to do */
1326 if ((ret & flags) == flags)
1327 return 0;
1328
1329 /* Frozen PE, check if it needs PE level reset */
1330 eeh_pe_for_each_dev(pe, edev, tmp) {
1331 pdev = eeh_dev_to_pci_dev(edev);
1332 if (!pdev)
1333 continue;
1334
1335 for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) {
1336 if (id->vendor != PCI_ANY_ID &&
1337 id->vendor != pdev->vendor)
1338 continue;
1339 if (id->device != PCI_ANY_ID &&
1340 id->device != pdev->device)
1341 continue;
1342 if (id->subvendor != PCI_ANY_ID &&
1343 id->subvendor != pdev->subsystem_vendor)
1344 continue;
1345 if (id->subdevice != PCI_ANY_ID &&
1346 id->subdevice != pdev->subsystem_device)
1347 continue;
1348
1349 goto reset;
1350 }
1351 }
1352
1353 return eeh_unfreeze_pe(pe, true);
1354
1355 reset:
1356 return eeh_pe_reset_and_recover(pe);
1357 }
1358
1359 /**
1360 * eeh_dev_open - Increase count of pass through devices for PE
1361 * @pdev: PCI device
1362 *
1363 * Increase count of passed through devices for the indicated
1364 * PE. In the result, the EEH errors detected on the PE won't be
1365 * reported. The PE owner will be responsible for detection
1366 * and recovery.
1367 */
eeh_dev_open(struct pci_dev * pdev)1368 int eeh_dev_open(struct pci_dev *pdev)
1369 {
1370 struct eeh_dev *edev;
1371 int ret = -ENODEV;
1372
1373 mutex_lock(&eeh_dev_mutex);
1374
1375 /* No PCI device ? */
1376 if (!pdev)
1377 goto out;
1378
1379 /* No EEH device or PE ? */
1380 edev = pci_dev_to_eeh_dev(pdev);
1381 if (!edev || !edev->pe)
1382 goto out;
1383
1384 /*
1385 * The PE might have been put into frozen state, but we
1386 * didn't detect that yet. The passed through PCI devices
1387 * in frozen PE won't work properly. Clear the frozen state
1388 * in advance.
1389 */
1390 ret = eeh_pe_change_owner(edev->pe);
1391 if (ret)
1392 goto out;
1393
1394 /* Increase PE's pass through count */
1395 atomic_inc(&edev->pe->pass_dev_cnt);
1396 mutex_unlock(&eeh_dev_mutex);
1397
1398 return 0;
1399 out:
1400 mutex_unlock(&eeh_dev_mutex);
1401 return ret;
1402 }
1403 EXPORT_SYMBOL_GPL(eeh_dev_open);
1404
1405 /**
1406 * eeh_dev_release - Decrease count of pass through devices for PE
1407 * @pdev: PCI device
1408 *
1409 * Decrease count of pass through devices for the indicated PE. If
1410 * there is no passed through device in PE, the EEH errors detected
1411 * on the PE will be reported and handled as usual.
1412 */
eeh_dev_release(struct pci_dev * pdev)1413 void eeh_dev_release(struct pci_dev *pdev)
1414 {
1415 struct eeh_dev *edev;
1416
1417 mutex_lock(&eeh_dev_mutex);
1418
1419 /* No PCI device ? */
1420 if (!pdev)
1421 goto out;
1422
1423 /* No EEH device ? */
1424 edev = pci_dev_to_eeh_dev(pdev);
1425 if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
1426 goto out;
1427
1428 /* Decrease PE's pass through count */
1429 WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
1430 eeh_pe_change_owner(edev->pe);
1431 out:
1432 mutex_unlock(&eeh_dev_mutex);
1433 }
1434 EXPORT_SYMBOL(eeh_dev_release);
1435
1436 #ifdef CONFIG_IOMMU_API
1437
dev_has_iommu_table(struct device * dev,void * data)1438 static int dev_has_iommu_table(struct device *dev, void *data)
1439 {
1440 struct pci_dev *pdev = to_pci_dev(dev);
1441 struct pci_dev **ppdev = data;
1442
1443 if (!dev)
1444 return 0;
1445
1446 if (dev->iommu_group) {
1447 *ppdev = pdev;
1448 return 1;
1449 }
1450
1451 return 0;
1452 }
1453
1454 /**
1455 * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE
1456 * @group: IOMMU group
1457 *
1458 * The routine is called to convert IOMMU group to EEH PE.
1459 */
eeh_iommu_group_to_pe(struct iommu_group * group)1460 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group)
1461 {
1462 struct pci_dev *pdev = NULL;
1463 struct eeh_dev *edev;
1464 int ret;
1465
1466 /* No IOMMU group ? */
1467 if (!group)
1468 return NULL;
1469
1470 ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table);
1471 if (!ret || !pdev)
1472 return NULL;
1473
1474 /* No EEH device or PE ? */
1475 edev = pci_dev_to_eeh_dev(pdev);
1476 if (!edev || !edev->pe)
1477 return NULL;
1478
1479 return edev->pe;
1480 }
1481 EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe);
1482
1483 #endif /* CONFIG_IOMMU_API */
1484
1485 /**
1486 * eeh_pe_set_option - Set options for the indicated PE
1487 * @pe: EEH PE
1488 * @option: requested option
1489 *
1490 * The routine is called to enable or disable EEH functionality
1491 * on the indicated PE, to enable IO or DMA for the frozen PE.
1492 */
eeh_pe_set_option(struct eeh_pe * pe,int option)1493 int eeh_pe_set_option(struct eeh_pe *pe, int option)
1494 {
1495 int ret = 0;
1496
1497 /* Invalid PE ? */
1498 if (!pe)
1499 return -ENODEV;
1500
1501 /*
1502 * EEH functionality could possibly be disabled, just
1503 * return error for the case. And the EEH functinality
1504 * isn't expected to be disabled on one specific PE.
1505 */
1506 switch (option) {
1507 case EEH_OPT_ENABLE:
1508 if (eeh_enabled()) {
1509 ret = eeh_pe_change_owner(pe);
1510 break;
1511 }
1512 ret = -EIO;
1513 break;
1514 case EEH_OPT_DISABLE:
1515 break;
1516 case EEH_OPT_THAW_MMIO:
1517 case EEH_OPT_THAW_DMA:
1518 if (!eeh_ops || !eeh_ops->set_option) {
1519 ret = -ENOENT;
1520 break;
1521 }
1522
1523 ret = eeh_pci_enable(pe, option);
1524 break;
1525 default:
1526 pr_debug("%s: Option %d out of range (%d, %d)\n",
1527 __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA);
1528 ret = -EINVAL;
1529 }
1530
1531 return ret;
1532 }
1533 EXPORT_SYMBOL_GPL(eeh_pe_set_option);
1534
1535 /**
1536 * eeh_pe_get_state - Retrieve PE's state
1537 * @pe: EEH PE
1538 *
1539 * Retrieve the PE's state, which includes 3 aspects: enabled
1540 * DMA, enabled IO and asserted reset.
1541 */
eeh_pe_get_state(struct eeh_pe * pe)1542 int eeh_pe_get_state(struct eeh_pe *pe)
1543 {
1544 int result, ret = 0;
1545 bool rst_active, dma_en, mmio_en;
1546
1547 /* Existing PE ? */
1548 if (!pe)
1549 return -ENODEV;
1550
1551 if (!eeh_ops || !eeh_ops->get_state)
1552 return -ENOENT;
1553
1554 result = eeh_ops->get_state(pe, NULL);
1555 rst_active = !!(result & EEH_STATE_RESET_ACTIVE);
1556 dma_en = !!(result & EEH_STATE_DMA_ENABLED);
1557 mmio_en = !!(result & EEH_STATE_MMIO_ENABLED);
1558
1559 if (rst_active)
1560 ret = EEH_PE_STATE_RESET;
1561 else if (dma_en && mmio_en)
1562 ret = EEH_PE_STATE_NORMAL;
1563 else if (!dma_en && !mmio_en)
1564 ret = EEH_PE_STATE_STOPPED_IO_DMA;
1565 else if (!dma_en && mmio_en)
1566 ret = EEH_PE_STATE_STOPPED_DMA;
1567 else
1568 ret = EEH_PE_STATE_UNAVAIL;
1569
1570 return ret;
1571 }
1572 EXPORT_SYMBOL_GPL(eeh_pe_get_state);
1573
eeh_pe_reenable_devices(struct eeh_pe * pe)1574 static int eeh_pe_reenable_devices(struct eeh_pe *pe)
1575 {
1576 struct eeh_dev *edev, *tmp;
1577 struct pci_dev *pdev;
1578 int ret = 0;
1579
1580 /* Restore config space */
1581 eeh_pe_restore_bars(pe);
1582
1583 /*
1584 * Reenable PCI devices as the devices passed
1585 * through are always enabled before the reset.
1586 */
1587 eeh_pe_for_each_dev(pe, edev, tmp) {
1588 pdev = eeh_dev_to_pci_dev(edev);
1589 if (!pdev)
1590 continue;
1591
1592 ret = pci_reenable_device(pdev);
1593 if (ret) {
1594 pr_warn("%s: Failure %d reenabling %s\n",
1595 __func__, ret, pci_name(pdev));
1596 return ret;
1597 }
1598 }
1599
1600 /* The PE is still in frozen state */
1601 return eeh_unfreeze_pe(pe, true);
1602 }
1603
1604 /**
1605 * eeh_pe_reset - Issue PE reset according to specified type
1606 * @pe: EEH PE
1607 * @option: reset type
1608 *
1609 * The routine is called to reset the specified PE with the
1610 * indicated type, either fundamental reset or hot reset.
1611 * PE reset is the most important part for error recovery.
1612 */
eeh_pe_reset(struct eeh_pe * pe,int option)1613 int eeh_pe_reset(struct eeh_pe *pe, int option)
1614 {
1615 int ret = 0;
1616
1617 /* Invalid PE ? */
1618 if (!pe)
1619 return -ENODEV;
1620
1621 if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
1622 return -ENOENT;
1623
1624 switch (option) {
1625 case EEH_RESET_DEACTIVATE:
1626 ret = eeh_ops->reset(pe, option);
1627 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
1628 if (ret)
1629 break;
1630
1631 ret = eeh_pe_reenable_devices(pe);
1632 break;
1633 case EEH_RESET_HOT:
1634 case EEH_RESET_FUNDAMENTAL:
1635 /*
1636 * Proactively freeze the PE to drop all MMIO access
1637 * during reset, which should be banned as it's always
1638 * cause recursive EEH error.
1639 */
1640 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
1641
1642 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
1643 ret = eeh_ops->reset(pe, option);
1644 break;
1645 default:
1646 pr_debug("%s: Unsupported option %d\n",
1647 __func__, option);
1648 ret = -EINVAL;
1649 }
1650
1651 return ret;
1652 }
1653 EXPORT_SYMBOL_GPL(eeh_pe_reset);
1654
1655 /**
1656 * eeh_pe_configure - Configure PCI bridges after PE reset
1657 * @pe: EEH PE
1658 *
1659 * The routine is called to restore the PCI config space for
1660 * those PCI devices, especially PCI bridges affected by PE
1661 * reset issued previously.
1662 */
eeh_pe_configure(struct eeh_pe * pe)1663 int eeh_pe_configure(struct eeh_pe *pe)
1664 {
1665 int ret = 0;
1666
1667 /* Invalid PE ? */
1668 if (!pe)
1669 return -ENODEV;
1670
1671 return ret;
1672 }
1673 EXPORT_SYMBOL_GPL(eeh_pe_configure);
1674
1675 /**
1676 * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
1677 * @pe: the indicated PE
1678 * @type: error type
1679 * @function: error function
1680 * @addr: address
1681 * @mask: address mask
1682 *
1683 * The routine is called to inject the specified PCI error, which
1684 * is determined by @type and @function, to the indicated PE for
1685 * testing purpose.
1686 */
eeh_pe_inject_err(struct eeh_pe * pe,int type,int func,unsigned long addr,unsigned long mask)1687 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
1688 unsigned long addr, unsigned long mask)
1689 {
1690 /* Invalid PE ? */
1691 if (!pe)
1692 return -ENODEV;
1693
1694 /* Unsupported operation ? */
1695 if (!eeh_ops || !eeh_ops->err_inject)
1696 return -ENOENT;
1697
1698 /* Check on PCI error type */
1699 if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
1700 return -EINVAL;
1701
1702 /* Check on PCI error function */
1703 if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
1704 return -EINVAL;
1705
1706 return eeh_ops->err_inject(pe, type, func, addr, mask);
1707 }
1708 EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
1709
proc_eeh_show(struct seq_file * m,void * v)1710 static int proc_eeh_show(struct seq_file *m, void *v)
1711 {
1712 if (!eeh_enabled()) {
1713 seq_printf(m, "EEH Subsystem is globally disabled\n");
1714 seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
1715 } else {
1716 seq_printf(m, "EEH Subsystem is enabled\n");
1717 seq_printf(m,
1718 "no device=%llu\n"
1719 "no device node=%llu\n"
1720 "no config address=%llu\n"
1721 "check not wanted=%llu\n"
1722 "eeh_total_mmio_ffs=%llu\n"
1723 "eeh_false_positives=%llu\n"
1724 "eeh_slot_resets=%llu\n",
1725 eeh_stats.no_device,
1726 eeh_stats.no_dn,
1727 eeh_stats.no_cfg_addr,
1728 eeh_stats.ignored_check,
1729 eeh_stats.total_mmio_ffs,
1730 eeh_stats.false_positives,
1731 eeh_stats.slot_resets);
1732 }
1733
1734 return 0;
1735 }
1736
proc_eeh_open(struct inode * inode,struct file * file)1737 static int proc_eeh_open(struct inode *inode, struct file *file)
1738 {
1739 return single_open(file, proc_eeh_show, NULL);
1740 }
1741
1742 static const struct file_operations proc_eeh_operations = {
1743 .open = proc_eeh_open,
1744 .read = seq_read,
1745 .llseek = seq_lseek,
1746 .release = single_release,
1747 };
1748
1749 #ifdef CONFIG_DEBUG_FS
eeh_enable_dbgfs_set(void * data,u64 val)1750 static int eeh_enable_dbgfs_set(void *data, u64 val)
1751 {
1752 if (val)
1753 eeh_clear_flag(EEH_FORCE_DISABLED);
1754 else
1755 eeh_add_flag(EEH_FORCE_DISABLED);
1756
1757 /* Notify the backend */
1758 if (eeh_ops->post_init)
1759 eeh_ops->post_init();
1760
1761 return 0;
1762 }
1763
eeh_enable_dbgfs_get(void * data,u64 * val)1764 static int eeh_enable_dbgfs_get(void *data, u64 *val)
1765 {
1766 if (eeh_enabled())
1767 *val = 0x1ul;
1768 else
1769 *val = 0x0ul;
1770 return 0;
1771 }
1772
eeh_freeze_dbgfs_set(void * data,u64 val)1773 static int eeh_freeze_dbgfs_set(void *data, u64 val)
1774 {
1775 eeh_max_freezes = val;
1776 return 0;
1777 }
1778
eeh_freeze_dbgfs_get(void * data,u64 * val)1779 static int eeh_freeze_dbgfs_get(void *data, u64 *val)
1780 {
1781 *val = eeh_max_freezes;
1782 return 0;
1783 }
1784
1785 DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
1786 eeh_enable_dbgfs_set, "0x%llx\n");
1787 DEFINE_SIMPLE_ATTRIBUTE(eeh_freeze_dbgfs_ops, eeh_freeze_dbgfs_get,
1788 eeh_freeze_dbgfs_set, "0x%llx\n");
1789 #endif
1790
eeh_init_proc(void)1791 static int __init eeh_init_proc(void)
1792 {
1793 if (machine_is(pseries) || machine_is(powernv)) {
1794 proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations);
1795 #ifdef CONFIG_DEBUG_FS
1796 debugfs_create_file("eeh_enable", 0600,
1797 powerpc_debugfs_root, NULL,
1798 &eeh_enable_dbgfs_ops);
1799 debugfs_create_file("eeh_max_freezes", 0600,
1800 powerpc_debugfs_root, NULL,
1801 &eeh_freeze_dbgfs_ops);
1802 #endif
1803 }
1804
1805 return 0;
1806 }
1807 __initcall(eeh_init_proc);
1808