1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32#include <asm/ptrace.h> 33 34/* Macro to make the code more readable. */ 35#ifdef CONFIG_8xx_CPU6 36#define SPRN_MI_TWC_ADDR 0x2b80 37#define SPRN_MI_RPN_ADDR 0x2d80 38#define SPRN_MD_TWC_ADDR 0x3b80 39#define SPRN_MD_RPN_ADDR 0x3d80 40 41#define MTSPR_CPU6(spr, reg, treg) \ 42 li treg, spr##_ADDR; \ 43 stw treg, 12(r0); \ 44 lwz treg, 12(r0); \ 45 mtspr spr, reg 46#else 47#define MTSPR_CPU6(spr, reg, treg) \ 48 mtspr spr, reg 49#endif 50 51/* Macro to test if an address is a kernel address */ 52#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 53#define IS_KERNEL(tmp, addr) \ 54 andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */ 55#define BRANCH_UNLESS_KERNEL(label) beq label 56#else 57#define IS_KERNEL(tmp, addr) \ 58 rlwinm tmp, addr, 16, 16, 31; \ 59 cmpli cr0, tmp, PAGE_OFFSET >> 16 60#define BRANCH_UNLESS_KERNEL(label) blt label 61#endif 62 63 64/* 65 * Value for the bits that have fixed value in RPN entries. 66 * Also used for tagging DAR for DTLBerror. 67 */ 68#ifdef CONFIG_PPC_16K_PAGES 69#define RPN_PATTERN (0x00f0 | MD_SPS16K) 70#else 71#define RPN_PATTERN 0x00f0 72#endif 73 74 __HEAD 75_ENTRY(_stext); 76_ENTRY(_start); 77 78/* MPC8xx 79 * This port was done on an MBX board with an 860. Right now I only 80 * support an ELF compressed (zImage) boot from EPPC-Bug because the 81 * code there loads up some registers before calling us: 82 * r3: ptr to board info data 83 * r4: initrd_start or if no initrd then 0 84 * r5: initrd_end - unused if r4 is 0 85 * r6: Start of command line string 86 * r7: End of command line string 87 * 88 * I decided to use conditional compilation instead of checking PVR and 89 * adding more processor specific branches around code I don't need. 90 * Since this is an embedded processor, I also appreciate any memory 91 * savings I can get. 92 * 93 * The MPC8xx does not have any BATs, but it supports large page sizes. 94 * We first initialize the MMU to support 8M byte pages, then load one 95 * entry into each of the instruction and data TLBs to map the first 96 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 97 * the "internal" processor registers before MMU_init is called. 98 * 99 * -- Dan 100 */ 101 .globl __start 102__start: 103 mr r31,r3 /* save device tree ptr */ 104 105 /* We have to turn on the MMU right away so we get cache modes 106 * set correctly. 107 */ 108 bl initial_mmu 109 110/* We now have the lower 8 Meg mapped into TLB entries, and the caches 111 * ready to work. 112 */ 113 114turn_on_mmu: 115 mfmsr r0 116 ori r0,r0,MSR_DR|MSR_IR 117 mtspr SPRN_SRR1,r0 118 lis r0,start_here@h 119 ori r0,r0,start_here@l 120 mtspr SPRN_SRR0,r0 121 SYNC 122 rfi /* enables MMU */ 123 124/* 125 * Exception entry code. This code runs with address translation 126 * turned off, i.e. using physical addresses. 127 * We assume sprg3 has the physical address of the current 128 * task's thread_struct. 129 */ 130#define EXCEPTION_PROLOG \ 131 EXCEPTION_PROLOG_0; \ 132 mfcr r10; \ 133 EXCEPTION_PROLOG_1; \ 134 EXCEPTION_PROLOG_2 135 136#define EXCEPTION_PROLOG_0 \ 137 mtspr SPRN_SPRG_SCRATCH0,r10; \ 138 mtspr SPRN_SPRG_SCRATCH1,r11 139 140#define EXCEPTION_PROLOG_1 \ 141 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 142 andi. r11,r11,MSR_PR; \ 143 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 144 beq 1f; \ 145 mfspr r11,SPRN_SPRG_THREAD; \ 146 lwz r11,THREAD_INFO-THREAD(r11); \ 147 addi r11,r11,THREAD_SIZE; \ 148 tophys(r11,r11); \ 1491: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 150 151 152#define EXCEPTION_PROLOG_2 \ 153 CLR_TOP32(r11); \ 154 stw r10,_CCR(r11); /* save registers */ \ 155 stw r12,GPR12(r11); \ 156 stw r9,GPR9(r11); \ 157 mfspr r10,SPRN_SPRG_SCRATCH0; \ 158 stw r10,GPR10(r11); \ 159 mfspr r12,SPRN_SPRG_SCRATCH1; \ 160 stw r12,GPR11(r11); \ 161 mflr r10; \ 162 stw r10,_LINK(r11); \ 163 mfspr r12,SPRN_SRR0; \ 164 mfspr r9,SPRN_SRR1; \ 165 stw r1,GPR1(r11); \ 166 stw r1,0(r11); \ 167 tovirt(r1,r11); /* set new kernel sp */ \ 168 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 169 MTMSRD(r10); /* (except for mach check in rtas) */ \ 170 stw r0,GPR0(r11); \ 171 SAVE_4GPRS(3, r11); \ 172 SAVE_2GPRS(7, r11) 173 174/* 175 * Exception exit code. 176 */ 177#define EXCEPTION_EPILOG_0 \ 178 mfspr r10,SPRN_SPRG_SCRATCH0; \ 179 mfspr r11,SPRN_SPRG_SCRATCH1 180 181/* 182 * Note: code which follows this uses cr0.eq (set if from kernel), 183 * r11, r12 (SRR0), and r9 (SRR1). 184 * 185 * Note2: once we have set r1 we are in a position to take exceptions 186 * again, and we could thus set MSR:RI at that point. 187 */ 188 189/* 190 * Exception vectors. 191 */ 192#define EXCEPTION(n, label, hdlr, xfer) \ 193 . = n; \ 194label: \ 195 EXCEPTION_PROLOG; \ 196 addi r3,r1,STACK_FRAME_OVERHEAD; \ 197 xfer(n, hdlr) 198 199#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 200 li r10,trap; \ 201 stw r10,_TRAP(r11); \ 202 li r10,MSR_KERNEL; \ 203 copyee(r10, r9); \ 204 bl tfer; \ 205i##n: \ 206 .long hdlr; \ 207 .long ret 208 209#define COPY_EE(d, s) rlwimi d,s,0,16,16 210#define NOCOPY(d, s) 211 212#define EXC_XFER_STD(n, hdlr) \ 213 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 214 ret_from_except_full) 215 216#define EXC_XFER_LITE(n, hdlr) \ 217 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 218 ret_from_except) 219 220#define EXC_XFER_EE(n, hdlr) \ 221 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 222 ret_from_except_full) 223 224#define EXC_XFER_EE_LITE(n, hdlr) \ 225 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 226 ret_from_except) 227 228/* System reset */ 229 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) 230 231/* Machine check */ 232 . = 0x200 233MachineCheck: 234 EXCEPTION_PROLOG 235 mfspr r4,SPRN_DAR 236 stw r4,_DAR(r11) 237 li r5,RPN_PATTERN 238 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 239 mfspr r5,SPRN_DSISR 240 stw r5,_DSISR(r11) 241 addi r3,r1,STACK_FRAME_OVERHEAD 242 EXC_XFER_STD(0x200, machine_check_exception) 243 244/* Data access exception. 245 * This is "never generated" by the MPC8xx. 246 */ 247 . = 0x300 248DataAccess: 249 250/* Instruction access exception. 251 * This is "never generated" by the MPC8xx. 252 */ 253 . = 0x400 254InstructionAccess: 255 256/* External interrupt */ 257 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 258 259/* Alignment exception */ 260 . = 0x600 261Alignment: 262 EXCEPTION_PROLOG 263 mfspr r4,SPRN_DAR 264 stw r4,_DAR(r11) 265 li r5,RPN_PATTERN 266 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 267 mfspr r5,SPRN_DSISR 268 stw r5,_DSISR(r11) 269 addi r3,r1,STACK_FRAME_OVERHEAD 270 EXC_XFER_EE(0x600, alignment_exception) 271 272/* Program check exception */ 273 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 274 275/* No FPU on MPC8xx. This exception is not supposed to happen. 276*/ 277 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 278 279/* Decrementer */ 280 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 281 282 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 283 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 284 285/* System call */ 286 . = 0xc00 287SystemCall: 288 EXCEPTION_PROLOG 289 EXC_XFER_EE_LITE(0xc00, DoSyscall) 290 291/* Single step - not used on 601 */ 292 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 293 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 294 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 295 296/* On the MPC8xx, this is a software emulation interrupt. It occurs 297 * for all unimplemented and illegal instructions. 298 */ 299 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 300 301 . = 0x1100 302/* 303 * For the MPC8xx, this is a software tablewalk to load the instruction 304 * TLB. The task switch loads the M_TW register with the pointer to the first 305 * level table. 306 * If we discover there is no second level table (value is zero) or if there 307 * is an invalid pte, we load that into the TLB, which causes another fault 308 * into the TLB Error interrupt where we can handle such problems. 309 * We have to use the MD_xxx registers for the tablewalk because the 310 * equivalent MI_xxx registers only perform the attribute functions. 311 */ 312 313#ifdef CONFIG_8xx_CPU15 314#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ 315 addi tmp, addr, PAGE_SIZE; \ 316 tlbie tmp; \ 317 addi tmp, addr, -PAGE_SIZE; \ 318 tlbie tmp 319#else 320#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) 321#endif 322 323InstructionTLBMiss: 324#ifdef CONFIG_8xx_CPU6 325 mtspr SPRN_SPRG_SCRATCH2, r3 326#endif 327 EXCEPTION_PROLOG_0 328 329 /* If we are faulting a kernel address, we have to use the 330 * kernel page tables. 331 */ 332#ifdef CONFIG_MODULES 333 /* Only modules will cause ITLB Misses as we always 334 * pin the first 8MB of kernel memory */ 335 mfspr r11, SPRN_SRR0 /* Get effective address of fault */ 336 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11) 337 mfcr r10 338 IS_KERNEL(r11, r11) 339 mfspr r11, SPRN_M_TW /* Get level 1 table */ 340 BRANCH_UNLESS_KERNEL(3f) 341 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3423: 343 mtcr r10 344 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 345#else 346 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 347 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) 348 mfspr r11, SPRN_M_TW /* Get level 1 table base address */ 349#endif 350 /* Insert level 1 index */ 351 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 352 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 353 354 /* Extract level 2 index */ 355 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 356 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 357 lwz r10, 0(r10) /* Get the pte */ 358 359 /* Insert the APG into the TWC from the Linux PTE. */ 360 rlwimi r11, r10, 0, 25, 26 361 /* Load the MI_TWC with the attributes for this "segment." */ 362 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */ 363 364 rlwinm r11, r10, 32-11, _PAGE_PRESENT 365 and r11, r11, r10 366 rlwimi r10, r11, 0, _PAGE_PRESENT 367 li r11, RPN_PATTERN 368 /* The Linux PTE won't go exactly into the MMU TLB. 369 * Software indicator bits 20-23 and 28 must be clear. 370 * Software indicator bits 24, 25, 26, and 27 must be 371 * set. All other Linux PTE bits control the behavior 372 * of the MMU. 373 */ 374 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */ 375 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */ 376 377 /* Restore registers */ 378#ifdef CONFIG_8xx_CPU6 379 mfspr r3, SPRN_SPRG_SCRATCH2 380#endif 381 EXCEPTION_EPILOG_0 382 rfi 383 384 . = 0x1200 385DataStoreTLBMiss: 386#ifdef CONFIG_8xx_CPU6 387 mtspr SPRN_SPRG_SCRATCH2, r3 388#endif 389 EXCEPTION_PROLOG_0 390 mfcr r10 391 392 /* If we are faulting a kernel address, we have to use the 393 * kernel page tables. 394 */ 395 mfspr r11, SPRN_MD_EPN 396 IS_KERNEL(r11, r11) 397 mfspr r11, SPRN_M_TW /* Get level 1 table */ 398 BRANCH_UNLESS_KERNEL(3f) 399 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 4003: 401 mtcr r10 402 mfspr r10, SPRN_MD_EPN 403 404 /* Insert level 1 index */ 405 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 406 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 407 408 /* We have a pte table, so load fetch the pte from the table. 409 */ 410 /* Extract level 2 index */ 411 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 412 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ 413 lwz r10, 0(r10) /* Get the pte */ 414 415 /* Insert the Guarded flag and APG into the TWC from the Linux PTE. 416 * It is bit 26-27 of both the Linux PTE and the TWC (at least 417 * I got that right :-). It will be better when we can put 418 * this into the Linux pgd/pmd and load it in the operation 419 * above. 420 */ 421 rlwimi r11, r10, 0, 26, 27 422 /* Insert the WriteThru flag into the TWC from the Linux PTE. 423 * It is bit 25 in the Linux PTE and bit 30 in the TWC 424 */ 425 rlwimi r11, r10, 32-5, 30, 30 426 MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 427 428 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 429 * We also need to know if the insn is a load/store, so: 430 * Clear _PAGE_PRESENT and load that which will 431 * trap into DTLB Error with store bit set accordinly. 432 */ 433 /* PRESENT=0x1, ACCESSED=0x20 434 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 435 * r10 = (r10 & ~PRESENT) | r11; 436 */ 437 rlwinm r11, r10, 32-11, _PAGE_PRESENT 438 and r11, r11, r10 439 rlwimi r10, r11, 0, _PAGE_PRESENT 440 /* The Linux PTE won't go exactly into the MMU TLB. 441 * Software indicator bits 22 and 28 must be clear. 442 * Software indicator bits 24, 25, 26, and 27 must be 443 * set. All other Linux PTE bits control the behavior 444 * of the MMU. 445 */ 446 li r11, RPN_PATTERN 447 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 448 rlwimi r10, r11, 0, 20, 20 /* clear 20 */ 449 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ 450 451 /* Restore registers */ 452#ifdef CONFIG_8xx_CPU6 453 mfspr r3, SPRN_SPRG_SCRATCH2 454#endif 455 mtspr SPRN_DAR, r11 /* Tag DAR */ 456 EXCEPTION_EPILOG_0 457 rfi 458 459/* This is an instruction TLB error on the MPC8xx. This could be due 460 * to many reasons, such as executing guarded memory or illegal instruction 461 * addresses. There is nothing to do but handle a big time error fault. 462 */ 463 . = 0x1300 464InstructionTLBError: 465 EXCEPTION_PROLOG 466 mr r4,r12 467 mr r5,r9 468 andis. r10,r5,0x4000 469 beq+ 1f 470 tlbie r4 471 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 4721: EXC_XFER_LITE(0x400, handle_page_fault) 473 474/* This is the data TLB error on the MPC8xx. This could be due to 475 * many reasons, including a dirty update to a pte. We bail out to 476 * a higher level function that can handle it. 477 */ 478 . = 0x1400 479DataTLBError: 480 EXCEPTION_PROLOG_0 481 mfcr r10 482 483 mfspr r11, SPRN_DAR 484 cmpwi cr0, r11, RPN_PATTERN 485 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 486DARFixed:/* Return from dcbx instruction bug workaround */ 487 EXCEPTION_PROLOG_1 488 EXCEPTION_PROLOG_2 489 mfspr r5,SPRN_DSISR 490 stw r5,_DSISR(r11) 491 mfspr r4,SPRN_DAR 492 andis. r10,r5,0x4000 493 beq+ 1f 494 tlbie r4 4951: li r10,RPN_PATTERN 496 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 497 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 498 EXC_XFER_LITE(0x300, handle_page_fault) 499 500 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 501 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 502 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 503 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 504 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 505 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 506 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 507 508/* On the MPC8xx, these next four traps are used for development 509 * support of breakpoints and such. Someday I will get around to 510 * using them. 511 */ 512 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 513 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 514 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 515 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 516 517 . = 0x2000 518 519/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 520 * by decoding the registers used by the dcbx instruction and adding them. 521 * DAR is set to the calculated address. 522 */ 523 /* define if you don't want to use self modifying code */ 524#define NO_SELF_MODIFYING_CODE 525FixupDAR:/* Entry point for dcbx workaround. */ 526 mtspr SPRN_SPRG_SCRATCH2, r10 527 /* fetch instruction from memory. */ 528 mfspr r10, SPRN_SRR0 529 IS_KERNEL(r11, r10) 530 mfspr r11, SPRN_M_TW /* Get level 1 table */ 531 BRANCH_UNLESS_KERNEL(3f) 532 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 533 /* Insert level 1 index */ 5343: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 535 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ 536 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */ 537 /* Insert level 2 index */ 538 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 539 lwz r11, 0(r11) /* Get the pte */ 540 /* concat physical page address(r11) and page offset(r10) */ 541 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 542 lwz r11,0(r11) 543/* Check if it really is a dcbx instruction. */ 544/* dcbt and dcbtst does not generate DTLB Misses/Errors, 545 * no need to include them here */ 546 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ 547 rlwinm r10, r10, 0, 21, 5 548 cmpwi cr0, r10, 2028 /* Is dcbz? */ 549 beq+ 142f 550 cmpwi cr0, r10, 940 /* Is dcbi? */ 551 beq+ 142f 552 cmpwi cr0, r10, 108 /* Is dcbst? */ 553 beq+ 144f /* Fix up store bit! */ 554 cmpwi cr0, r10, 172 /* Is dcbf? */ 555 beq+ 142f 556 cmpwi cr0, r10, 1964 /* Is icbi? */ 557 beq+ 142f 558141: mfspr r10,SPRN_SPRG_SCRATCH2 559 b DARFixed /* Nope, go back to normal TLB processing */ 560 561144: mfspr r10, SPRN_DSISR 562 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 563 mtspr SPRN_DSISR, r10 564142: /* continue, it was a dcbx, dcbi instruction. */ 565#ifndef NO_SELF_MODIFYING_CODE 566 andis. r10,r11,0x1f /* test if reg RA is r0 */ 567 li r10,modified_instr@l 568 dcbtst r0,r10 /* touch for store */ 569 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 570 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 571 ori r11,r11,532 572 stw r11,0(r10) /* store add/and instruction */ 573 dcbf 0,r10 /* flush new instr. to memory. */ 574 icbi 0,r10 /* invalidate instr. cache line */ 575 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */ 576 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */ 577 isync /* Wait until new instr is loaded from memory */ 578modified_instr: 579 .space 4 /* this is where the add instr. is stored */ 580 bne+ 143f 581 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 582143: mtdar r10 /* store faulting EA in DAR */ 583 mfspr r10,SPRN_SPRG_SCRATCH2 584 b DARFixed /* Go back to normal TLB handling */ 585#else 586 mfctr r10 587 mtdar r10 /* save ctr reg in DAR */ 588 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 589 addi r10, r10, 150f@l /* add start of table */ 590 mtctr r10 /* load ctr with jump address */ 591 xor r10, r10, r10 /* sum starts at zero */ 592 bctr /* jump into table */ 593150: 594 add r10, r10, r0 ;b 151f 595 add r10, r10, r1 ;b 151f 596 add r10, r10, r2 ;b 151f 597 add r10, r10, r3 ;b 151f 598 add r10, r10, r4 ;b 151f 599 add r10, r10, r5 ;b 151f 600 add r10, r10, r6 ;b 151f 601 add r10, r10, r7 ;b 151f 602 add r10, r10, r8 ;b 151f 603 add r10, r10, r9 ;b 151f 604 mtctr r11 ;b 154f /* r10 needs special handling */ 605 mtctr r11 ;b 153f /* r11 needs special handling */ 606 add r10, r10, r12 ;b 151f 607 add r10, r10, r13 ;b 151f 608 add r10, r10, r14 ;b 151f 609 add r10, r10, r15 ;b 151f 610 add r10, r10, r16 ;b 151f 611 add r10, r10, r17 ;b 151f 612 add r10, r10, r18 ;b 151f 613 add r10, r10, r19 ;b 151f 614 add r10, r10, r20 ;b 151f 615 add r10, r10, r21 ;b 151f 616 add r10, r10, r22 ;b 151f 617 add r10, r10, r23 ;b 151f 618 add r10, r10, r24 ;b 151f 619 add r10, r10, r25 ;b 151f 620 add r10, r10, r26 ;b 151f 621 add r10, r10, r27 ;b 151f 622 add r10, r10, r28 ;b 151f 623 add r10, r10, r29 ;b 151f 624 add r10, r10, r30 ;b 151f 625 add r10, r10, r31 626151: 627 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 628 beq 152f /* if reg RA is zero, don't add it */ 629 addi r11, r11, 150b@l /* add start of table */ 630 mtctr r11 /* load ctr with jump address */ 631 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 632 bctr /* jump into table */ 633152: 634 mfdar r11 635 mtctr r11 /* restore ctr reg from DAR */ 636 mtdar r10 /* save fault EA to DAR */ 637 mfspr r10,SPRN_SPRG_SCRATCH2 638 b DARFixed /* Go back to normal TLB handling */ 639 640 /* special handling for r10,r11 since these are modified already */ 641153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ 642 add r10, r10, r11 /* add it */ 643 mfctr r11 /* restore r11 */ 644 b 151b 645154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ 646 add r10, r10, r11 /* add it */ 647 mfctr r11 /* restore r11 */ 648 b 151b 649#endif 650 651/* 652 * This is where the main kernel code starts. 653 */ 654start_here: 655 /* ptr to current */ 656 lis r2,init_task@h 657 ori r2,r2,init_task@l 658 659 /* ptr to phys current thread */ 660 tophys(r4,r2) 661 addi r4,r4,THREAD /* init task's THREAD */ 662 mtspr SPRN_SPRG_THREAD,r4 663 664 /* stack */ 665 lis r1,init_thread_union@ha 666 addi r1,r1,init_thread_union@l 667 li r0,0 668 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 669 670 bl early_init /* We have to do this with MMU on */ 671 672/* 673 * Decide what sort of machine this is and initialize the MMU. 674 */ 675 li r3,0 676 mr r4,r31 677 bl machine_init 678 bl MMU_init 679 680/* 681 * Go back to running unmapped so we can load up new values 682 * and change to using our exception vectors. 683 * On the 8xx, all we have to do is invalidate the TLB to clear 684 * the old 8M byte TLB mappings and load the page table base register. 685 */ 686 /* The right way to do this would be to track it down through 687 * init's THREAD like the context switch code does, but this is 688 * easier......until someone changes init's static structures. 689 */ 690 lis r6, swapper_pg_dir@ha 691 tophys(r6,r6) 692#ifdef CONFIG_8xx_CPU6 693 lis r4, cpu6_errata_word@h 694 ori r4, r4, cpu6_errata_word@l 695 li r3, 0x3f80 696 stw r3, 12(r4) 697 lwz r3, 12(r4) 698#endif 699 mtspr SPRN_M_TW, r6 700 lis r4,2f@h 701 ori r4,r4,2f@l 702 tophys(r4,r4) 703 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 704 mtspr SPRN_SRR0,r4 705 mtspr SPRN_SRR1,r3 706 rfi 707/* Load up the kernel context */ 7082: 709 SYNC /* Force all PTE updates to finish */ 710 tlbia /* Clear all TLB entries */ 711 sync /* wait for tlbia/tlbie to finish */ 712 TLBSYNC /* ... on all CPUs */ 713 714 /* set up the PTE pointers for the Abatron bdiGDB. 715 */ 716 tovirt(r6,r6) 717 lis r5, abatron_pteptrs@h 718 ori r5, r5, abatron_pteptrs@l 719 stw r5, 0xf0(0) /* Must match your Abatron config file */ 720 tophys(r5,r5) 721 stw r6, 0(r5) 722 723/* Now turn on the MMU for real! */ 724 li r4,MSR_KERNEL 725 lis r3,start_kernel@h 726 ori r3,r3,start_kernel@l 727 mtspr SPRN_SRR0,r3 728 mtspr SPRN_SRR1,r4 729 rfi /* enable MMU and jump to start_kernel */ 730 731/* Set up the initial MMU state so we can do the first level of 732 * kernel initialization. This maps the first 8 MBytes of memory 1:1 733 * virtual to physical. Also, set the cache mode since that is defined 734 * by TLB entries and perform any additional mapping (like of the IMMR). 735 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 736 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by 737 * these mappings is mapped by page tables. 738 */ 739initial_mmu: 740 tlbia /* Invalidate all TLB entries */ 741/* Always pin the first 8 MB ITLB to prevent ITLB 742 misses while mucking around with SRR0/SRR1 in asm 743*/ 744 lis r8, MI_RSV4I@h 745 ori r8, r8, 0x1c00 746 747 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 748 749#ifdef CONFIG_PIN_TLB 750 lis r10, (MD_RSV4I | MD_RESETVAL)@h 751 ori r10, r10, 0x1c00 752 mr r8, r10 753#else 754 lis r10, MD_RESETVAL@h 755#endif 756#ifndef CONFIG_8xx_COPYBACK 757 oris r10, r10, MD_WTDEF@h 758#endif 759 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 760 761 /* Now map the lower 8 Meg into the TLBs. For this quick hack, 762 * we can load the instruction and data TLB registers with the 763 * same values. 764 */ 765 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 766 ori r8, r8, MI_EVALID /* Mark it valid */ 767 mtspr SPRN_MI_EPN, r8 768 mtspr SPRN_MD_EPN, r8 769 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */ 770 ori r8, r8, MI_SVALID /* Make it valid */ 771 mtspr SPRN_MI_TWC, r8 772 li r8, MI_PS8MEG /* Set 8M byte page, APG 0 */ 773 ori r8, r8, MI_SVALID /* Make it valid */ 774 mtspr SPRN_MD_TWC, r8 775 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 776 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 777 mtspr SPRN_MD_RPN, r8 778 lis r8, MI_APG_INIT@h /* Set protection modes */ 779 ori r8, r8, MI_APG_INIT@l 780 mtspr SPRN_MI_AP, r8 781 lis r8, MD_APG_INIT@h 782 ori r8, r8, MD_APG_INIT@l 783 mtspr SPRN_MD_AP, r8 784 785 /* Map another 8 MByte at the IMMR to get the processor 786 * internal registers (among other things). 787 */ 788#ifdef CONFIG_PIN_TLB 789 addi r10, r10, 0x0100 790 mtspr SPRN_MD_CTR, r10 791#endif 792 mfspr r9, 638 /* Get current IMMR */ 793 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ 794 795 mr r8, r9 /* Create vaddr for TLB */ 796 ori r8, r8, MD_EVALID /* Mark it valid */ 797 mtspr SPRN_MD_EPN, r8 798 li r8, MD_PS8MEG /* Set 8M byte page */ 799 ori r8, r8, MD_SVALID /* Make it valid */ 800 mtspr SPRN_MD_TWC, r8 801 mr r8, r9 /* Create paddr for TLB */ 802 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 803 mtspr SPRN_MD_RPN, r8 804 805#ifdef CONFIG_PIN_TLB 806 /* Map two more 8M kernel data pages. 807 */ 808 addi r10, r10, 0x0100 809 mtspr SPRN_MD_CTR, r10 810 811 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 812 addis r8, r8, 0x0080 /* Add 8M */ 813 ori r8, r8, MI_EVALID /* Mark it valid */ 814 mtspr SPRN_MD_EPN, r8 815 li r9, MI_PS8MEG /* Set 8M byte page */ 816 ori r9, r9, MI_SVALID /* Make it valid */ 817 mtspr SPRN_MD_TWC, r9 818 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 819 addis r11, r11, 0x0080 /* Add 8M */ 820 mtspr SPRN_MD_RPN, r11 821 822 addi r10, r10, 0x0100 823 mtspr SPRN_MD_CTR, r10 824 825 addis r8, r8, 0x0080 /* Add 8M */ 826 mtspr SPRN_MD_EPN, r8 827 mtspr SPRN_MD_TWC, r9 828 addis r11, r11, 0x0080 /* Add 8M */ 829 mtspr SPRN_MD_RPN, r11 830#endif 831 832 /* Since the cache is enabled according to the information we 833 * just loaded into the TLB, invalidate and enable the caches here. 834 * We should probably check/set other modes....later. 835 */ 836 lis r8, IDC_INVALL@h 837 mtspr SPRN_IC_CST, r8 838 mtspr SPRN_DC_CST, r8 839 lis r8, IDC_ENABLE@h 840 mtspr SPRN_IC_CST, r8 841#ifdef CONFIG_8xx_COPYBACK 842 mtspr SPRN_DC_CST, r8 843#else 844 /* For a debug option, I left this here to easily enable 845 * the write through cache mode 846 */ 847 lis r8, DC_SFWT@h 848 mtspr SPRN_DC_CST, r8 849 lis r8, IDC_ENABLE@h 850 mtspr SPRN_DC_CST, r8 851#endif 852 blr 853 854 855/* 856 * Set up to use a given MMU context. 857 * r3 is context number, r4 is PGD pointer. 858 * 859 * We place the physical address of the new task page directory loaded 860 * into the MMU base register, and set the ASID compare register with 861 * the new "context." 862 */ 863_GLOBAL(set_context) 864 865#ifdef CONFIG_BDI_SWITCH 866 /* Context switch the PTE pointer for the Abatron BDI2000. 867 * The PGDIR is passed as second argument. 868 */ 869 lis r5, KERNELBASE@h 870 lwz r5, 0xf0(r5) 871 stw r4, 0x4(r5) 872#endif 873 874 /* Register M_TW will contain base address of level 1 table minus the 875 * lower part of the kernel PGDIR base address, so that all accesses to 876 * level 1 table are done relative to lower part of kernel PGDIR base 877 * address. 878 */ 879 li r5, (swapper_pg_dir-PAGE_OFFSET)@l 880 sub r4, r4, r5 881 tophys (r4, r4) 882#ifdef CONFIG_8xx_CPU6 883 lis r6, cpu6_errata_word@h 884 ori r6, r6, cpu6_errata_word@l 885 li r7, 0x3f80 886 stw r7, 12(r6) 887 lwz r7, 12(r6) 888#endif 889 mtspr SPRN_M_TW, r4 /* Update pointeur to level 1 table */ 890#ifdef CONFIG_8xx_CPU6 891 li r7, 0x3380 892 stw r7, 12(r6) 893 lwz r7, 12(r6) 894#endif 895 mtspr SPRN_M_CASID, r3 /* Update context */ 896 SYNC 897 blr 898 899#ifdef CONFIG_8xx_CPU6 900/* It's here because it is unique to the 8xx. 901 * It is important we get called with interrupts disabled. I used to 902 * do that, but it appears that all code that calls this already had 903 * interrupt disabled. 904 */ 905 .globl set_dec_cpu6 906set_dec_cpu6: 907 lis r7, cpu6_errata_word@h 908 ori r7, r7, cpu6_errata_word@l 909 li r4, 0x2c00 910 stw r4, 8(r7) 911 lwz r4, 8(r7) 912 mtspr 22, r3 /* Update Decrementer */ 913 SYNC 914 blr 915#endif 916 917/* 918 * We put a few things here that have to be page-aligned. 919 * This stuff goes at the beginning of the data segment, 920 * which is page-aligned. 921 */ 922 .data 923 .globl sdata 924sdata: 925 .globl empty_zero_page 926 .align PAGE_SHIFT 927empty_zero_page: 928 .space PAGE_SIZE 929 930 .globl swapper_pg_dir 931swapper_pg_dir: 932 .space PGD_TABLE_SIZE 933 934/* Room for two PTE table poiners, usually the kernel and current user 935 * pointer to their respective root page table (pgdir). 936 */ 937abatron_pteptrs: 938 .space 8 939 940#ifdef CONFIG_8xx_CPU6 941 .globl cpu6_errata_word 942cpu6_errata_word: 943 .space 16 944#endif 945 946