1/* 2 * Low-level SLB routines 3 * 4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM 5 * 6 * Based on earlier C version: 7 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com 8 * Copyright (c) 2001 Dave Engebretsen 9 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17#include <asm/processor.h> 18#include <asm/ppc_asm.h> 19#include <asm/asm-offsets.h> 20#include <asm/cputable.h> 21#include <asm/page.h> 22#include <asm/mmu.h> 23#include <asm/pgtable.h> 24#include <asm/firmware.h> 25 26/* void slb_allocate_realmode(unsigned long ea); 27 * 28 * Create an SLB entry for the given EA (user or kernel). 29 * r3 = faulting address, r13 = PACA 30 * r9, r10, r11 are clobbered by this function 31 * No other registers are examined or changed. 32 */ 33_GLOBAL(slb_allocate_realmode) 34 /* 35 * check for bad kernel/user address 36 * (ea & ~REGION_MASK) >= PGTABLE_RANGE 37 */ 38 rldicr. r9,r3,4,(63 - PGTABLE_EADDR_SIZE - 4) 39 bne- 8f 40 41 srdi r9,r3,60 /* get region */ 42 srdi r10,r3,SID_SHIFT /* get esid */ 43 cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */ 44 45 /* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */ 46 blt cr7,0f /* user or kernel? */ 47 48 /* kernel address: proto-VSID = ESID */ 49 /* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but 50 * this code will generate the protoVSID 0xfffffffff for the 51 * top segment. That's ok, the scramble below will translate 52 * it to VSID 0, which is reserved as a bad VSID - one which 53 * will never have any pages in it. */ 54 55 /* Check if hitting the linear mapping or some other kernel space 56 */ 57 bne cr7,1f 58 59 /* Linear mapping encoding bits, the "li" instruction below will 60 * be patched by the kernel at boot 61 */ 62.globl slb_miss_kernel_load_linear 63slb_miss_kernel_load_linear: 64 li r11,0 65 /* 66 * context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1 67 * r9 = region id. 68 */ 69 addis r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha 70 addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l 71 72 73BEGIN_FTR_SECTION 74 b slb_finish_load 75END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT) 76 b slb_finish_load_1T 77 781: 79#ifdef CONFIG_SPARSEMEM_VMEMMAP 80 /* Check virtual memmap region. To be patches at kernel boot */ 81 cmpldi cr0,r9,0xf 82 bne 1f 83.globl slb_miss_kernel_load_vmemmap 84slb_miss_kernel_load_vmemmap: 85 li r11,0 86 b 6f 871: 88#endif /* CONFIG_SPARSEMEM_VMEMMAP */ 89 90 /* vmalloc mapping gets the encoding from the PACA as the mapping 91 * can be demoted from 64K -> 4K dynamically on some machines 92 */ 93 clrldi r11,r10,48 94 cmpldi r11,(VMALLOC_SIZE >> 28) - 1 95 bgt 5f 96 lhz r11,PACAVMALLOCSLLP(r13) 97 b 6f 985: 99 /* IO mapping */ 100.globl slb_miss_kernel_load_io 101slb_miss_kernel_load_io: 102 li r11,0 1036: 104 /* 105 * context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1 106 * r9 = region id. 107 */ 108 addis r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha 109 addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l 110 111BEGIN_FTR_SECTION 112 b slb_finish_load 113END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT) 114 b slb_finish_load_1T 115 1160: /* 117 * For userspace addresses, make sure this is region 0. 118 */ 119 cmpdi r9, 0 120 bne 8f 121 122 /* when using slices, we extract the psize off the slice bitmaps 123 * and then we need to get the sllp encoding off the mmu_psize_defs 124 * array. 125 * 126 * XXX This is a bit inefficient especially for the normal case, 127 * so we should try to implement a fast path for the standard page 128 * size using the old sllp value so we avoid the array. We cannot 129 * really do dynamic patching unfortunately as processes might flip 130 * between 4k and 64k standard page size 131 */ 132#ifdef CONFIG_PPC_MM_SLICES 133 /* r10 have esid */ 134 cmpldi r10,16 135 /* below SLICE_LOW_TOP */ 136 blt 5f 137 /* 138 * Handle hpsizes, 139 * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index 140 */ 141 srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */ 142 addi r9,r11,PACAHIGHSLICEPSIZE 143 lbzx r9,r13,r9 /* r9 is hpsizes[r11] */ 144 /* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */ 145 rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63 146 b 6f 147 1485: 149 /* 150 * Handle lpsizes 151 * r9 is get_paca()->context.low_slices_psize, r11 is index 152 */ 153 ld r9,PACALOWSLICESPSIZE(r13) 154 mr r11,r10 1556: 156 sldi r11,r11,2 /* index * 4 */ 157 /* Extract the psize and multiply to get an array offset */ 158 srd r9,r9,r11 159 andi. r9,r9,0xf 160 mulli r9,r9,MMUPSIZEDEFSIZE 161 162 /* Now get to the array and obtain the sllp 163 */ 164 ld r11,PACATOC(r13) 165 ld r11,mmu_psize_defs@got(r11) 166 add r11,r11,r9 167 ld r11,MMUPSIZESLLP(r11) 168 ori r11,r11,SLB_VSID_USER 169#else 170 /* paca context sllp already contains the SLB_VSID_USER bits */ 171 lhz r11,PACACONTEXTSLLP(r13) 172#endif /* CONFIG_PPC_MM_SLICES */ 173 174 ld r9,PACACONTEXTID(r13) 175BEGIN_FTR_SECTION 176 cmpldi r10,0x1000 177 bge slb_finish_load_1T 178END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) 179 b slb_finish_load 180 1818: /* invalid EA */ 182 /* 183 * It's possible the bad EA is too large to fit in the SLB cache, which 184 * would mean we'd fail to invalidate it on context switch. So mark the 185 * SLB cache as full so we force a full flush. We also set cr7+eq to 186 * mark the address as a kernel address, so slb_finish_load() skips 187 * trying to insert it into the SLB cache. 188 */ 189 li r9,SLB_CACHE_ENTRIES + 1 190 sth r9,PACASLBCACHEPTR(r13) 191 crset 4*cr7+eq 192 li r10,0 /* BAD_VSID */ 193 li r9,0 /* BAD_VSID */ 194 li r11,SLB_VSID_USER /* flags don't much matter */ 195 b slb_finish_load 196 197#ifdef __DISABLED__ 198 199/* void slb_allocate_user(unsigned long ea); 200 * 201 * Create an SLB entry for the given EA (user or kernel). 202 * r3 = faulting address, r13 = PACA 203 * r9, r10, r11 are clobbered by this function 204 * No other registers are examined or changed. 205 * 206 * It is called with translation enabled in order to be able to walk the 207 * page tables. This is not currently used. 208 */ 209_GLOBAL(slb_allocate_user) 210 /* r3 = faulting address */ 211 srdi r10,r3,28 /* get esid */ 212 213 crset 4*cr7+lt /* set "user" flag for later */ 214 215 /* check if we fit in the range covered by the pagetables*/ 216 srdi. r9,r3,PGTABLE_EADDR_SIZE 217 crnot 4*cr0+eq,4*cr0+eq 218 beqlr 219 220 /* now we need to get to the page tables in order to get the page 221 * size encoding from the PMD. In the future, we'll be able to deal 222 * with 1T segments too by getting the encoding from the PGD instead 223 */ 224 ld r9,PACAPGDIR(r13) 225 cmpldi cr0,r9,0 226 beqlr 227 rlwinm r11,r10,8,25,28 228 ldx r9,r9,r11 /* get pgd_t */ 229 cmpldi cr0,r9,0 230 beqlr 231 rlwinm r11,r10,3,17,28 232 ldx r9,r9,r11 /* get pmd_t */ 233 cmpldi cr0,r9,0 234 beqlr 235 236 /* build vsid flags */ 237 andi. r11,r9,SLB_VSID_LLP 238 ori r11,r11,SLB_VSID_USER 239 240 /* get context to calculate proto-VSID */ 241 ld r9,PACACONTEXTID(r13) 242 /* fall through slb_finish_load */ 243 244#endif /* __DISABLED__ */ 245 246 247/* 248 * Finish loading of an SLB entry and return 249 * 250 * r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET 251 */ 252slb_finish_load: 253 rldimi r10,r9,ESID_BITS,0 254 ASM_VSID_SCRAMBLE(r10,r9,256M) 255 /* 256 * bits above VSID_BITS_256M need to be ignored from r10 257 * also combine VSID and flags 258 */ 259 rldimi r11,r10,SLB_VSID_SHIFT,(64 - (SLB_VSID_SHIFT + VSID_BITS_256M)) 260 261 /* r3 = EA, r11 = VSID data */ 262 /* 263 * Find a slot, round robin. Previously we tried to find a 264 * free slot first but that took too long. Unfortunately we 265 * dont have any LRU information to help us choose a slot. 266 */ 267 2687: ld r10,PACASTABRR(r13) 269 addi r10,r10,1 270 /* This gets soft patched on boot. */ 271.globl slb_compare_rr_to_size 272slb_compare_rr_to_size: 273 cmpldi r10,0 274 275 blt+ 4f 276 li r10,SLB_NUM_BOLTED 277 2784: 279 std r10,PACASTABRR(r13) 280 2813: 282 rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */ 283 oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */ 284 285 /* r3 = ESID data, r11 = VSID data */ 286 287 /* 288 * No need for an isync before or after this slbmte. The exception 289 * we enter with and the rfid we exit with are context synchronizing. 290 */ 291 slbmte r11,r10 292 293 /* we're done for kernel addresses */ 294 crclr 4*cr0+eq /* set result to "success" */ 295 bgelr cr7 296 297 /* Update the slb cache */ 298 lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */ 299 cmpldi r3,SLB_CACHE_ENTRIES 300 bge 1f 301 302 /* still room in the slb cache */ 303 sldi r11,r3,2 /* r11 = offset * sizeof(u32) */ 304 srdi r10,r10,28 /* get the 36 bits of the ESID */ 305 add r11,r11,r13 /* r11 = (u32 *)paca + offset */ 306 stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */ 307 addi r3,r3,1 /* offset++ */ 308 b 2f 3091: /* offset >= SLB_CACHE_ENTRIES */ 310 li r3,SLB_CACHE_ENTRIES+1 3112: 312 sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */ 313 crclr 4*cr0+eq /* set result to "success" */ 314 blr 315 316/* 317 * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return. 318 * 319 * r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9 320 */ 321slb_finish_load_1T: 322 srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */ 323 rldimi r10,r9,ESID_BITS_1T,0 324 ASM_VSID_SCRAMBLE(r10,r9,1T) 325 /* 326 * bits above VSID_BITS_1T need to be ignored from r10 327 * also combine VSID and flags 328 */ 329 rldimi r11,r10,SLB_VSID_SHIFT_1T,(64 - (SLB_VSID_SHIFT_1T + VSID_BITS_1T)) 330 li r10,MMU_SEGSIZE_1T 331 rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */ 332 333 /* r3 = EA, r11 = VSID data */ 334 clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */ 335 b 7b 336 337