1/* 2 * arch/s390/kernel/base.S 3 * 4 * Copyright IBM Corp. 2006, 2007 5 * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com> 6 * Michael Holzheu <holzheu@de.ibm.com> 7 */ 8 9#include <linux/linkage.h> 10#include <asm/asm-offsets.h> 11#include <asm/nospec-insn.h> 12#include <asm/ptrace.h> 13#include <asm/sigp.h> 14 15 GEN_BR_THUNK %r9 16 GEN_BR_THUNK %r14 17 18ENTRY(s390_base_mcck_handler) 19 basr %r13,0 200: lg %r15,__LC_PANIC_STACK # load panic stack 21 aghi %r15,-STACK_FRAME_OVERHEAD 22 larl %r1,s390_base_mcck_handler_fn 23 lg %r9,0(%r1) 24 ltgr %r9,%r9 25 jz 1f 26 BASR_EX %r14,%r9 271: la %r1,4095 28 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1) 29 lpswe __LC_MCK_OLD_PSW 30 31 .section .bss 32 .align 8 33 .globl s390_base_mcck_handler_fn 34s390_base_mcck_handler_fn: 35 .quad 0 36 .previous 37 38ENTRY(s390_base_ext_handler) 39 stmg %r0,%r15,__LC_SAVE_AREA_ASYNC 40 basr %r13,0 410: aghi %r15,-STACK_FRAME_OVERHEAD 42 larl %r1,s390_base_ext_handler_fn 43 lg %r9,0(%r1) 44 ltgr %r9,%r9 45 jz 1f 46 BASR_EX %r14,%r9 471: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC 48 ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit 49 lpswe __LC_EXT_OLD_PSW 50 51 .section .bss 52 .align 8 53 .globl s390_base_ext_handler_fn 54s390_base_ext_handler_fn: 55 .quad 0 56 .previous 57 58ENTRY(s390_base_pgm_handler) 59 stmg %r0,%r15,__LC_SAVE_AREA_SYNC 60 basr %r13,0 610: aghi %r15,-STACK_FRAME_OVERHEAD 62 larl %r1,s390_base_pgm_handler_fn 63 lg %r9,0(%r1) 64 ltgr %r9,%r9 65 jz 1f 66 BASR_EX %r14,%r9 67 lmg %r0,%r15,__LC_SAVE_AREA_SYNC 68 lpswe __LC_PGM_OLD_PSW 691: lpswe disabled_wait_psw-0b(%r13) 70 71 .align 8 72disabled_wait_psw: 73 .quad 0x0002000180000000,0x0000000000000000 + s390_base_pgm_handler 74 75 .section .bss 76 .align 8 77 .globl s390_base_pgm_handler_fn 78s390_base_pgm_handler_fn: 79 .quad 0 80 .previous 81 82# 83# Calls diag 308 subcode 1 and continues execution 84# 85ENTRY(diag308_reset) 86 larl %r4,.Lctlregs # Save control registers 87 stctg %c0,%c15,0(%r4) 88 lg %r2,0(%r4) # Disable lowcore protection 89 nilh %r2,0xefff 90 larl %r4,.Lctlreg0 91 stg %r2,0(%r4) 92 lctlg %c0,%c0,0(%r4) 93 larl %r4,.Lfpctl # Floating point control register 94 stfpc 0(%r4) 95 larl %r4,.Lprefix # Save prefix register 96 stpx 0(%r4) 97 larl %r4,.Lprefix_zero # Set prefix register to 0 98 spx 0(%r4) 99 larl %r4,.Lcontinue_psw # Save PSW flags 100 epsw %r2,%r3 101 stm %r2,%r3,0(%r4) 102 larl %r4,.Lrestart_psw # Setup restart PSW at absolute 0 103 lghi %r3,0 104 lg %r4,0(%r4) # Save PSW 105 sturg %r4,%r3 # Use sturg, because of large pages 106 lghi %r1,1 107 lghi %r0,0 108 diag %r0,%r1,0x308 109.Lrestart_part2: 110 lhi %r0,0 # Load r0 with zero 111 lhi %r1,2 # Use mode 2 = ESAME (dump) 112 sigp %r1,%r0,SIGP_SET_ARCHITECTURE # Switch to ESAME mode 113 sam64 # Switch to 64 bit addressing mode 114 larl %r4,.Lctlregs # Restore control registers 115 lctlg %c0,%c15,0(%r4) 116 larl %r4,.Lfpctl # Restore floating point ctl register 117 lfpc 0(%r4) 118 larl %r4,.Lprefix # Restore prefix register 119 spx 0(%r4) 120 larl %r4,.Lcontinue_psw # Restore PSW flags 121 lpswe 0(%r4) 122.Lcontinue: 123 BR_EX %r14 124.align 16 125.Lrestart_psw: 126 .long 0x00080000,0x80000000 + .Lrestart_part2 127 128 .section .data..nosave,"aw",@progbits 129.align 8 130.Lcontinue_psw: 131 .quad 0,.Lcontinue 132 .previous 133 134 .section .bss 135.align 8 136.Lctlreg0: 137 .quad 0 138.Lctlregs: 139 .rept 16 140 .quad 0 141 .endr 142.Lfpctl: 143 .long 0 144.Lprefix: 145 .long 0 146.Lprefix_zero: 147 .long 0 148 .previous 149