1 /*
2 * Renesas System Solutions Asia Pte. Ltd - Migo-R
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/interrupt.h>
13 #include <linux/input.h>
14 #include <linux/input/sh_keysc.h>
15 #include <linux/mmc/host.h>
16 #include <linux/mmc/sh_mobile_sdhi.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/mfd/tmio.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/i2c.h>
21 #include <linux/regulator/fixed.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/smc91x.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/gpio.h>
27 #include <linux/videodev2.h>
28 #include <linux/sh_intc.h>
29 #include <video/sh_mobile_lcdc.h>
30 #include <media/sh_mobile_ceu.h>
31 #include <media/ov772x.h>
32 #include <media/soc_camera.h>
33 #include <media/tw9910.h>
34 #include <asm/clock.h>
35 #include <asm/machvec.h>
36 #include <asm/io.h>
37 #include <asm/suspend.h>
38 #include <mach/migor.h>
39 #include <cpu/sh7722.h>
40
41 /* Address IRQ Size Bus Description
42 * 0x00000000 64MB 16 NOR Flash (SP29PL256N)
43 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
44 * 0x10000000 IRQ0 16 Ethernet (SMC91C111)
45 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
46 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
47 */
48
49 static struct smc91x_platdata smc91x_info = {
50 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
51 };
52
53 static struct resource smc91x_eth_resources[] = {
54 [0] = {
55 .name = "SMC91C111" ,
56 .start = 0x10000300,
57 .end = 0x1000030f,
58 .flags = IORESOURCE_MEM,
59 },
60 [1] = {
61 .start = evt2irq(0x600), /* IRQ0 */
62 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
63 },
64 };
65
66 static struct platform_device smc91x_eth_device = {
67 .name = "smc91x",
68 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
69 .resource = smc91x_eth_resources,
70 .dev = {
71 .platform_data = &smc91x_info,
72 },
73 };
74
75 static struct sh_keysc_info sh_keysc_info = {
76 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
77 .scan_timing = 3,
78 .delay = 5,
79 .keycodes = {
80 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
81 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
82 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
83 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
84 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
85 },
86 };
87
88 static struct resource sh_keysc_resources[] = {
89 [0] = {
90 .start = 0x044b0000,
91 .end = 0x044b000f,
92 .flags = IORESOURCE_MEM,
93 },
94 [1] = {
95 .start = evt2irq(0xbe0),
96 .flags = IORESOURCE_IRQ,
97 },
98 };
99
100 static struct platform_device sh_keysc_device = {
101 .name = "sh_keysc",
102 .id = 0, /* "keysc0" clock */
103 .num_resources = ARRAY_SIZE(sh_keysc_resources),
104 .resource = sh_keysc_resources,
105 .dev = {
106 .platform_data = &sh_keysc_info,
107 },
108 };
109
110 static struct mtd_partition migor_nor_flash_partitions[] =
111 {
112 {
113 .name = "uboot",
114 .offset = 0,
115 .size = (1 * 1024 * 1024),
116 .mask_flags = MTD_WRITEABLE, /* Read-only */
117 },
118 {
119 .name = "rootfs",
120 .offset = MTDPART_OFS_APPEND,
121 .size = (15 * 1024 * 1024),
122 },
123 {
124 .name = "other",
125 .offset = MTDPART_OFS_APPEND,
126 .size = MTDPART_SIZ_FULL,
127 },
128 };
129
130 static struct physmap_flash_data migor_nor_flash_data = {
131 .width = 2,
132 .parts = migor_nor_flash_partitions,
133 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
134 };
135
136 static struct resource migor_nor_flash_resources[] = {
137 [0] = {
138 .name = "NOR Flash",
139 .start = 0x00000000,
140 .end = 0x03ffffff,
141 .flags = IORESOURCE_MEM,
142 }
143 };
144
145 static struct platform_device migor_nor_flash_device = {
146 .name = "physmap-flash",
147 .resource = migor_nor_flash_resources,
148 .num_resources = ARRAY_SIZE(migor_nor_flash_resources),
149 .dev = {
150 .platform_data = &migor_nor_flash_data,
151 },
152 };
153
154 static struct mtd_partition migor_nand_flash_partitions[] = {
155 {
156 .name = "nanddata1",
157 .offset = 0x0,
158 .size = 512 * 1024 * 1024,
159 },
160 {
161 .name = "nanddata2",
162 .offset = MTDPART_OFS_APPEND,
163 .size = 512 * 1024 * 1024,
164 },
165 };
166
migor_nand_flash_cmd_ctl(struct mtd_info * mtd,int cmd,unsigned int ctrl)167 static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
168 unsigned int ctrl)
169 {
170 struct nand_chip *chip = mtd->priv;
171
172 if (cmd == NAND_CMD_NONE)
173 return;
174
175 if (ctrl & NAND_CLE)
176 writeb(cmd, chip->IO_ADDR_W + 0x00400000);
177 else if (ctrl & NAND_ALE)
178 writeb(cmd, chip->IO_ADDR_W + 0x00800000);
179 else
180 writeb(cmd, chip->IO_ADDR_W);
181 }
182
migor_nand_flash_ready(struct mtd_info * mtd)183 static int migor_nand_flash_ready(struct mtd_info *mtd)
184 {
185 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
186 }
187
188 static struct platform_nand_data migor_nand_flash_data = {
189 .chip = {
190 .nr_chips = 1,
191 .partitions = migor_nand_flash_partitions,
192 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
193 .chip_delay = 20,
194 },
195 .ctrl = {
196 .dev_ready = migor_nand_flash_ready,
197 .cmd_ctrl = migor_nand_flash_cmd_ctl,
198 },
199 };
200
201 static struct resource migor_nand_flash_resources[] = {
202 [0] = {
203 .name = "NAND Flash",
204 .start = 0x18000000,
205 .end = 0x18ffffff,
206 .flags = IORESOURCE_MEM,
207 },
208 };
209
210 static struct platform_device migor_nand_flash_device = {
211 .name = "gen_nand",
212 .resource = migor_nand_flash_resources,
213 .num_resources = ARRAY_SIZE(migor_nand_flash_resources),
214 .dev = {
215 .platform_data = &migor_nand_flash_data,
216 }
217 };
218
219 static const struct fb_videomode migor_lcd_modes[] = {
220 {
221 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
222 .name = "LB070WV1",
223 .xres = 800,
224 .yres = 480,
225 .left_margin = 64,
226 .right_margin = 16,
227 .hsync_len = 120,
228 .sync = 0,
229 #elif defined(CONFIG_SH_MIGOR_QVGA)
230 .name = "PH240320T",
231 .xres = 320,
232 .yres = 240,
233 .left_margin = 0,
234 .right_margin = 16,
235 .hsync_len = 8,
236 .sync = FB_SYNC_HOR_HIGH_ACT,
237 #endif
238 .upper_margin = 1,
239 .lower_margin = 17,
240 .vsync_len = 2,
241 },
242 };
243
244 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
245 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
246 .clock_source = LCDC_CLK_BUS,
247 .ch[0] = {
248 .chan = LCDC_CHAN_MAINLCD,
249 .fourcc = V4L2_PIX_FMT_RGB565,
250 .interface_type = RGB16,
251 .clock_divider = 2,
252 .lcd_modes = migor_lcd_modes,
253 .num_modes = ARRAY_SIZE(migor_lcd_modes),
254 .panel_cfg = { /* 7.0 inch */
255 .width = 152,
256 .height = 91,
257 },
258 }
259 #elif defined(CONFIG_SH_MIGOR_QVGA)
260 .clock_source = LCDC_CLK_PERIPHERAL,
261 .ch[0] = {
262 .chan = LCDC_CHAN_MAINLCD,
263 .fourcc = V4L2_PIX_FMT_RGB565,
264 .interface_type = SYS16A,
265 .clock_divider = 10,
266 .lcd_modes = migor_lcd_modes,
267 .num_modes = ARRAY_SIZE(migor_lcd_modes),
268 .panel_cfg = {
269 .width = 49, /* 2.4 inch */
270 .height = 37,
271 .setup_sys = migor_lcd_qvga_setup,
272 },
273 .sys_bus_cfg = {
274 .ldmt2r = 0x06000a09,
275 .ldmt3r = 0x180e3418,
276 /* set 1s delay to encourage fsync() */
277 .deferred_io_msec = 1000,
278 },
279 }
280 #endif
281 };
282
283 static struct resource migor_lcdc_resources[] = {
284 [0] = {
285 .name = "LCDC",
286 .start = 0xfe940000, /* P4-only space */
287 .end = 0xfe942fff,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = evt2irq(0x580),
292 .flags = IORESOURCE_IRQ,
293 },
294 };
295
296 static struct platform_device migor_lcdc_device = {
297 .name = "sh_mobile_lcdc_fb",
298 .num_resources = ARRAY_SIZE(migor_lcdc_resources),
299 .resource = migor_lcdc_resources,
300 .dev = {
301 .platform_data = &sh_mobile_lcdc_info,
302 },
303 };
304
305 static struct clk *camera_clk;
306 static DEFINE_MUTEX(camera_lock);
307
camera_power_on(int is_tw)308 static void camera_power_on(int is_tw)
309 {
310 mutex_lock(&camera_lock);
311
312 /* Use 10 MHz VIO_CKO instead of 24 MHz to work
313 * around signal quality issues on Panel Board V2.1.
314 */
315 camera_clk = clk_get(NULL, "video_clk");
316 clk_set_rate(camera_clk, 10000000);
317 clk_enable(camera_clk); /* start VIO_CKO */
318
319 /* use VIO_RST to take camera out of reset */
320 mdelay(10);
321 if (is_tw) {
322 gpio_set_value(GPIO_PTT2, 0);
323 gpio_set_value(GPIO_PTT0, 0);
324 } else {
325 gpio_set_value(GPIO_PTT0, 1);
326 }
327 gpio_set_value(GPIO_PTT3, 0);
328 mdelay(10);
329 gpio_set_value(GPIO_PTT3, 1);
330 mdelay(10); /* wait to let chip come out of reset */
331 }
332
camera_power_off(void)333 static void camera_power_off(void)
334 {
335 clk_disable(camera_clk); /* stop VIO_CKO */
336 clk_put(camera_clk);
337
338 gpio_set_value(GPIO_PTT3, 0);
339 mutex_unlock(&camera_lock);
340 }
341
ov7725_power(struct device * dev,int mode)342 static int ov7725_power(struct device *dev, int mode)
343 {
344 if (mode)
345 camera_power_on(0);
346 else
347 camera_power_off();
348
349 return 0;
350 }
351
tw9910_power(struct device * dev,int mode)352 static int tw9910_power(struct device *dev, int mode)
353 {
354 if (mode)
355 camera_power_on(1);
356 else
357 camera_power_off();
358
359 return 0;
360 }
361
362 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
363 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
364 };
365
366 static struct resource migor_ceu_resources[] = {
367 [0] = {
368 .name = "CEU",
369 .start = 0xfe910000,
370 .end = 0xfe91009f,
371 .flags = IORESOURCE_MEM,
372 },
373 [1] = {
374 .start = evt2irq(0x880),
375 .flags = IORESOURCE_IRQ,
376 },
377 [2] = {
378 /* place holder for contiguous memory */
379 },
380 };
381
382 static struct platform_device migor_ceu_device = {
383 .name = "sh_mobile_ceu",
384 .id = 0, /* "ceu0" clock */
385 .num_resources = ARRAY_SIZE(migor_ceu_resources),
386 .resource = migor_ceu_resources,
387 .dev = {
388 .platform_data = &sh_mobile_ceu_info,
389 },
390 };
391
392 /* Fixed 3.3V regulator to be used by SDHI0 */
393 static struct regulator_consumer_supply fixed3v3_power_consumers[] =
394 {
395 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
396 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
397 };
398
399 static struct resource sdhi_cn9_resources[] = {
400 [0] = {
401 .name = "SDHI",
402 .start = 0x04ce0000,
403 .end = 0x04ce00ff,
404 .flags = IORESOURCE_MEM,
405 },
406 [1] = {
407 .start = evt2irq(0xe80),
408 .flags = IORESOURCE_IRQ,
409 },
410 };
411
412 static struct tmio_mmc_data sh7724_sdhi_data = {
413 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
414 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
415 .capabilities = MMC_CAP_SDIO_IRQ,
416 };
417
418 static struct platform_device sdhi_cn9_device = {
419 .name = "sh_mobile_sdhi",
420 .num_resources = ARRAY_SIZE(sdhi_cn9_resources),
421 .resource = sdhi_cn9_resources,
422 .dev = {
423 .platform_data = &sh7724_sdhi_data,
424 },
425 };
426
427 static struct i2c_board_info migor_i2c_devices[] = {
428 {
429 I2C_BOARD_INFO("rs5c372b", 0x32),
430 },
431 {
432 I2C_BOARD_INFO("migor_ts", 0x51),
433 .irq = evt2irq(0x6c0), /* IRQ6 */
434 },
435 {
436 I2C_BOARD_INFO("wm8978", 0x1a),
437 },
438 };
439
440 static struct i2c_board_info migor_i2c_camera[] = {
441 {
442 I2C_BOARD_INFO("ov772x", 0x21),
443 },
444 {
445 I2C_BOARD_INFO("tw9910", 0x45),
446 },
447 };
448
449 static struct ov772x_camera_info ov7725_info;
450
451 static struct soc_camera_link ov7725_link = {
452 .power = ov7725_power,
453 .board_info = &migor_i2c_camera[0],
454 .i2c_adapter_id = 0,
455 .priv = &ov7725_info,
456 };
457
458 static struct tw9910_video_info tw9910_info = {
459 .buswidth = SOCAM_DATAWIDTH_8,
460 .mpout = TW9910_MPO_FIELD,
461 };
462
463 static struct soc_camera_link tw9910_link = {
464 .power = tw9910_power,
465 .board_info = &migor_i2c_camera[1],
466 .i2c_adapter_id = 0,
467 .priv = &tw9910_info,
468 };
469
470 static struct platform_device migor_camera[] = {
471 {
472 .name = "soc-camera-pdrv",
473 .id = 0,
474 .dev = {
475 .platform_data = &ov7725_link,
476 },
477 }, {
478 .name = "soc-camera-pdrv",
479 .id = 1,
480 .dev = {
481 .platform_data = &tw9910_link,
482 },
483 },
484 };
485
486 static struct platform_device *migor_devices[] __initdata = {
487 &smc91x_eth_device,
488 &sh_keysc_device,
489 &migor_lcdc_device,
490 &migor_ceu_device,
491 &migor_nor_flash_device,
492 &migor_nand_flash_device,
493 &sdhi_cn9_device,
494 &migor_camera[0],
495 &migor_camera[1],
496 };
497
498 extern char migor_sdram_enter_start;
499 extern char migor_sdram_enter_end;
500 extern char migor_sdram_leave_start;
501 extern char migor_sdram_leave_end;
502
migor_devices_setup(void)503 static int __init migor_devices_setup(void)
504 {
505 /* register board specific self-refresh code */
506 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
507 &migor_sdram_enter_start,
508 &migor_sdram_enter_end,
509 &migor_sdram_leave_start,
510 &migor_sdram_leave_end);
511
512 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
513 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
514
515 /* Let D11 LED show STATUS0 */
516 gpio_request(GPIO_FN_STATUS0, NULL);
517
518 /* Lit D12 LED show PDSTATUS */
519 gpio_request(GPIO_FN_PDSTATUS, NULL);
520
521 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
522 gpio_request(GPIO_FN_IRQ0, NULL);
523 __raw_writel(0x00003400, BSC_CS4BCR);
524 __raw_writel(0x00110080, BSC_CS4WCR);
525
526 /* KEYSC */
527 gpio_request(GPIO_FN_KEYOUT0, NULL);
528 gpio_request(GPIO_FN_KEYOUT1, NULL);
529 gpio_request(GPIO_FN_KEYOUT2, NULL);
530 gpio_request(GPIO_FN_KEYOUT3, NULL);
531 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
532 gpio_request(GPIO_FN_KEYIN1, NULL);
533 gpio_request(GPIO_FN_KEYIN2, NULL);
534 gpio_request(GPIO_FN_KEYIN3, NULL);
535 gpio_request(GPIO_FN_KEYIN4, NULL);
536 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
537
538 /* NAND Flash */
539 gpio_request(GPIO_FN_CS6A_CE2B, NULL);
540 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
541 gpio_request(GPIO_PTA1, NULL);
542 gpio_direction_input(GPIO_PTA1);
543
544 /* SDHI */
545 gpio_request(GPIO_FN_SDHICD, NULL);
546 gpio_request(GPIO_FN_SDHIWP, NULL);
547 gpio_request(GPIO_FN_SDHID3, NULL);
548 gpio_request(GPIO_FN_SDHID2, NULL);
549 gpio_request(GPIO_FN_SDHID1, NULL);
550 gpio_request(GPIO_FN_SDHID0, NULL);
551 gpio_request(GPIO_FN_SDHICMD, NULL);
552 gpio_request(GPIO_FN_SDHICLK, NULL);
553
554 /* Touch Panel */
555 gpio_request(GPIO_FN_IRQ6, NULL);
556
557 /* LCD Panel */
558 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
559 gpio_request(GPIO_FN_LCDD17, NULL);
560 gpio_request(GPIO_FN_LCDD16, NULL);
561 gpio_request(GPIO_FN_LCDD15, NULL);
562 gpio_request(GPIO_FN_LCDD14, NULL);
563 gpio_request(GPIO_FN_LCDD13, NULL);
564 gpio_request(GPIO_FN_LCDD12, NULL);
565 gpio_request(GPIO_FN_LCDD11, NULL);
566 gpio_request(GPIO_FN_LCDD10, NULL);
567 gpio_request(GPIO_FN_LCDD8, NULL);
568 gpio_request(GPIO_FN_LCDD7, NULL);
569 gpio_request(GPIO_FN_LCDD6, NULL);
570 gpio_request(GPIO_FN_LCDD5, NULL);
571 gpio_request(GPIO_FN_LCDD4, NULL);
572 gpio_request(GPIO_FN_LCDD3, NULL);
573 gpio_request(GPIO_FN_LCDD2, NULL);
574 gpio_request(GPIO_FN_LCDD1, NULL);
575 gpio_request(GPIO_FN_LCDRS, NULL);
576 gpio_request(GPIO_FN_LCDCS, NULL);
577 gpio_request(GPIO_FN_LCDRD, NULL);
578 gpio_request(GPIO_FN_LCDWR, NULL);
579 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
580 gpio_direction_output(GPIO_PTH2, 1);
581 #endif
582 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
583 gpio_request(GPIO_FN_LCDD15, NULL);
584 gpio_request(GPIO_FN_LCDD14, NULL);
585 gpio_request(GPIO_FN_LCDD13, NULL);
586 gpio_request(GPIO_FN_LCDD12, NULL);
587 gpio_request(GPIO_FN_LCDD11, NULL);
588 gpio_request(GPIO_FN_LCDD10, NULL);
589 gpio_request(GPIO_FN_LCDD9, NULL);
590 gpio_request(GPIO_FN_LCDD8, NULL);
591 gpio_request(GPIO_FN_LCDD7, NULL);
592 gpio_request(GPIO_FN_LCDD6, NULL);
593 gpio_request(GPIO_FN_LCDD5, NULL);
594 gpio_request(GPIO_FN_LCDD4, NULL);
595 gpio_request(GPIO_FN_LCDD3, NULL);
596 gpio_request(GPIO_FN_LCDD2, NULL);
597 gpio_request(GPIO_FN_LCDD1, NULL);
598 gpio_request(GPIO_FN_LCDD0, NULL);
599 gpio_request(GPIO_FN_LCDLCLK, NULL);
600 gpio_request(GPIO_FN_LCDDCK, NULL);
601 gpio_request(GPIO_FN_LCDVEPWC, NULL);
602 gpio_request(GPIO_FN_LCDVCPWC, NULL);
603 gpio_request(GPIO_FN_LCDVSYN, NULL);
604 gpio_request(GPIO_FN_LCDHSYN, NULL);
605 gpio_request(GPIO_FN_LCDDISP, NULL);
606 gpio_request(GPIO_FN_LCDDON, NULL);
607 #endif
608
609 /* CEU */
610 gpio_request(GPIO_FN_VIO_CLK2, NULL);
611 gpio_request(GPIO_FN_VIO_VD2, NULL);
612 gpio_request(GPIO_FN_VIO_HD2, NULL);
613 gpio_request(GPIO_FN_VIO_FLD, NULL);
614 gpio_request(GPIO_FN_VIO_CKO, NULL);
615 gpio_request(GPIO_FN_VIO_D15, NULL);
616 gpio_request(GPIO_FN_VIO_D14, NULL);
617 gpio_request(GPIO_FN_VIO_D13, NULL);
618 gpio_request(GPIO_FN_VIO_D12, NULL);
619 gpio_request(GPIO_FN_VIO_D11, NULL);
620 gpio_request(GPIO_FN_VIO_D10, NULL);
621 gpio_request(GPIO_FN_VIO_D9, NULL);
622 gpio_request(GPIO_FN_VIO_D8, NULL);
623
624 gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
625 gpio_direction_output(GPIO_PTT3, 0);
626 gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
627 gpio_direction_output(GPIO_PTT2, 1);
628 gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
629 #ifdef CONFIG_SH_MIGOR_RTA_WVGA
630 gpio_direction_output(GPIO_PTT0, 0);
631 #else
632 gpio_direction_output(GPIO_PTT0, 1);
633 #endif
634 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
635
636 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
637
638 /* SIU: Port B */
639 gpio_request(GPIO_FN_SIUBOLR, NULL);
640 gpio_request(GPIO_FN_SIUBOBT, NULL);
641 gpio_request(GPIO_FN_SIUBISLD, NULL);
642 gpio_request(GPIO_FN_SIUBOSLD, NULL);
643 gpio_request(GPIO_FN_SIUMCKB, NULL);
644
645 /*
646 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
647 * output. Need only SIUB, set to output for master mode (table 34.2)
648 */
649 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
650
651 i2c_register_board_info(0, migor_i2c_devices,
652 ARRAY_SIZE(migor_i2c_devices));
653
654 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
655 }
656 arch_initcall(migor_devices_setup);
657
658 /* Return the board specific boot mode pin configuration */
migor_mode_pins(void)659 static int migor_mode_pins(void)
660 {
661 /* MD0=1, MD1=1, MD2=0: Clock Mode 3
662 * MD3=0: 16-bit Area0 Bus Width
663 * MD5=1: Little Endian
664 * TSTMD=1, MD8=0: Test Mode Disabled
665 */
666 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
667 }
668
669 /*
670 * The Machine Vector
671 */
672 static struct sh_machine_vector mv_migor __initmv = {
673 .mv_name = "Migo-R",
674 .mv_mode_pins = migor_mode_pins,
675 };
676