1 /*
2 * Copyright (C) 1994 Linus Torvalds
3 *
4 * Cyrix stuff, June 1998 by:
5 * - Rafael R. Reilova (moved everything from head.S),
6 * <rreilova@ececs.uc.edu>
7 * - Channing Corn (tests & fixes),
8 * - Andrew D. Balsa (code cleanup).
9 */
10 #include <linux/init.h>
11 #include <linux/utsname.h>
12 #include <linux/cpu.h>
13 #include <linux/module.h>
14 #include <linux/nospec.h>
15 #include <linux/prctl.h>
16 #include <linux/sched/smt.h>
17
18 #include <asm/spec-ctrl.h>
19 #include <asm/cmdline.h>
20 #include <asm/bugs.h>
21 #include <asm/processor.h>
22 #include <asm/processor-flags.h>
23 #include <asm/fpu/internal.h>
24 #include <asm/msr.h>
25 #include <asm/paravirt.h>
26 #include <asm/alternative.h>
27 #include <asm/hypervisor.h>
28 #include <asm/pgtable.h>
29 #include <asm/cacheflush.h>
30 #include <asm/intel-family.h>
31 #include <asm/e820.h>
32
33 #include "cpu.h"
34
35 static void __init spectre_v1_select_mitigation(void);
36 static void __init spectre_v2_select_mitigation(void);
37 static void __init ssb_select_mitigation(void);
38 static void __init l1tf_select_mitigation(void);
39 static void __init mds_select_mitigation(void);
40 static void __init mds_print_mitigation(void);
41 static void __init taa_select_mitigation(void);
42 static void __init srbds_select_mitigation(void);
43
44 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
45 u64 x86_spec_ctrl_base;
46 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
47 static DEFINE_MUTEX(spec_ctrl_mutex);
48
49 /*
50 * The vendor and possibly platform specific bits which can be modified in
51 * x86_spec_ctrl_base.
52 */
53 static u64 x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
54
55 /*
56 * AMD specific MSR info for Speculative Store Bypass control.
57 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
58 */
59 u64 x86_amd_ls_cfg_base;
60 u64 x86_amd_ls_cfg_ssbd_mask;
61
62 /* Control conditional STIBP in switch_to() */
63 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
64 /* Control conditional IBPB in switch_mm() */
65 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
66 /* Control unconditional IBPB in switch_mm() */
67 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
68
69 /* Control MDS CPU buffer clear before returning to user space */
70 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
71 /* Control MDS CPU buffer clear before idling (halt, mwait) */
72 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
73 EXPORT_SYMBOL_GPL(mds_idle_clear);
74
check_bugs(void)75 void __init check_bugs(void)
76 {
77 identify_boot_cpu();
78
79 if (!IS_ENABLED(CONFIG_SMP)) {
80 pr_info("CPU: ");
81 print_cpu_info(&boot_cpu_data);
82 }
83
84 /*
85 * Read the SPEC_CTRL MSR to account for reserved bits which may
86 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
87 * init code as it is not enumerated and depends on the family.
88 */
89 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
90 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
91
92 /* Allow STIBP in MSR_SPEC_CTRL if supported */
93 if (boot_cpu_has(X86_FEATURE_STIBP))
94 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
95
96 /* Select the proper CPU mitigations before patching alternatives: */
97 spectre_v1_select_mitigation();
98 spectre_v2_select_mitigation();
99 ssb_select_mitigation();
100 l1tf_select_mitigation();
101 mds_select_mitigation();
102 taa_select_mitigation();
103 srbds_select_mitigation();
104
105 /*
106 * As MDS and TAA mitigations are inter-related, print MDS
107 * mitigation until after TAA mitigation selection is done.
108 */
109 mds_print_mitigation();
110
111 arch_smt_update();
112
113 #ifdef CONFIG_X86_32
114 /*
115 * Check whether we are able to run this kernel safely on SMP.
116 *
117 * - i386 is no longer supported.
118 * - In order to run on anything without a TSC, we need to be
119 * compiled for a i486.
120 */
121 if (boot_cpu_data.x86 < 4)
122 panic("Kernel requires i486+ for 'invlpg' and other features");
123
124 init_utsname()->machine[1] =
125 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
126 alternative_instructions();
127
128 fpu__init_check_bugs();
129 #else /* CONFIG_X86_64 */
130 alternative_instructions();
131
132 /*
133 * Make sure the first 2MB area is not mapped by huge pages
134 * There are typically fixed size MTRRs in there and overlapping
135 * MTRRs into large pages causes slow downs.
136 *
137 * Right now we don't do that with gbpages because there seems
138 * very little benefit for that case.
139 */
140 if (!direct_gbpages)
141 set_memory_4k((unsigned long)__va(0), 1);
142 #endif
143 }
144
145 void
x86_virt_spec_ctrl(u64 guest_spec_ctrl,u64 guest_virt_spec_ctrl,bool setguest)146 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
147 {
148 u64 msrval, guestval, hostval = x86_spec_ctrl_base;
149 struct thread_info *ti = current_thread_info();
150
151 /* Is MSR_SPEC_CTRL implemented ? */
152 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
153 /*
154 * Restrict guest_spec_ctrl to supported values. Clear the
155 * modifiable bits in the host base value and or the
156 * modifiable bits from the guest value.
157 */
158 guestval = hostval & ~x86_spec_ctrl_mask;
159 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
160
161 /* SSBD controlled in MSR_SPEC_CTRL */
162 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
163 static_cpu_has(X86_FEATURE_AMD_SSBD))
164 hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
165
166 /* Conditional STIBP enabled? */
167 if (static_branch_unlikely(&switch_to_cond_stibp))
168 hostval |= stibp_tif_to_spec_ctrl(ti->flags);
169
170 if (hostval != guestval) {
171 msrval = setguest ? guestval : hostval;
172 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
173 }
174 }
175
176 /*
177 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
178 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
179 */
180 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
181 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
182 return;
183
184 /*
185 * If the host has SSBD mitigation enabled, force it in the host's
186 * virtual MSR value. If its not permanently enabled, evaluate
187 * current's TIF_SSBD thread flag.
188 */
189 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
190 hostval = SPEC_CTRL_SSBD;
191 else
192 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
193
194 /* Sanitize the guest value */
195 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
196
197 if (hostval != guestval) {
198 unsigned long tif;
199
200 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
201 ssbd_spec_ctrl_to_tif(hostval);
202
203 speculation_ctrl_update(tif);
204 }
205 }
206 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
207
x86_amd_ssb_disable(void)208 static void x86_amd_ssb_disable(void)
209 {
210 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
211
212 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
213 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
214 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
215 wrmsrl(MSR_AMD64_LS_CFG, msrval);
216 }
217
218 #undef pr_fmt
219 #define pr_fmt(fmt) "MDS: " fmt
220
221 /* Default mitigation for MDS-affected CPUs */
222 static enum mds_mitigations mds_mitigation = MDS_MITIGATION_FULL;
223
224 static const char * const mds_strings[] = {
225 [MDS_MITIGATION_OFF] = "Vulnerable",
226 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
227 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
228 };
229
mds_select_mitigation(void)230 static void __init mds_select_mitigation(void)
231 {
232 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
233 mds_mitigation = MDS_MITIGATION_OFF;
234 return;
235 }
236 }
237
mds_print_mitigation(void)238 static void __init mds_print_mitigation(void)
239 {
240 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off())
241 return;
242
243 if (mds_mitigation == MDS_MITIGATION_FULL) {
244 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
245 mds_mitigation = MDS_MITIGATION_VMWERV;
246 static_branch_enable(&mds_user_clear);
247 }
248 pr_info("%s\n", mds_strings[mds_mitigation]);
249 }
250
mds_cmdline(char * str)251 static int __init mds_cmdline(char *str)
252 {
253 if (!boot_cpu_has_bug(X86_BUG_MDS))
254 return 0;
255
256 if (!str)
257 return -EINVAL;
258
259 if (!strcmp(str, "off"))
260 mds_mitigation = MDS_MITIGATION_OFF;
261 else if (!strcmp(str, "full"))
262 mds_mitigation = MDS_MITIGATION_FULL;
263
264 return 0;
265 }
266 early_param("mds", mds_cmdline);
267
mds_user_clear_buffers(void)268 void mds_user_clear_buffers(void)
269 {
270 mds_user_clear_cpu_buffers();
271 }
272
273 #undef pr_fmt
274 #define pr_fmt(fmt) "TAA: " fmt
275
276 /* Default mitigation for TAA-affected CPUs */
277 static enum taa_mitigations taa_mitigation = TAA_MITIGATION_VERW;
278
279 static const char * const taa_strings[] = {
280 [TAA_MITIGATION_OFF] = "Vulnerable",
281 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
282 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
283 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
284 };
285
taa_select_mitigation(void)286 static void __init taa_select_mitigation(void)
287 {
288 u64 ia32_cap;
289
290 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
291 taa_mitigation = TAA_MITIGATION_OFF;
292 return;
293 }
294
295 /* TSX previously disabled by tsx=off */
296 if (!boot_cpu_has(X86_FEATURE_RTM)) {
297 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
298 goto out;
299 }
300
301 if (cpu_mitigations_off()) {
302 taa_mitigation = TAA_MITIGATION_OFF;
303 return;
304 }
305
306 /*
307 * TAA mitigation via VERW is turned off if both
308 * tsx_async_abort=off and mds=off are specified.
309 */
310 if (taa_mitigation == TAA_MITIGATION_OFF &&
311 mds_mitigation == MDS_MITIGATION_OFF)
312 goto out;
313
314 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
315 taa_mitigation = TAA_MITIGATION_VERW;
316 else
317 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
318
319 /*
320 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
321 * A microcode update fixes this behavior to clear CPU buffers. It also
322 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
323 * ARCH_CAP_TSX_CTRL_MSR bit.
324 *
325 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
326 * update is required.
327 */
328 ia32_cap = x86_read_arch_cap_msr();
329 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
330 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
331 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
332
333 /*
334 * TSX is enabled, select alternate mitigation for TAA which is
335 * the same as MDS. Enable MDS static branch to clear CPU buffers.
336 *
337 * For guests that can't determine whether the correct microcode is
338 * present on host, enable the mitigation for UCODE_NEEDED as well.
339 */
340 static_branch_enable(&mds_user_clear);
341
342 /*
343 * Update MDS mitigation, if necessary, as the mds_user_clear is
344 * now enabled for TAA mitigation.
345 */
346 if (mds_mitigation == MDS_MITIGATION_OFF &&
347 boot_cpu_has_bug(X86_BUG_MDS)) {
348 mds_mitigation = MDS_MITIGATION_FULL;
349 mds_select_mitigation();
350 }
351 out:
352 pr_info("%s\n", taa_strings[taa_mitigation]);
353 }
354
tsx_async_abort_parse_cmdline(char * str)355 static int __init tsx_async_abort_parse_cmdline(char *str)
356 {
357 if (!boot_cpu_has_bug(X86_BUG_TAA))
358 return 0;
359
360 if (!str)
361 return -EINVAL;
362
363 if (!strcmp(str, "off")) {
364 taa_mitigation = TAA_MITIGATION_OFF;
365 } else if (!strcmp(str, "full")) {
366 taa_mitigation = TAA_MITIGATION_VERW;
367 }
368
369 return 0;
370 }
371 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
372
373 #undef pr_fmt
374 #define pr_fmt(fmt) "SRBDS: " fmt
375
376 enum srbds_mitigations {
377 SRBDS_MITIGATION_OFF,
378 SRBDS_MITIGATION_UCODE_NEEDED,
379 SRBDS_MITIGATION_FULL,
380 SRBDS_MITIGATION_TSX_OFF,
381 SRBDS_MITIGATION_HYPERVISOR,
382 };
383
384 static enum srbds_mitigations srbds_mitigation = SRBDS_MITIGATION_FULL;
385
386 static const char * const srbds_strings[] = {
387 [SRBDS_MITIGATION_OFF] = "Vulnerable",
388 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
389 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
390 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
391 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
392 };
393
394 static bool srbds_off;
395
update_srbds_msr(void)396 void update_srbds_msr(void)
397 {
398 u64 mcu_ctrl;
399
400 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
401 return;
402
403 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
404 return;
405
406 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
407 return;
408
409 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
410
411 switch (srbds_mitigation) {
412 case SRBDS_MITIGATION_OFF:
413 case SRBDS_MITIGATION_TSX_OFF:
414 mcu_ctrl |= RNGDS_MITG_DIS;
415 break;
416 case SRBDS_MITIGATION_FULL:
417 mcu_ctrl &= ~RNGDS_MITG_DIS;
418 break;
419 default:
420 break;
421 }
422
423 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
424 }
425
srbds_select_mitigation(void)426 static void __init srbds_select_mitigation(void)
427 {
428 u64 ia32_cap;
429
430 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
431 return;
432
433 /*
434 * Check to see if this is one of the MDS_NO systems supporting
435 * TSX that are only exposed to SRBDS when TSX is enabled.
436 */
437 ia32_cap = x86_read_arch_cap_msr();
438 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
439 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
440 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
441 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
442 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
443 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
444 else if (cpu_mitigations_off() || srbds_off)
445 srbds_mitigation = SRBDS_MITIGATION_OFF;
446
447 update_srbds_msr();
448 pr_info("%s\n", srbds_strings[srbds_mitigation]);
449 }
450
srbds_parse_cmdline(char * str)451 static int __init srbds_parse_cmdline(char *str)
452 {
453 if (!str)
454 return -EINVAL;
455
456 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
457 return 0;
458
459 srbds_off = !strcmp(str, "off");
460 return 0;
461 }
462 early_param("srbds", srbds_parse_cmdline);
463
464 #undef pr_fmt
465 #define pr_fmt(fmt) "Spectre V1 : " fmt
466
467 enum spectre_v1_mitigation {
468 SPECTRE_V1_MITIGATION_NONE,
469 SPECTRE_V1_MITIGATION_AUTO,
470 };
471
472 static enum spectre_v1_mitigation spectre_v1_mitigation =
473 SPECTRE_V1_MITIGATION_AUTO;
474
475 static const char * const spectre_v1_strings[] = {
476 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
477 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
478 };
479
480 /*
481 * Does SMAP provide full mitigation against speculative kernel access to
482 * userspace?
483 */
smap_works_speculatively(void)484 static bool smap_works_speculatively(void)
485 {
486 if (!boot_cpu_has(X86_FEATURE_SMAP))
487 return false;
488
489 /*
490 * On CPUs which are vulnerable to Meltdown, SMAP does not
491 * prevent speculative access to user data in the L1 cache.
492 * Consider SMAP to be non-functional as a mitigation on these
493 * CPUs.
494 */
495 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
496 return false;
497
498 return true;
499 }
500
spectre_v1_select_mitigation(void)501 static void __init spectre_v1_select_mitigation(void)
502 {
503 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
504 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
505 return;
506 }
507
508 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
509 /*
510 * With Spectre v1, a user can speculatively control either
511 * path of a conditional swapgs with a user-controlled GS
512 * value. The mitigation is to add lfences to both code paths.
513 *
514 * If FSGSBASE is enabled, the user can put a kernel address in
515 * GS, in which case SMAP provides no protection.
516 *
517 * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
518 * FSGSBASE enablement patches have been merged. ]
519 *
520 * If FSGSBASE is disabled, the user can only put a user space
521 * address in GS. That makes an attack harder, but still
522 * possible if there's no SMAP protection.
523 */
524 if (!smap_works_speculatively()) {
525 /*
526 * Mitigation can be provided from SWAPGS itself or
527 * PTI as the CR3 write in the Meltdown mitigation
528 * is serializing.
529 *
530 * If neither is there, mitigate with an LFENCE to
531 * stop speculation through swapgs.
532 */
533 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
534 !boot_cpu_has(X86_FEATURE_KAISER))
535 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
536
537 /*
538 * Enable lfences in the kernel entry (non-swapgs)
539 * paths, to prevent user entry from speculatively
540 * skipping swapgs.
541 */
542 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
543 }
544 }
545
546 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
547 }
548
nospectre_v1_cmdline(char * str)549 static int __init nospectre_v1_cmdline(char *str)
550 {
551 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
552 return 0;
553 }
554 early_param("nospectre_v1", nospectre_v1_cmdline);
555
556 #undef pr_fmt
557 #define pr_fmt(fmt) "Spectre V2 : " fmt
558
559 static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE;
560
561 static enum spectre_v2_user_mitigation spectre_v2_user_stibp = SPECTRE_V2_USER_NONE;
562 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb = SPECTRE_V2_USER_NONE;
563
564 #ifdef RETPOLINE
565 static bool spectre_v2_bad_module;
566
retpoline_module_ok(bool has_retpoline)567 bool retpoline_module_ok(bool has_retpoline)
568 {
569 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
570 return true;
571
572 pr_err("System may be vulnerable to spectre v2\n");
573 spectre_v2_bad_module = true;
574 return false;
575 }
576
spectre_v2_module_string(void)577 static inline const char *spectre_v2_module_string(void)
578 {
579 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
580 }
581 #else
spectre_v2_module_string(void)582 static inline const char *spectre_v2_module_string(void) { return ""; }
583 #endif
584
match_option(const char * arg,int arglen,const char * opt)585 static inline bool match_option(const char *arg, int arglen, const char *opt)
586 {
587 int len = strlen(opt);
588
589 return len == arglen && !strncmp(arg, opt, len);
590 }
591
592 /* The kernel command line selection for spectre v2 */
593 enum spectre_v2_mitigation_cmd {
594 SPECTRE_V2_CMD_NONE,
595 SPECTRE_V2_CMD_AUTO,
596 SPECTRE_V2_CMD_FORCE,
597 SPECTRE_V2_CMD_RETPOLINE,
598 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
599 SPECTRE_V2_CMD_RETPOLINE_AMD,
600 };
601
602 enum spectre_v2_user_cmd {
603 SPECTRE_V2_USER_CMD_NONE,
604 SPECTRE_V2_USER_CMD_AUTO,
605 SPECTRE_V2_USER_CMD_FORCE,
606 SPECTRE_V2_USER_CMD_PRCTL,
607 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
608 SPECTRE_V2_USER_CMD_SECCOMP,
609 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
610 };
611
612 static const char * const spectre_v2_user_strings[] = {
613 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
614 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
615 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
616 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
617 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
618 };
619
620 static const struct {
621 const char *option;
622 enum spectre_v2_user_cmd cmd;
623 bool secure;
624 } v2_user_options[] __initconst = {
625 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
626 { "off", SPECTRE_V2_USER_CMD_NONE, false },
627 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
628 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
629 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
630 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
631 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
632 };
633
spec_v2_user_print_cond(const char * reason,bool secure)634 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
635 {
636 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
637 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
638 }
639
640 static enum spectre_v2_user_cmd __init
spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)641 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)
642 {
643 char arg[20];
644 int ret, i;
645
646 switch (v2_cmd) {
647 case SPECTRE_V2_CMD_NONE:
648 return SPECTRE_V2_USER_CMD_NONE;
649 case SPECTRE_V2_CMD_FORCE:
650 return SPECTRE_V2_USER_CMD_FORCE;
651 default:
652 break;
653 }
654
655 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
656 arg, sizeof(arg));
657 if (ret < 0)
658 return SPECTRE_V2_USER_CMD_AUTO;
659
660 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
661 if (match_option(arg, ret, v2_user_options[i].option)) {
662 spec_v2_user_print_cond(v2_user_options[i].option,
663 v2_user_options[i].secure);
664 return v2_user_options[i].cmd;
665 }
666 }
667
668 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
669 return SPECTRE_V2_USER_CMD_AUTO;
670 }
671
672 static void __init
spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)673 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
674 {
675 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
676 bool smt_possible = IS_ENABLED(CONFIG_SMP);
677 enum spectre_v2_user_cmd cmd;
678
679 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
680 return;
681
682 if (!IS_ENABLED(CONFIG_SMP))
683 smt_possible = false;
684
685 cmd = spectre_v2_parse_user_cmdline(v2_cmd);
686 switch (cmd) {
687 case SPECTRE_V2_USER_CMD_NONE:
688 goto set_mode;
689 case SPECTRE_V2_USER_CMD_FORCE:
690 mode = SPECTRE_V2_USER_STRICT;
691 break;
692 case SPECTRE_V2_USER_CMD_PRCTL:
693 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
694 mode = SPECTRE_V2_USER_PRCTL;
695 break;
696 case SPECTRE_V2_USER_CMD_AUTO:
697 case SPECTRE_V2_USER_CMD_SECCOMP:
698 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
699 if (IS_ENABLED(CONFIG_SECCOMP))
700 mode = SPECTRE_V2_USER_SECCOMP;
701 else
702 mode = SPECTRE_V2_USER_PRCTL;
703 break;
704 }
705
706 /* Initialize Indirect Branch Prediction Barrier */
707 if (boot_cpu_has(X86_FEATURE_IBPB)) {
708 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
709
710 spectre_v2_user_ibpb = mode;
711 switch (cmd) {
712 case SPECTRE_V2_USER_CMD_FORCE:
713 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
714 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
715 static_branch_enable(&switch_mm_always_ibpb);
716 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
717 break;
718 case SPECTRE_V2_USER_CMD_PRCTL:
719 case SPECTRE_V2_USER_CMD_AUTO:
720 case SPECTRE_V2_USER_CMD_SECCOMP:
721 static_branch_enable(&switch_mm_cond_ibpb);
722 break;
723 default:
724 break;
725 }
726
727 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
728 static_key_enabled(&switch_mm_always_ibpb) ?
729 "always-on" : "conditional");
730 }
731
732 /*
733 * If enhanced IBRS is enabled or SMT impossible, STIBP is not
734 * required.
735 */
736 if (!smt_possible || spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
737 return;
738
739 /*
740 * At this point, an STIBP mode other than "off" has been set.
741 * If STIBP support is not being forced, check if STIBP always-on
742 * is preferred.
743 */
744 if (mode != SPECTRE_V2_USER_STRICT &&
745 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
746 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
747
748 /*
749 * If STIBP is not available, clear the STIBP mode.
750 */
751 if (!boot_cpu_has(X86_FEATURE_STIBP))
752 mode = SPECTRE_V2_USER_NONE;
753
754 spectre_v2_user_stibp = mode;
755
756 set_mode:
757 pr_info("%s\n", spectre_v2_user_strings[mode]);
758 }
759
760 static const char * const spectre_v2_strings[] = {
761 [SPECTRE_V2_NONE] = "Vulnerable",
762 [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline",
763 [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline",
764 [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline",
765 [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline",
766 [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS",
767 };
768
769 static const struct {
770 const char *option;
771 enum spectre_v2_mitigation_cmd cmd;
772 bool secure;
773 } mitigation_options[] __initconst = {
774 { "off", SPECTRE_V2_CMD_NONE, false },
775 { "on", SPECTRE_V2_CMD_FORCE, true },
776 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
777 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false },
778 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
779 { "auto", SPECTRE_V2_CMD_AUTO, false },
780 };
781
spec_v2_print_cond(const char * reason,bool secure)782 static void __init spec_v2_print_cond(const char *reason, bool secure)
783 {
784 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
785 pr_info("%s selected on command line.\n", reason);
786 }
787
retp_compiler(void)788 static inline bool retp_compiler(void)
789 {
790 return __is_defined(RETPOLINE);
791 }
792
spectre_v2_parse_cmdline(void)793 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
794 {
795 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
796 char arg[20];
797 int ret, i;
798
799 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
800 cpu_mitigations_off())
801 return SPECTRE_V2_CMD_NONE;
802
803 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
804 if (ret < 0)
805 return SPECTRE_V2_CMD_AUTO;
806
807 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
808 if (!match_option(arg, ret, mitigation_options[i].option))
809 continue;
810 cmd = mitigation_options[i].cmd;
811 break;
812 }
813
814 if (i >= ARRAY_SIZE(mitigation_options)) {
815 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
816 return SPECTRE_V2_CMD_AUTO;
817 }
818
819 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
820 cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
821 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
822 !IS_ENABLED(CONFIG_RETPOLINE)) {
823 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
824 return SPECTRE_V2_CMD_AUTO;
825 }
826
827 if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
828 boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
829 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
830 return SPECTRE_V2_CMD_AUTO;
831 }
832
833 spec_v2_print_cond(mitigation_options[i].option,
834 mitigation_options[i].secure);
835 return cmd;
836 }
837
spectre_v2_select_mitigation(void)838 static void __init spectre_v2_select_mitigation(void)
839 {
840 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
841 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
842
843 /*
844 * If the CPU is not affected and the command line mode is NONE or AUTO
845 * then nothing to do.
846 */
847 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
848 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
849 return;
850
851 switch (cmd) {
852 case SPECTRE_V2_CMD_NONE:
853 return;
854
855 case SPECTRE_V2_CMD_FORCE:
856 case SPECTRE_V2_CMD_AUTO:
857 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
858 mode = SPECTRE_V2_IBRS_ENHANCED;
859 /* Force it so VMEXIT will restore correctly */
860 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
861 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
862 goto specv2_set_mode;
863 }
864 if (IS_ENABLED(CONFIG_RETPOLINE))
865 goto retpoline_auto;
866 break;
867 case SPECTRE_V2_CMD_RETPOLINE_AMD:
868 if (IS_ENABLED(CONFIG_RETPOLINE))
869 goto retpoline_amd;
870 break;
871 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
872 if (IS_ENABLED(CONFIG_RETPOLINE))
873 goto retpoline_generic;
874 break;
875 case SPECTRE_V2_CMD_RETPOLINE:
876 if (IS_ENABLED(CONFIG_RETPOLINE))
877 goto retpoline_auto;
878 break;
879 }
880 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
881 return;
882
883 retpoline_auto:
884 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
885 retpoline_amd:
886 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
887 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
888 goto retpoline_generic;
889 }
890 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
891 SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
892 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
893 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
894 } else {
895 retpoline_generic:
896 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
897 SPECTRE_V2_RETPOLINE_MINIMAL;
898 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
899 }
900
901 specv2_set_mode:
902 spectre_v2_enabled = mode;
903 pr_info("%s\n", spectre_v2_strings[mode]);
904
905 /*
906 * If spectre v2 protection has been enabled, unconditionally fill
907 * RSB during a context switch; this protects against two independent
908 * issues:
909 *
910 * - RSB underflow (and switch to BTB) on Skylake+
911 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
912 */
913 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
914 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
915
916 /*
917 * Retpoline means the kernel is safe because it has no indirect
918 * branches. Enhanced IBRS protects firmware too, so, enable restricted
919 * speculation around firmware calls only when Enhanced IBRS isn't
920 * supported.
921 *
922 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
923 * the user might select retpoline on the kernel command line and if
924 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
925 * enable IBRS around firmware calls.
926 */
927 if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
928 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
929 pr_info("Enabling Restricted Speculation for firmware calls\n");
930 }
931
932 /* Set up IBPB and STIBP depending on the general spectre V2 command */
933 spectre_v2_user_select_mitigation(cmd);
934 }
935
update_stibp_msr(void * __unused)936 static void update_stibp_msr(void * __unused)
937 {
938 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
939 }
940
941 /* Update x86_spec_ctrl_base in case SMT state changed. */
update_stibp_strict(void)942 static void update_stibp_strict(void)
943 {
944 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
945
946 if (sched_smt_active())
947 mask |= SPEC_CTRL_STIBP;
948
949 if (mask == x86_spec_ctrl_base)
950 return;
951
952 pr_info("Update user space SMT mitigation: STIBP %s\n",
953 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
954 x86_spec_ctrl_base = mask;
955 on_each_cpu(update_stibp_msr, NULL, 1);
956 }
957
958 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
update_indir_branch_cond(void)959 static void update_indir_branch_cond(void)
960 {
961 if (sched_smt_active())
962 static_branch_enable(&switch_to_cond_stibp);
963 else
964 static_branch_disable(&switch_to_cond_stibp);
965 }
966
967 #undef pr_fmt
968 #define pr_fmt(fmt) fmt
969
970 /* Update the static key controlling the MDS CPU buffer clear in idle */
update_mds_branch_idle(void)971 static void update_mds_branch_idle(void)
972 {
973 /*
974 * Enable the idle clearing if SMT is active on CPUs which are
975 * affected only by MSBDS and not any other MDS variant.
976 *
977 * The other variants cannot be mitigated when SMT is enabled, so
978 * clearing the buffers on idle just to prevent the Store Buffer
979 * repartitioning leak would be a window dressing exercise.
980 */
981 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
982 return;
983
984 if (sched_smt_active())
985 static_branch_enable(&mds_idle_clear);
986 else
987 static_branch_disable(&mds_idle_clear);
988 }
989
990 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
991 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
992
arch_smt_update(void)993 void arch_smt_update(void)
994 {
995 mutex_lock(&spec_ctrl_mutex);
996
997 switch (spectre_v2_user_stibp) {
998 case SPECTRE_V2_USER_NONE:
999 break;
1000 case SPECTRE_V2_USER_STRICT:
1001 case SPECTRE_V2_USER_STRICT_PREFERRED:
1002 update_stibp_strict();
1003 break;
1004 case SPECTRE_V2_USER_PRCTL:
1005 case SPECTRE_V2_USER_SECCOMP:
1006 update_indir_branch_cond();
1007 break;
1008 }
1009
1010 switch (mds_mitigation) {
1011 case MDS_MITIGATION_FULL:
1012 case MDS_MITIGATION_VMWERV:
1013 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1014 pr_warn_once(MDS_MSG_SMT);
1015 update_mds_branch_idle();
1016 break;
1017 case MDS_MITIGATION_OFF:
1018 break;
1019 }
1020
1021 switch (taa_mitigation) {
1022 case TAA_MITIGATION_VERW:
1023 case TAA_MITIGATION_UCODE_NEEDED:
1024 if (sched_smt_active())
1025 pr_warn_once(TAA_MSG_SMT);
1026 break;
1027 case TAA_MITIGATION_TSX_DISABLED:
1028 case TAA_MITIGATION_OFF:
1029 break;
1030 }
1031
1032 mutex_unlock(&spec_ctrl_mutex);
1033 }
1034
1035 #undef pr_fmt
1036 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1037
1038 static enum ssb_mitigation ssb_mode = SPEC_STORE_BYPASS_NONE;
1039
1040 /* The kernel command line selection */
1041 enum ssb_mitigation_cmd {
1042 SPEC_STORE_BYPASS_CMD_NONE,
1043 SPEC_STORE_BYPASS_CMD_AUTO,
1044 SPEC_STORE_BYPASS_CMD_ON,
1045 SPEC_STORE_BYPASS_CMD_PRCTL,
1046 SPEC_STORE_BYPASS_CMD_SECCOMP,
1047 };
1048
1049 static const char * const ssb_strings[] = {
1050 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1051 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1052 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1053 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1054 };
1055
1056 static const struct {
1057 const char *option;
1058 enum ssb_mitigation_cmd cmd;
1059 } ssb_mitigation_options[] __initconst = {
1060 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1061 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1062 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1063 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1064 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1065 };
1066
ssb_parse_cmdline(void)1067 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1068 {
1069 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1070 char arg[20];
1071 int ret, i;
1072
1073 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1074 cpu_mitigations_off()) {
1075 return SPEC_STORE_BYPASS_CMD_NONE;
1076 } else {
1077 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1078 arg, sizeof(arg));
1079 if (ret < 0)
1080 return SPEC_STORE_BYPASS_CMD_AUTO;
1081
1082 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1083 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1084 continue;
1085
1086 cmd = ssb_mitigation_options[i].cmd;
1087 break;
1088 }
1089
1090 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1091 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1092 return SPEC_STORE_BYPASS_CMD_AUTO;
1093 }
1094 }
1095
1096 return cmd;
1097 }
1098
__ssb_select_mitigation(void)1099 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1100 {
1101 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1102 enum ssb_mitigation_cmd cmd;
1103
1104 if (!boot_cpu_has(X86_FEATURE_SSBD))
1105 return mode;
1106
1107 cmd = ssb_parse_cmdline();
1108 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1109 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1110 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1111 return mode;
1112
1113 switch (cmd) {
1114 case SPEC_STORE_BYPASS_CMD_AUTO:
1115 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1116 /*
1117 * Choose prctl+seccomp as the default mode if seccomp is
1118 * enabled.
1119 */
1120 if (IS_ENABLED(CONFIG_SECCOMP))
1121 mode = SPEC_STORE_BYPASS_SECCOMP;
1122 else
1123 mode = SPEC_STORE_BYPASS_PRCTL;
1124 break;
1125 case SPEC_STORE_BYPASS_CMD_ON:
1126 mode = SPEC_STORE_BYPASS_DISABLE;
1127 break;
1128 case SPEC_STORE_BYPASS_CMD_PRCTL:
1129 mode = SPEC_STORE_BYPASS_PRCTL;
1130 break;
1131 case SPEC_STORE_BYPASS_CMD_NONE:
1132 break;
1133 }
1134
1135 /*
1136 * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1137 * bit in the mask to allow guests to use the mitigation even in the
1138 * case where the host does not enable it.
1139 */
1140 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
1141 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1142 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
1143 }
1144
1145 /*
1146 * We have three CPU feature flags that are in play here:
1147 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1148 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1149 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1150 */
1151 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1152 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1153 /*
1154 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1155 * use a completely different MSR and bit dependent on family.
1156 */
1157 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1158 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1159 x86_amd_ssb_disable();
1160 } else {
1161 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1162 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1163 }
1164 }
1165
1166 return mode;
1167 }
1168
ssb_select_mitigation(void)1169 static void ssb_select_mitigation(void)
1170 {
1171 ssb_mode = __ssb_select_mitigation();
1172
1173 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1174 pr_info("%s\n", ssb_strings[ssb_mode]);
1175 }
1176
1177 #undef pr_fmt
1178 #define pr_fmt(fmt) "Speculation prctl: " fmt
1179
task_update_spec_tif(struct task_struct * tsk)1180 static void task_update_spec_tif(struct task_struct *tsk)
1181 {
1182 /* Force the update of the real TIF bits */
1183 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1184
1185 /*
1186 * Immediately update the speculation control MSRs for the current
1187 * task, but for a non-current task delay setting the CPU
1188 * mitigation until it is scheduled next.
1189 *
1190 * This can only happen for SECCOMP mitigation. For PRCTL it's
1191 * always the current task.
1192 */
1193 if (tsk == current)
1194 speculation_ctrl_update_current();
1195 }
1196
ssb_prctl_set(struct task_struct * task,unsigned long ctrl)1197 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1198 {
1199 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1200 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1201 return -ENXIO;
1202
1203 switch (ctrl) {
1204 case PR_SPEC_ENABLE:
1205 /* If speculation is force disabled, enable is not allowed */
1206 if (task_spec_ssb_force_disable(task))
1207 return -EPERM;
1208 task_clear_spec_ssb_disable(task);
1209 task_update_spec_tif(task);
1210 break;
1211 case PR_SPEC_DISABLE:
1212 task_set_spec_ssb_disable(task);
1213 task_update_spec_tif(task);
1214 break;
1215 case PR_SPEC_FORCE_DISABLE:
1216 task_set_spec_ssb_disable(task);
1217 task_set_spec_ssb_force_disable(task);
1218 task_update_spec_tif(task);
1219 break;
1220 default:
1221 return -ERANGE;
1222 }
1223 return 0;
1224 }
1225
is_spec_ib_user_controlled(void)1226 static bool is_spec_ib_user_controlled(void)
1227 {
1228 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1229 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1230 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1231 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1232 }
1233
ib_prctl_set(struct task_struct * task,unsigned long ctrl)1234 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1235 {
1236 switch (ctrl) {
1237 case PR_SPEC_ENABLE:
1238 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1239 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1240 return 0;
1241
1242 /*
1243 * With strict mode for both IBPB and STIBP, the instruction
1244 * code paths avoid checking this task flag and instead,
1245 * unconditionally run the instruction. However, STIBP and IBPB
1246 * are independent and either can be set to conditionally
1247 * enabled regardless of the mode of the other.
1248 *
1249 * If either is set to conditional, allow the task flag to be
1250 * updated, unless it was force-disabled by a previous prctl
1251 * call. Currently, this is possible on an AMD CPU which has the
1252 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1253 * kernel is booted with 'spectre_v2_user=seccomp', then
1254 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1255 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1256 */
1257 if (!is_spec_ib_user_controlled() ||
1258 task_spec_ib_force_disable(task))
1259 return -EPERM;
1260
1261 task_clear_spec_ib_disable(task);
1262 task_update_spec_tif(task);
1263 break;
1264 case PR_SPEC_DISABLE:
1265 case PR_SPEC_FORCE_DISABLE:
1266 /*
1267 * Indirect branch speculation is always allowed when
1268 * mitigation is force disabled.
1269 */
1270 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1271 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1272 return -EPERM;
1273
1274 if (!is_spec_ib_user_controlled())
1275 return 0;
1276
1277 task_set_spec_ib_disable(task);
1278 if (ctrl == PR_SPEC_FORCE_DISABLE)
1279 task_set_spec_ib_force_disable(task);
1280 task_update_spec_tif(task);
1281 break;
1282 default:
1283 return -ERANGE;
1284 }
1285 return 0;
1286 }
1287
arch_prctl_spec_ctrl_set(struct task_struct * task,unsigned long which,unsigned long ctrl)1288 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1289 unsigned long ctrl)
1290 {
1291 switch (which) {
1292 case PR_SPEC_STORE_BYPASS:
1293 return ssb_prctl_set(task, ctrl);
1294 case PR_SPEC_INDIRECT_BRANCH:
1295 return ib_prctl_set(task, ctrl);
1296 default:
1297 return -ENODEV;
1298 }
1299 }
1300
1301 #ifdef CONFIG_SECCOMP
arch_seccomp_spec_mitigate(struct task_struct * task)1302 void arch_seccomp_spec_mitigate(struct task_struct *task)
1303 {
1304 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1305 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1306 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1307 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1308 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1309 }
1310 #endif
1311
ssb_prctl_get(struct task_struct * task)1312 static int ssb_prctl_get(struct task_struct *task)
1313 {
1314 switch (ssb_mode) {
1315 case SPEC_STORE_BYPASS_DISABLE:
1316 return PR_SPEC_DISABLE;
1317 case SPEC_STORE_BYPASS_SECCOMP:
1318 case SPEC_STORE_BYPASS_PRCTL:
1319 if (task_spec_ssb_force_disable(task))
1320 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1321 if (task_spec_ssb_disable(task))
1322 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1323 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1324 default:
1325 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1326 return PR_SPEC_ENABLE;
1327 return PR_SPEC_NOT_AFFECTED;
1328 }
1329 }
1330
ib_prctl_get(struct task_struct * task)1331 static int ib_prctl_get(struct task_struct *task)
1332 {
1333 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1334 return PR_SPEC_NOT_AFFECTED;
1335
1336 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1337 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1338 return PR_SPEC_ENABLE;
1339 else if (is_spec_ib_user_controlled()) {
1340 if (task_spec_ib_force_disable(task))
1341 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1342 if (task_spec_ib_disable(task))
1343 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1344 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1345 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1346 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1347 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1348 return PR_SPEC_DISABLE;
1349 else
1350 return PR_SPEC_NOT_AFFECTED;
1351 }
1352
arch_prctl_spec_ctrl_get(struct task_struct * task,unsigned long which)1353 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1354 {
1355 switch (which) {
1356 case PR_SPEC_STORE_BYPASS:
1357 return ssb_prctl_get(task);
1358 case PR_SPEC_INDIRECT_BRANCH:
1359 return ib_prctl_get(task);
1360 default:
1361 return -ENODEV;
1362 }
1363 }
1364
x86_spec_ctrl_setup_ap(void)1365 void x86_spec_ctrl_setup_ap(void)
1366 {
1367 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1368 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1369
1370 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1371 x86_amd_ssb_disable();
1372 }
1373
1374 #undef pr_fmt
1375 #define pr_fmt(fmt) "L1TF: " fmt
1376
1377 /*
1378 * These CPUs all support 44bits physical address space internally in the
1379 * cache but CPUID can report a smaller number of physical address bits.
1380 *
1381 * The L1TF mitigation uses the top most address bit for the inversion of
1382 * non present PTEs. When the installed memory reaches into the top most
1383 * address bit due to memory holes, which has been observed on machines
1384 * which report 36bits physical address bits and have 32G RAM installed,
1385 * then the mitigation range check in l1tf_select_mitigation() triggers.
1386 * This is a false positive because the mitigation is still possible due to
1387 * the fact that the cache uses 44bit internally. Use the cache bits
1388 * instead of the reported physical bits and adjust them on the affected
1389 * machines to 44bit if the reported bits are less than 44.
1390 */
override_cache_bits(struct cpuinfo_x86 * c)1391 static void override_cache_bits(struct cpuinfo_x86 *c)
1392 {
1393 if (c->x86 != 6)
1394 return;
1395
1396 switch (c->x86_model) {
1397 case INTEL_FAM6_NEHALEM:
1398 case INTEL_FAM6_WESTMERE:
1399 case INTEL_FAM6_SANDYBRIDGE:
1400 case INTEL_FAM6_IVYBRIDGE:
1401 case INTEL_FAM6_HASWELL_CORE:
1402 case INTEL_FAM6_HASWELL_ULT:
1403 case INTEL_FAM6_HASWELL_GT3E:
1404 case INTEL_FAM6_BROADWELL_CORE:
1405 case INTEL_FAM6_BROADWELL_GT3E:
1406 case INTEL_FAM6_SKYLAKE_MOBILE:
1407 case INTEL_FAM6_SKYLAKE_DESKTOP:
1408 case INTEL_FAM6_KABYLAKE_MOBILE:
1409 case INTEL_FAM6_KABYLAKE_DESKTOP:
1410 if (c->x86_cache_bits < 44)
1411 c->x86_cache_bits = 44;
1412 break;
1413 }
1414 }
1415
l1tf_select_mitigation(void)1416 static void __init l1tf_select_mitigation(void)
1417 {
1418 u64 half_pa;
1419
1420 if (!boot_cpu_has_bug(X86_BUG_L1TF))
1421 return;
1422
1423 override_cache_bits(&boot_cpu_data);
1424
1425 #if CONFIG_PGTABLE_LEVELS == 2
1426 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1427 return;
1428 #endif
1429
1430 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1431 if (e820_any_mapped(half_pa, ULLONG_MAX - half_pa, E820_RAM)) {
1432 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1433 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1434 half_pa);
1435 pr_info("However, doing so will make a part of your RAM unusable.\n");
1436 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1437 return;
1438 }
1439
1440 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1441 }
1442 #undef pr_fmt
1443 #define pr_fmt(fmt) fmt
1444
1445 #ifdef CONFIG_SYSFS
1446
itlb_multihit_show_state(char * buf)1447 static ssize_t itlb_multihit_show_state(char *buf)
1448 {
1449 return sprintf(buf, "Processor vulnerable\n");
1450 }
1451
mds_show_state(char * buf)1452 static ssize_t mds_show_state(char *buf)
1453 {
1454 #ifdef CONFIG_HYPERVISOR_GUEST
1455 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1456 return sprintf(buf, "%s; SMT Host state unknown\n",
1457 mds_strings[mds_mitigation]);
1458 }
1459 #endif
1460
1461 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
1462 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1463 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
1464 sched_smt_active() ? "mitigated" : "disabled"));
1465 }
1466
1467 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1468 sched_smt_active() ? "vulnerable" : "disabled");
1469 }
1470
tsx_async_abort_show_state(char * buf)1471 static ssize_t tsx_async_abort_show_state(char *buf)
1472 {
1473 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
1474 (taa_mitigation == TAA_MITIGATION_OFF))
1475 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
1476
1477 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1478 return sprintf(buf, "%s; SMT Host state unknown\n",
1479 taa_strings[taa_mitigation]);
1480 }
1481
1482 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
1483 sched_smt_active() ? "vulnerable" : "disabled");
1484 }
1485
stibp_state(void)1486 static char *stibp_state(void)
1487 {
1488 if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
1489 return "";
1490
1491 switch (spectre_v2_user_stibp) {
1492 case SPECTRE_V2_USER_NONE:
1493 return ", STIBP: disabled";
1494 case SPECTRE_V2_USER_STRICT:
1495 return ", STIBP: forced";
1496 case SPECTRE_V2_USER_STRICT_PREFERRED:
1497 return ", STIBP: always-on";
1498 case SPECTRE_V2_USER_PRCTL:
1499 case SPECTRE_V2_USER_SECCOMP:
1500 if (static_key_enabled(&switch_to_cond_stibp))
1501 return ", STIBP: conditional";
1502 }
1503 return "";
1504 }
1505
ibpb_state(void)1506 static char *ibpb_state(void)
1507 {
1508 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1509 if (static_key_enabled(&switch_mm_always_ibpb))
1510 return ", IBPB: always-on";
1511 if (static_key_enabled(&switch_mm_cond_ibpb))
1512 return ", IBPB: conditional";
1513 return ", IBPB: disabled";
1514 }
1515 return "";
1516 }
1517
srbds_show_state(char * buf)1518 static ssize_t srbds_show_state(char *buf)
1519 {
1520 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
1521 }
1522
cpu_show_common(struct device * dev,struct device_attribute * attr,char * buf,unsigned int bug)1523 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
1524 char *buf, unsigned int bug)
1525 {
1526 if (!boot_cpu_has_bug(bug))
1527 return sprintf(buf, "Not affected\n");
1528
1529 switch (bug) {
1530 case X86_BUG_CPU_MELTDOWN:
1531 if (boot_cpu_has(X86_FEATURE_KAISER))
1532 return sprintf(buf, "Mitigation: PTI\n");
1533
1534 break;
1535
1536 case X86_BUG_SPECTRE_V1:
1537 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
1538
1539 case X86_BUG_SPECTRE_V2:
1540 return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
1541 ibpb_state(),
1542 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
1543 stibp_state(),
1544 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
1545 spectre_v2_module_string());
1546
1547 case X86_BUG_SPEC_STORE_BYPASS:
1548 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
1549
1550 case X86_BUG_L1TF:
1551 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
1552 return sprintf(buf, "Mitigation: PTE Inversion\n");
1553 break;
1554
1555 case X86_BUG_MDS:
1556 return mds_show_state(buf);
1557
1558 case X86_BUG_TAA:
1559 return tsx_async_abort_show_state(buf);
1560
1561 case X86_BUG_ITLB_MULTIHIT:
1562 return itlb_multihit_show_state(buf);
1563
1564 case X86_BUG_SRBDS:
1565 return srbds_show_state(buf);
1566
1567 default:
1568 break;
1569 }
1570
1571 return sprintf(buf, "Vulnerable\n");
1572 }
1573
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)1574 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
1575 {
1576 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
1577 }
1578
cpu_show_spectre_v1(struct device * dev,struct device_attribute * attr,char * buf)1579 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
1580 {
1581 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
1582 }
1583
cpu_show_spectre_v2(struct device * dev,struct device_attribute * attr,char * buf)1584 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
1585 {
1586 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
1587 }
1588
cpu_show_spec_store_bypass(struct device * dev,struct device_attribute * attr,char * buf)1589 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
1590 {
1591 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
1592 }
1593
cpu_show_l1tf(struct device * dev,struct device_attribute * attr,char * buf)1594 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
1595 {
1596 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
1597 }
1598
cpu_show_mds(struct device * dev,struct device_attribute * attr,char * buf)1599 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
1600 {
1601 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
1602 }
1603
cpu_show_tsx_async_abort(struct device * dev,struct device_attribute * attr,char * buf)1604 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
1605 {
1606 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
1607 }
1608
cpu_show_itlb_multihit(struct device * dev,struct device_attribute * attr,char * buf)1609 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
1610 {
1611 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
1612 }
1613
cpu_show_srbds(struct device * dev,struct device_attribute * attr,char * buf)1614 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
1615 {
1616 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
1617 }
1618 #endif
1619