1 /*
2 * intel-mid.c: Intel MID platform setup code
3 *
4 * (C) Copyright 2008, 2012 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
6 * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
11 * of the License.
12 */
13
14 #define pr_fmt(fmt) "intel_mid: " fmt
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/interrupt.h>
19 #include <linux/scatterlist.h>
20 #include <linux/sfi.h>
21 #include <linux/irq.h>
22 #include <linux/module.h>
23 #include <linux/notifier.h>
24
25 #include <asm/setup.h>
26 #include <asm/mpspec_def.h>
27 #include <asm/hw_irq.h>
28 #include <asm/apic.h>
29 #include <asm/io_apic.h>
30 #include <asm/intel-mid.h>
31 #include <asm/intel_mid_vrtc.h>
32 #include <asm/io.h>
33 #include <asm/i8259.h>
34 #include <asm/intel_scu_ipc.h>
35 #include <asm/apb_timer.h>
36 #include <asm/reboot.h>
37
38 #include "intel_mid_weak_decls.h"
39
40 /*
41 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
42 * cmdline option x86_intel_mid_timer can be used to override the configuration
43 * to prefer one or the other.
44 * at runtime, there are basically three timer configurations:
45 * 1. per cpu apbt clock only
46 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
47 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
48 *
49 * by default (without cmdline option), platform code first detects cpu type
50 * to see if we are on lincroft or penwell, then set up both lapic or apbt
51 * clocks accordingly.
52 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
53 * config #3 is supported but not recommended on medfield.
54 *
55 * rating and feature summary:
56 * lapic (with C3STOP) --------- 100
57 * apbt (always-on) ------------ 110
58 * lapic (always-on,ARAT) ------ 150
59 */
60
61 enum intel_mid_timer_options intel_mid_timer_options;
62
63 /* intel_mid_ops to store sub arch ops */
64 static struct intel_mid_ops *intel_mid_ops;
65 /* getter function for sub arch ops*/
66 static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;
67 enum intel_mid_cpu_type __intel_mid_cpu_chip;
68 EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
69
intel_mid_power_off(void)70 static void intel_mid_power_off(void)
71 {
72 };
73
intel_mid_reboot(void)74 static void intel_mid_reboot(void)
75 {
76 intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
77 }
78
intel_mid_calibrate_tsc(void)79 static unsigned long __init intel_mid_calibrate_tsc(void)
80 {
81 return 0;
82 }
83
intel_mid_setup_bp_timer(void)84 static void __init intel_mid_setup_bp_timer(void)
85 {
86 apbt_time_init();
87 setup_boot_APIC_clock();
88 }
89
intel_mid_time_init(void)90 static void __init intel_mid_time_init(void)
91 {
92 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
93
94 switch (intel_mid_timer_options) {
95 case INTEL_MID_TIMER_APBT_ONLY:
96 break;
97 case INTEL_MID_TIMER_LAPIC_APBT:
98 /* Use apbt and local apic */
99 x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer;
100 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
101 return;
102 default:
103 if (!boot_cpu_has(X86_FEATURE_ARAT))
104 break;
105 /* Lapic only, no apbt */
106 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
107 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
108 return;
109 }
110
111 x86_init.timers.setup_percpu_clockev = apbt_time_init;
112 }
113
intel_mid_arch_setup(void)114 static void intel_mid_arch_setup(void)
115 {
116 if (boot_cpu_data.x86 != 6) {
117 pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
118 boot_cpu_data.x86, boot_cpu_data.x86_model);
119 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
120 goto out;
121 }
122
123 switch (boot_cpu_data.x86_model) {
124 case 0x35:
125 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
126 break;
127 case 0x3C:
128 case 0x4A:
129 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
130 break;
131 case 0x27:
132 default:
133 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
134 break;
135 }
136
137 if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops))
138 intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
139 else {
140 intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
141 pr_info("ARCH: Unknown SoC, assuming PENWELL!\n");
142 }
143
144 out:
145 if (intel_mid_ops->arch_setup)
146 intel_mid_ops->arch_setup();
147 }
148
149 /* MID systems don't have i8042 controller */
intel_mid_i8042_detect(void)150 static int intel_mid_i8042_detect(void)
151 {
152 return 0;
153 }
154
155 /*
156 * Moorestown does not have external NMI source nor port 0x61 to report
157 * NMI status. The possible NMI sources are from pmu as a result of NMI
158 * watchdog or lock debug. Reading io port 0x61 results in 0xff which
159 * misled NMI handler.
160 */
intel_mid_get_nmi_reason(void)161 static unsigned char intel_mid_get_nmi_reason(void)
162 {
163 return 0;
164 }
165
166 /*
167 * Moorestown specific x86_init function overrides and early setup
168 * calls.
169 */
x86_intel_mid_early_setup(void)170 void __init x86_intel_mid_early_setup(void)
171 {
172 x86_init.resources.probe_roms = x86_init_noop;
173 x86_init.resources.reserve_resources = x86_init_noop;
174
175 x86_init.timers.timer_init = intel_mid_time_init;
176 x86_init.timers.setup_percpu_clockev = x86_init_noop;
177
178 x86_init.irqs.pre_vector_init = x86_init_noop;
179
180 x86_init.oem.arch_setup = intel_mid_arch_setup;
181
182 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
183
184 x86_platform.calibrate_tsc = intel_mid_calibrate_tsc;
185 x86_platform.i8042_detect = intel_mid_i8042_detect;
186 x86_init.timers.wallclock_init = intel_mid_rtc_init;
187 x86_platform.get_nmi_reason = intel_mid_get_nmi_reason;
188
189 x86_init.pci.init = intel_mid_pci_init;
190 x86_init.pci.fixup_irqs = x86_init_noop;
191
192 legacy_pic = &null_legacy_pic;
193
194 pm_power_off = intel_mid_power_off;
195 machine_ops.emergency_restart = intel_mid_reboot;
196
197 /* Avoid searching for BIOS MP tables */
198 x86_init.mpparse.find_smp_config = x86_init_noop;
199 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
200 set_bit(MP_BUS_ISA, mp_bus_not_pci);
201 }
202
203 /*
204 * if user does not want to use per CPU apb timer, just give it a lower rating
205 * than local apic timer and skip the late per cpu timer init.
206 */
setup_x86_intel_mid_timer(char * arg)207 static inline int __init setup_x86_intel_mid_timer(char *arg)
208 {
209 if (!arg)
210 return -EINVAL;
211
212 if (strcmp("apbt_only", arg) == 0)
213 intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY;
214 else if (strcmp("lapic_and_apbt", arg) == 0)
215 intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT;
216 else {
217 pr_warn("X86 INTEL_MID timer option %s not recognised"
218 " use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
219 arg);
220 return -EINVAL;
221 }
222 return 0;
223 }
224 __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer);
225
226