1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001 - 2008 Tensilica Inc.
7 * Copyright (C) 2015 Cadence Design Systems Inc.
8 */
9
10 #ifndef _XTENSA_PROCESSOR_H
11 #define _XTENSA_PROCESSOR_H
12
13 #include <variant/core.h>
14 #include <platform/hardware.h>
15
16 #include <linux/compiler.h>
17 #include <asm/ptrace.h>
18 #include <asm/types.h>
19 #include <asm/regs.h>
20
21 /* Assertions. */
22
23 #if (XCHAL_HAVE_WINDOWED != 1)
24 # error Linux requires the Xtensa Windowed Registers Option.
25 #endif
26
27 /* Xtensa ABI requires stack alignment to be at least 16 */
28
29 #define STACK_ALIGN (XCHAL_DATA_WIDTH > 16 ? XCHAL_DATA_WIDTH : 16)
30
31 #define ARCH_SLAB_MINALIGN STACK_ALIGN
32
33 /*
34 * User space process size: 1 GB.
35 * Windowed call ABI requires caller and callee to be located within the same
36 * 1 GB region. The C compiler places trampoline code on the stack for sources
37 * that take the address of a nested C function (a feature used by glibc), so
38 * the 1 GB requirement applies to the stack as well.
39 */
40
41 #ifdef CONFIG_MMU
42 #define TASK_SIZE __XTENSA_UL_CONST(0x40000000)
43 #else
44 #define TASK_SIZE (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
45 #endif
46
47 #define STACK_TOP TASK_SIZE
48 #define STACK_TOP_MAX STACK_TOP
49
50 /*
51 * General exception cause assigned to fake NMI. Fake NMI needs to be handled
52 * differently from other interrupts, but it uses common kernel entry/exit
53 * code.
54 */
55
56 #define EXCCAUSE_MAPPED_NMI 62
57
58 /*
59 * General exception cause assigned to debug exceptions. Debug exceptions go
60 * to their own vector, rather than the general exception vectors (user,
61 * kernel, double); and their specific causes are reported via DEBUGCAUSE
62 * rather than EXCCAUSE. However it is sometimes convenient to redirect debug
63 * exceptions to the general exception mechanism. To do this, an otherwise
64 * unused EXCCAUSE value was assigned to debug exceptions for this purpose.
65 */
66
67 #define EXCCAUSE_MAPPED_DEBUG 63
68
69 /*
70 * We use DEPC also as a flag to distinguish between double and regular
71 * exceptions. For performance reasons, DEPC might contain the value of
72 * EXCCAUSE for regular exceptions, so we use this definition to mark a
73 * valid double exception address.
74 * (Note: We use it in bgeui, so it should be 64, 128, or 256)
75 */
76
77 #define VALID_DOUBLE_EXCEPTION_ADDRESS 64
78
79 #define XTENSA_INT_LEVEL(intno) _XTENSA_INT_LEVEL(intno)
80 #define _XTENSA_INT_LEVEL(intno) XCHAL_INT##intno##_LEVEL
81
82 #define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level)
83 #define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK)
84
85 #define IS_POW2(v) (((v) & ((v) - 1)) == 0)
86
87 #define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT)
88
89 /* LOCKLEVEL defines the interrupt level that masks all
90 * general-purpose interrupts.
91 */
92 #if defined(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) && \
93 defined(XCHAL_PROFILING_INTERRUPT) && \
94 PROFILING_INTLEVEL == XCHAL_EXCM_LEVEL && \
95 XCHAL_EXCM_LEVEL > 1 && \
96 IS_POW2(XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL))
97 #define LOCKLEVEL (XCHAL_EXCM_LEVEL - 1)
98 #else
99 #define LOCKLEVEL XCHAL_EXCM_LEVEL
100 #endif
101 #define TOPLEVEL XCHAL_EXCM_LEVEL
102 #define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL)
103
104 /* WSBITS and WBBITS are the width of the WINDOWSTART and WINDOWBASE
105 * registers
106 */
107 #define WSBITS (XCHAL_NUM_AREGS / 4) /* width of WINDOWSTART in bits */
108 #define WBBITS (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE in bits */
109
110 #ifndef __ASSEMBLY__
111
112 /* Build a valid return address for the specified call winsize.
113 * winsize must be 1 (call4), 2 (call8), or 3 (call12)
114 */
115 #define MAKE_RA_FOR_CALL(ra,ws) (((ra) & 0x3fffffff) | (ws) << 30)
116
117 /* Convert return address to a valid pc
118 * Note: We assume that the stack pointer is in the same 1GB ranges as the ra
119 */
120 #define MAKE_PC_FROM_RA(ra,sp) (((ra) & 0x3fffffff) | ((sp) & 0xc0000000))
121
122 typedef struct {
123 unsigned long seg;
124 } mm_segment_t;
125
126 struct thread_struct {
127
128 /* kernel's return address and stack pointer for context switching */
129 unsigned long ra; /* kernel's a0: return address and window call size */
130 unsigned long sp; /* kernel's a1: stack pointer */
131
132 mm_segment_t current_ds; /* see uaccess.h for example uses */
133
134 /* struct xtensa_cpuinfo info; */
135
136 unsigned long bad_vaddr; /* last user fault */
137 unsigned long bad_uaddr; /* last kernel fault accessing user space */
138 unsigned long error_code;
139
140 unsigned long ibreak[XCHAL_NUM_IBREAK];
141 unsigned long dbreaka[XCHAL_NUM_DBREAK];
142 unsigned long dbreakc[XCHAL_NUM_DBREAK];
143
144 /* Make structure 16 bytes aligned. */
145 int align[0] __attribute__ ((aligned(16)));
146 };
147
148
149 /*
150 * Default implementation of macro that returns current
151 * instruction pointer ("program counter").
152 */
153 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
154
155
156 /* This decides where the kernel will search for a free chunk of vm
157 * space during mmap's.
158 */
159 #define TASK_UNMAPPED_BASE (TASK_SIZE / 2)
160
161 #define INIT_THREAD \
162 { \
163 ra: 0, \
164 sp: sizeof(init_stack) + (long) &init_stack, \
165 current_ds: {0}, \
166 /*info: {0}, */ \
167 bad_vaddr: 0, \
168 bad_uaddr: 0, \
169 error_code: 0, \
170 }
171
172
173 /*
174 * Do necessary setup to start up a newly executed thread.
175 * Note: We set-up ps as if we did a call4 to the new pc.
176 * set_thread_state in signal.c depends on it.
177 */
178 #define USER_PS_VALUE ((1 << PS_WOE_BIT) | \
179 (1 << PS_CALLINC_SHIFT) | \
180 (USER_RING << PS_RING_SHIFT) | \
181 (1 << PS_UM_BIT) | \
182 (1 << PS_EXCM_BIT))
183
184 /* Clearing a0 terminates the backtrace. */
185 #define start_thread(regs, new_pc, new_sp) \
186 memset(regs, 0, sizeof(*regs)); \
187 regs->pc = new_pc; \
188 regs->ps = USER_PS_VALUE; \
189 regs->areg[1] = new_sp; \
190 regs->areg[0] = 0; \
191 regs->wmask = 1; \
192 regs->depc = 0; \
193 regs->windowbase = 0; \
194 regs->windowstart = 1;
195
196 /* Forward declaration */
197 struct task_struct;
198 struct mm_struct;
199
200 /* Free all resources held by a thread. */
201 #define release_thread(thread) do { } while(0)
202
203 /* Copy and release all segment info associated with a VM */
204 #define copy_segments(p, mm) do { } while(0)
205 #define release_segments(mm) do { } while(0)
206 #define forget_segments() do { } while (0)
207
208 #define thread_saved_pc(tsk) (task_pt_regs(tsk)->pc)
209
210 extern unsigned long get_wchan(struct task_struct *p);
211
212 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
213 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->areg[1])
214
215 #define cpu_relax() barrier()
216 #define cpu_relax_lowlatency() cpu_relax()
217
218 /* Special register access. */
219
220 #define WSR(v,sr) __asm__ __volatile__ ("wsr %0,"__stringify(sr) :: "a"(v));
221 #define RSR(v,sr) __asm__ __volatile__ ("rsr %0,"__stringify(sr) : "=a"(v));
222
223 #define set_sr(x,sr) ({unsigned int v=(unsigned int)x; WSR(v,sr);})
224 #define get_sr(sr) ({unsigned int v; RSR(v,sr); v; })
225
226 #ifndef XCHAL_HAVE_EXTERN_REGS
227 #define XCHAL_HAVE_EXTERN_REGS 0
228 #endif
229
230 #if XCHAL_HAVE_EXTERN_REGS
231
set_er(unsigned long value,unsigned long addr)232 static inline void set_er(unsigned long value, unsigned long addr)
233 {
234 asm volatile ("wer %0, %1" : : "a" (value), "a" (addr) : "memory");
235 }
236
get_er(unsigned long addr)237 static inline unsigned long get_er(unsigned long addr)
238 {
239 register unsigned long value;
240 asm volatile ("rer %0, %1" : "=a" (value) : "a" (addr) : "memory");
241 return value;
242 }
243
244 #endif /* XCHAL_HAVE_EXTERN_REGS */
245
246 #endif /* __ASSEMBLY__ */
247 #endif /* _XTENSA_PROCESSOR_H */
248