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1 /*
2  * Xtensa processor core configuration information.
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1999-2006 Tensilica Inc.
9  */
10 
11 #ifndef _XTENSA_CORE_H
12 #define _XTENSA_CORE_H
13 
14 
15 /****************************************************************************
16 	    Parameters Useful for Any Code, USER or PRIVILEGED
17  ****************************************************************************/
18 
19 /*
20  *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
21  *  configured, and a value of 0 otherwise.  These macros are always defined.
22  */
23 
24 
25 /*----------------------------------------------------------------------
26 				ISA
27   ----------------------------------------------------------------------*/
28 
29 #define XCHAL_HAVE_BE			1	/* big-endian byte ordering */
30 #define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
31 #define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
32 #define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
33 #define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
34 #define XCHAL_HAVE_DEBUG		1	/* debug option */
35 #define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
36 #define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
37 #define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
38 #define XCHAL_HAVE_MINMAX		0	/* MIN/MAX instructions */
39 #define XCHAL_HAVE_SEXT			0	/* SEXT instruction */
40 #define XCHAL_HAVE_CLAMPS		0	/* CLAMPS instruction */
41 #define XCHAL_HAVE_MUL16		0	/* MUL16S/MUL16U instructions */
42 #define XCHAL_HAVE_MUL32		0	/* MULL instruction */
43 #define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
44 #define XCHAL_HAVE_L32R			1	/* L32R instruction */
45 #define XCHAL_HAVE_ABSOLUTE_LITERALS	1	/* non-PC-rel (extended) L32R */
46 #define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
47 #define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
48 #define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
49 #define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
50 #define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
51 #define XCHAL_HAVE_ABS			1	/* ABS instruction */
52 /*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
53 /*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
54 #define XCHAL_HAVE_RELEASE_SYNC		0	/* L32AI/S32RI instructions */
55 #define XCHAL_HAVE_S32C1I		0	/* S32C1I instruction */
56 #define XCHAL_HAVE_SPECULATION		0	/* speculation */
57 #define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
58 #define XCHAL_NUM_CONTEXTS		1	/* */
59 #define XCHAL_NUM_MISC_REGS		2	/* num of scratch regs (0..4) */
60 #define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
61 #define XCHAL_HAVE_PRID			1	/* processor ID register */
62 #define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
63 #define XCHAL_HAVE_BOOLEANS		0	/* boolean registers */
64 #define XCHAL_HAVE_CP			0	/* CPENABLE reg (coprocessor) */
65 #define XCHAL_CP_MAXCFG			0	/* max allowed cp id plus one */
66 #define XCHAL_HAVE_MAC16		0	/* MAC16 package */
67 #define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
68 #define XCHAL_HAVE_FP			0	/* floating point pkg */
69 #define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
70 #define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
71 #define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
72 
73 
74 /*----------------------------------------------------------------------
75 				MISC
76   ----------------------------------------------------------------------*/
77 
78 #define XCHAL_NUM_WRITEBUFFER_ENTRIES	4	/* size of write buffer */
79 #define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
80 #define XCHAL_DATA_WIDTH		4	/* data width in bytes */
81 /*  In T1050, applies to selected core load and store instructions (see ISA): */
82 #define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
83 #define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
84 
85 #define XCHAL_CORE_ID			"fsf"	/* alphanum core name
86 						   (CoreID) set in the Xtensa
87 						   Processor Generator */
88 
89 #define XCHAL_BUILD_UNIQUE_ID		0x00006700	/* 22-bit sw build ID */
90 
91 /*
92  *  These definitions describe the hardware targeted by this software.
93  */
94 #define XCHAL_HW_CONFIGID0		0xC103C3FF	/* ConfigID hi 32 bits*/
95 #define XCHAL_HW_CONFIGID1		0x0C006700	/* ConfigID lo 32 bits*/
96 #define XCHAL_HW_VERSION_NAME		"LX2.0.0"	/* full version name */
97 #define XCHAL_HW_VERSION_MAJOR		2200	/* major ver# of targeted hw */
98 #define XCHAL_HW_VERSION_MINOR		0	/* minor ver# of targeted hw */
99 #define XTHAL_HW_REL_LX2		1
100 #define XTHAL_HW_REL_LX2_0		1
101 #define XTHAL_HW_REL_LX2_0_0		1
102 #define XCHAL_HW_CONFIGID_RELIABLE	1
103 /*  If software targets a *range* of hardware versions, these are the bounds: */
104 #define XCHAL_HW_MIN_VERSION_MAJOR	2200	/* major v of earliest tgt hw */
105 #define XCHAL_HW_MIN_VERSION_MINOR	0	/* minor v of earliest tgt hw */
106 #define XCHAL_HW_MAX_VERSION_MAJOR	2200	/* major v of latest tgt hw */
107 #define XCHAL_HW_MAX_VERSION_MINOR	0	/* minor v of latest tgt hw */
108 
109 
110 /*----------------------------------------------------------------------
111 				CACHE
112   ----------------------------------------------------------------------*/
113 
114 #define XCHAL_ICACHE_LINESIZE		16	/* I-cache line size in bytes */
115 #define XCHAL_DCACHE_LINESIZE		16	/* D-cache line size in bytes */
116 #define XCHAL_ICACHE_LINEWIDTH		4	/* log2(I line size in bytes) */
117 #define XCHAL_DCACHE_LINEWIDTH		4	/* log2(D line size in bytes) */
118 
119 #define XCHAL_ICACHE_SIZE		8192	/* I-cache size in bytes or 0 */
120 #define XCHAL_DCACHE_SIZE		8192	/* D-cache size in bytes or 0 */
121 
122 #define XCHAL_DCACHE_IS_WRITEBACK	0	/* writeback feature */
123 
124 
125 
126 
127 /****************************************************************************
128     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
129  ****************************************************************************/
130 
131 
132 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
133 
134 /*----------------------------------------------------------------------
135 				CACHE
136   ----------------------------------------------------------------------*/
137 
138 #define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
139 
140 /*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
141 
142 /*  Number of cache sets in log2(lines per way):  */
143 #define XCHAL_ICACHE_SETWIDTH		8
144 #define XCHAL_DCACHE_SETWIDTH		8
145 
146 /*  Cache set associativity (number of ways):  */
147 #define XCHAL_ICACHE_WAYS		2
148 #define XCHAL_DCACHE_WAYS		2
149 
150 /*  Cache features:  */
151 #define XCHAL_ICACHE_LINE_LOCKABLE	0
152 #define XCHAL_DCACHE_LINE_LOCKABLE	0
153 #define XCHAL_ICACHE_ECC_PARITY		0
154 #define XCHAL_DCACHE_ECC_PARITY		0
155 
156 /*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
157 #define XCHAL_CA_BITS			4
158 
159 
160 /*----------------------------------------------------------------------
161 			INTERNAL I/D RAM/ROMs and XLMI
162   ----------------------------------------------------------------------*/
163 
164 #define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
165 #define XCHAL_NUM_INSTRAM		0	/* number of core instr. RAMs */
166 #define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
167 #define XCHAL_NUM_DATARAM		0	/* number of core data RAMs */
168 #define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
169 #define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
170 
171 
172 /*----------------------------------------------------------------------
173 			INTERRUPTS and TIMERS
174   ----------------------------------------------------------------------*/
175 
176 #define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
177 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
178 #define XCHAL_HAVE_NMI			0	/* non-maskable interrupt */
179 #define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
180 #define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
181 #define XCHAL_NUM_INTERRUPTS		17	/* number of interrupts */
182 #define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
183 #define XCHAL_NUM_EXTINTERRUPTS		10	/* num of external interrupts */
184 #define XCHAL_NUM_INTLEVELS		4	/* number of interrupt levels
185 						   (not including level zero) */
186 #define XCHAL_EXCM_LEVEL		1	/* level masked by PS.EXCM */
187 	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
188 
189 /*  Masks of interrupts at each interrupt level:  */
190 #define XCHAL_INTLEVEL1_MASK		0x000064F9
191 #define XCHAL_INTLEVEL2_MASK		0x00008902
192 #define XCHAL_INTLEVEL3_MASK		0x00011204
193 #define XCHAL_INTLEVEL4_MASK		0x00000000
194 #define XCHAL_INTLEVEL5_MASK		0x00000000
195 #define XCHAL_INTLEVEL6_MASK		0x00000000
196 #define XCHAL_INTLEVEL7_MASK		0x00000000
197 
198 /*  Masks of interrupts at each range 1..n of interrupt levels:  */
199 #define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x000064F9
200 #define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x0000EDFB
201 #define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x0001FFFF
202 #define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x0001FFFF
203 #define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x0001FFFF
204 #define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x0001FFFF
205 #define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x0001FFFF
206 
207 /*  Level of each interrupt:  */
208 #define XCHAL_INT0_LEVEL		1
209 #define XCHAL_INT1_LEVEL		2
210 #define XCHAL_INT2_LEVEL		3
211 #define XCHAL_INT3_LEVEL		1
212 #define XCHAL_INT4_LEVEL		1
213 #define XCHAL_INT5_LEVEL		1
214 #define XCHAL_INT6_LEVEL		1
215 #define XCHAL_INT7_LEVEL		1
216 #define XCHAL_INT8_LEVEL		2
217 #define XCHAL_INT9_LEVEL		3
218 #define XCHAL_INT10_LEVEL		1
219 #define XCHAL_INT11_LEVEL		2
220 #define XCHAL_INT12_LEVEL		3
221 #define XCHAL_INT13_LEVEL		1
222 #define XCHAL_INT14_LEVEL		1
223 #define XCHAL_INT15_LEVEL		2
224 #define XCHAL_INT16_LEVEL		3
225 #define XCHAL_DEBUGLEVEL		4	/* debug interrupt level */
226 #define XCHAL_HAVE_DEBUG_EXTERN_INT	0	/* OCD external db interrupt */
227 
228 /*  Type of each interrupt:  */
229 #define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
230 #define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
231 #define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
232 #define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
233 #define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
234 #define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
235 #define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
236 #define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
237 #define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
238 #define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
239 #define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
240 #define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_TIMER
241 #define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_TIMER
242 #define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_SOFTWARE
243 #define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_SOFTWARE
244 #define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_SOFTWARE
245 #define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_SOFTWARE
246 
247 /*  Masks of interrupts for each type of interrupt:  */
248 #define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFFE0000
249 #define XCHAL_INTTYPE_MASK_SOFTWARE	0x0001E000
250 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x00000380
251 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x0000007F
252 #define XCHAL_INTTYPE_MASK_TIMER	0x00001C00
253 #define XCHAL_INTTYPE_MASK_NMI		0x00000000
254 #define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
255 
256 /*  Interrupt numbers assigned to specific interrupt sources:  */
257 #define XCHAL_TIMER0_INTERRUPT		10	/* CCOMPARE0 */
258 #define XCHAL_TIMER1_INTERRUPT		11	/* CCOMPARE1 */
259 #define XCHAL_TIMER2_INTERRUPT		12	/* CCOMPARE2 */
260 #define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
261 
262 /*  Interrupt numbers for levels at which only one interrupt is configured:  */
263 /*  (There are many interrupts each at level(s) 1, 2, 3.)  */
264 
265 
266 /*
267  *  External interrupt vectors/levels.
268  *  These macros describe how Xtensa processor interrupt numbers
269  *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
270  *  map to external BInterrupt<n> pins, for those interrupts
271  *  configured as external (level-triggered, edge-triggered, or NMI).
272  *  See the Xtensa processor databook for more details.
273  */
274 
275 /*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
276 #define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
277 #define XCHAL_EXTINT1_NUM		1	/* (intlevel 2) */
278 #define XCHAL_EXTINT2_NUM		2	/* (intlevel 3) */
279 #define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
280 #define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
281 #define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
282 #define XCHAL_EXTINT6_NUM		6	/* (intlevel 1) */
283 #define XCHAL_EXTINT7_NUM		7	/* (intlevel 1) */
284 #define XCHAL_EXTINT8_NUM		8	/* (intlevel 2) */
285 #define XCHAL_EXTINT9_NUM		9	/* (intlevel 3) */
286 
287 
288 /*----------------------------------------------------------------------
289 			EXCEPTIONS and VECTORS
290   ----------------------------------------------------------------------*/
291 
292 #define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
293 						   number: 1 == XEA1 (old)
294 							   2 == XEA2 (new)
295 							   0 == XEAX (extern) */
296 #define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
297 #define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
298 #define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
299 #define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
300 #define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
301 
302 #define XCHAL_RESET_VECTOR_VADDR	0xFE000020
303 #define XCHAL_RESET_VECTOR_PADDR	0xFE000020
304 #define XCHAL_USER_VECTOR_VADDR		0xD0000220
305 #define XCHAL_USER_VECTOR_PADDR		0x00000220
306 #define XCHAL_KERNEL_VECTOR_VADDR	0xD0000200
307 #define XCHAL_KERNEL_VECTOR_PADDR	0x00000200
308 #define XCHAL_DOUBLEEXC_VECTOR_VADDR	0xD0000290
309 #define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x00000290
310 #define XCHAL_WINDOW_VECTORS_VADDR	0xD0000000
311 #define XCHAL_WINDOW_VECTORS_PADDR	0x00000000
312 #define XCHAL_INTLEVEL2_VECTOR_VADDR	0xD0000240
313 #define XCHAL_INTLEVEL2_VECTOR_PADDR	0x00000240
314 #define XCHAL_INTLEVEL3_VECTOR_VADDR	0xD0000250
315 #define XCHAL_INTLEVEL3_VECTOR_PADDR	0x00000250
316 #define XCHAL_INTLEVEL4_VECTOR_VADDR	0xFE000520
317 #define XCHAL_INTLEVEL4_VECTOR_PADDR	0xFE000520
318 #define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL4_VECTOR_VADDR
319 #define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL4_VECTOR_PADDR
320 
321 
322 /*----------------------------------------------------------------------
323 				DEBUG
324   ----------------------------------------------------------------------*/
325 
326 #define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
327 #define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
328 #define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
329 #define XCHAL_HAVE_OCD_DIR_ARRAY	1	/* faster OCD option */
330 
331 
332 /*----------------------------------------------------------------------
333 				MMU
334   ----------------------------------------------------------------------*/
335 
336 /*  See <xtensa/config/core-matmap.h> header file for more details.  */
337 
338 #define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
339 #define XCHAL_HAVE_SPANNING_WAY		0	/* one way maps I+D 4GB vaddr */
340 #define XCHAL_HAVE_IDENTITY_MAP		0	/* vaddr == paddr always */
341 #define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
342 #define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
343 #define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
344 #define XCHAL_HAVE_PTP_MMU		1	/* full MMU (with page table
345 						   [autorefill] and protection)
346 						   usable for an MMU-based OS */
347 /*  If none of the above last 4 are set, it's a custom TLB configuration.  */
348 #define XCHAL_ITLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
349 #define XCHAL_DTLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
350 
351 #define XCHAL_MMU_ASID_BITS		8	/* number of bits in ASIDs */
352 #define XCHAL_MMU_RINGS			4	/* number of rings (1..4) */
353 #define XCHAL_MMU_RING_BITS		2	/* num of bits in RING field */
354 
355 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
356 
357 
358 #endif /* _XTENSA_CORE_CONFIGURATION_H */
359 
360