1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22
23 #include <scsi/scsi_host.h>
24 #include <scsi/scsi_cmnd.h>
25 #include <linux/libata.h>
26 #include <asm/io.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30
31 static unsigned int intr_coalescing_count;
32 module_param(intr_coalescing_count, int, S_IRUGO);
33 MODULE_PARM_DESC(intr_coalescing_count,
34 "INT coalescing count threshold (1..31)");
35
36 static unsigned int intr_coalescing_ticks;
37 module_param(intr_coalescing_ticks, int, S_IRUGO);
38 MODULE_PARM_DESC(intr_coalescing_ticks,
39 "INT coalescing timer threshold in AHB ticks");
40 /* Controller information */
41 enum {
42 SATA_FSL_QUEUE_DEPTH = 16,
43 SATA_FSL_MAX_PRD = 63,
44 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
45 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
46
47 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
48 ATA_FLAG_PMP | ATA_FLAG_NCQ |
49 ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE),
50
51 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
52 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
53 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
54
55 /*
56 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
57 * chained indirect PRDEs up to a max count of 63.
58 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
59 * be setup as an indirect descriptor, pointing to it's next
60 * (contiguous) PRDE. Though chained indirect PRDE arrays are
61 * supported,it will be more efficient to use a direct PRDT and
62 * a single chain/link to indirect PRDE array/PRDT.
63 */
64
65 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
66 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
67 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
68 SATA_FSL_CMD_DESC_RSRVD = 16,
69
70 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
71 SATA_FSL_CMD_DESC_SFIS_SZ +
72 SATA_FSL_CMD_DESC_ACMD_SZ +
73 SATA_FSL_CMD_DESC_RSRVD +
74 SATA_FSL_MAX_PRD * 16),
75
76 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
77 (SATA_FSL_CMD_DESC_CFIS_SZ +
78 SATA_FSL_CMD_DESC_SFIS_SZ +
79 SATA_FSL_CMD_DESC_ACMD_SZ +
80 SATA_FSL_CMD_DESC_RSRVD),
81
82 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
83 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
84 SATA_FSL_CMD_DESC_AR_SZ),
85
86 /*
87 * MPC8315 has two SATA controllers, SATA1 & SATA2
88 * (one port per controller)
89 * MPC837x has 2/4 controllers, one port per controller
90 */
91
92 SATA_FSL_MAX_PORTS = 1,
93
94 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
95 };
96
97 /*
98 * Interrupt Coalescing Control Register bitdefs */
99 enum {
100 ICC_MIN_INT_COUNT_THRESHOLD = 1,
101 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
102 ICC_MIN_INT_TICKS_THRESHOLD = 0,
103 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
104 ICC_SAFE_INT_TICKS = 1,
105 };
106
107 /*
108 * Host Controller command register set - per port
109 */
110 enum {
111 CQ = 0,
112 CA = 8,
113 CC = 0x10,
114 CE = 0x18,
115 DE = 0x20,
116 CHBA = 0x24,
117 HSTATUS = 0x28,
118 HCONTROL = 0x2C,
119 CQPMP = 0x30,
120 SIGNATURE = 0x34,
121 ICC = 0x38,
122
123 /*
124 * Host Status Register (HStatus) bitdefs
125 */
126 ONLINE = (1 << 31),
127 GOING_OFFLINE = (1 << 30),
128 BIST_ERR = (1 << 29),
129 CLEAR_ERROR = (1 << 27),
130
131 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
132 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
133 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
134 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
135 FATAL_ERR_DATA_OVERRUN = (1 << 12),
136 FATAL_ERR_CRC_ERR_TX = (1 << 11),
137 FATAL_ERR_CRC_ERR_RX = (1 << 10),
138 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
139 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
140
141 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
142 FATAL_ERR_PARITY_ERR_TX |
143 FATAL_ERR_PARITY_ERR_RX |
144 FATAL_ERR_DATA_UNDERRUN |
145 FATAL_ERR_DATA_OVERRUN |
146 FATAL_ERR_CRC_ERR_TX |
147 FATAL_ERR_CRC_ERR_RX |
148 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
149
150 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
151 INT_ON_FATAL_ERR = (1 << 5),
152 INT_ON_PHYRDY_CHG = (1 << 4),
153
154 INT_ON_SIGNATURE_UPDATE = (1 << 3),
155 INT_ON_SNOTIFY_UPDATE = (1 << 2),
156 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
157 INT_ON_CMD_COMPLETE = 1,
158
159 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
160 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
161
162 /*
163 * Host Control Register (HControl) bitdefs
164 */
165 HCONTROL_ONLINE_PHY_RST = (1 << 31),
166 HCONTROL_FORCE_OFFLINE = (1 << 30),
167 HCONTROL_LEGACY = (1 << 28),
168 HCONTROL_PARITY_PROT_MOD = (1 << 14),
169 HCONTROL_DPATH_PARITY = (1 << 12),
170 HCONTROL_SNOOP_ENABLE = (1 << 10),
171 HCONTROL_PMP_ATTACHED = (1 << 9),
172 HCONTROL_COPYOUT_STATFIS = (1 << 8),
173 IE_ON_FATAL_ERR = (1 << 5),
174 IE_ON_PHYRDY_CHG = (1 << 4),
175 IE_ON_SIGNATURE_UPDATE = (1 << 3),
176 IE_ON_SNOTIFY_UPDATE = (1 << 2),
177 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
178 IE_ON_CMD_COMPLETE = 1,
179
180 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
181 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
182 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
183
184 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
185 DATA_SNOOP_ENABLE_V1 = (1 << 22),
186 DATA_SNOOP_ENABLE_V2 = (1 << 28),
187 };
188
189 /*
190 * SATA Superset Registers
191 */
192 enum {
193 SSTATUS = 0,
194 SERROR = 4,
195 SCONTROL = 8,
196 SNOTIFY = 0xC,
197 };
198
199 /*
200 * Control Status Register Set
201 */
202 enum {
203 TRANSCFG = 0,
204 TRANSSTATUS = 4,
205 LINKCFG = 8,
206 LINKCFG1 = 0xC,
207 LINKCFG2 = 0x10,
208 LINKSTATUS = 0x14,
209 LINKSTATUS1 = 0x18,
210 PHYCTRLCFG = 0x1C,
211 COMMANDSTAT = 0x20,
212 };
213
214 /* TRANSCFG (transport-layer) configuration control */
215 enum {
216 TRANSCFG_RX_WATER_MARK = (1 << 4),
217 };
218
219 /* PHY (link-layer) configuration control */
220 enum {
221 PHY_BIST_ENABLE = 0x01,
222 };
223
224 /*
225 * Command Header Table entry, i.e, command slot
226 * 4 Dwords per command slot, command header size == 64 Dwords.
227 */
228 struct cmdhdr_tbl_entry {
229 u32 cda;
230 u32 prde_fis_len;
231 u32 ttl;
232 u32 desc_info;
233 };
234
235 /*
236 * Description information bitdefs
237 */
238 enum {
239 CMD_DESC_RES = (1 << 11),
240 VENDOR_SPECIFIC_BIST = (1 << 10),
241 CMD_DESC_SNOOP_ENABLE = (1 << 9),
242 FPDMA_QUEUED_CMD = (1 << 8),
243 SRST_CMD = (1 << 7),
244 BIST = (1 << 6),
245 ATAPI_CMD = (1 << 5),
246 };
247
248 /*
249 * Command Descriptor
250 */
251 struct command_desc {
252 u8 cfis[8 * 4];
253 u8 sfis[8 * 4];
254 u8 acmd[4 * 4];
255 u8 fill[4 * 4];
256 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
257 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
258 };
259
260 /*
261 * Physical region table descriptor(PRD)
262 */
263
264 struct prde {
265 u32 dba;
266 u8 fill[2 * 4];
267 u32 ddc_and_ext;
268 };
269
270 /*
271 * ata_port private data
272 * This is our per-port instance data.
273 */
274 struct sata_fsl_port_priv {
275 struct cmdhdr_tbl_entry *cmdslot;
276 dma_addr_t cmdslot_paddr;
277 struct command_desc *cmdentry;
278 dma_addr_t cmdentry_paddr;
279 };
280
281 /*
282 * ata_port->host_set private data
283 */
284 struct sata_fsl_host_priv {
285 void __iomem *hcr_base;
286 void __iomem *ssr_base;
287 void __iomem *csr_base;
288 int irq;
289 int data_snoop;
290 struct device_attribute intr_coalescing;
291 struct device_attribute rx_watermark;
292 };
293
fsl_sata_set_irq_coalescing(struct ata_host * host,unsigned int count,unsigned int ticks)294 static void fsl_sata_set_irq_coalescing(struct ata_host *host,
295 unsigned int count, unsigned int ticks)
296 {
297 struct sata_fsl_host_priv *host_priv = host->private_data;
298 void __iomem *hcr_base = host_priv->hcr_base;
299 unsigned long flags;
300
301 if (count > ICC_MAX_INT_COUNT_THRESHOLD)
302 count = ICC_MAX_INT_COUNT_THRESHOLD;
303 else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
304 count = ICC_MIN_INT_COUNT_THRESHOLD;
305
306 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
307 ticks = ICC_MAX_INT_TICKS_THRESHOLD;
308 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
309 (count > ICC_MIN_INT_COUNT_THRESHOLD))
310 ticks = ICC_SAFE_INT_TICKS;
311
312 spin_lock_irqsave(&host->lock, flags);
313 iowrite32((count << 24 | ticks), hcr_base + ICC);
314
315 intr_coalescing_count = count;
316 intr_coalescing_ticks = ticks;
317 spin_unlock_irqrestore(&host->lock, flags);
318
319 DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
320 intr_coalescing_count, intr_coalescing_ticks);
321 DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
322 hcr_base, ioread32(hcr_base + ICC));
323 }
324
fsl_sata_intr_coalescing_show(struct device * dev,struct device_attribute * attr,char * buf)325 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
326 struct device_attribute *attr, char *buf)
327 {
328 return sprintf(buf, "%d %d\n",
329 intr_coalescing_count, intr_coalescing_ticks);
330 }
331
fsl_sata_intr_coalescing_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)332 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
333 struct device_attribute *attr,
334 const char *buf, size_t count)
335 {
336 unsigned int coalescing_count, coalescing_ticks;
337
338 if (sscanf(buf, "%d%d",
339 &coalescing_count,
340 &coalescing_ticks) != 2) {
341 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
342 return -EINVAL;
343 }
344
345 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
346 coalescing_count, coalescing_ticks);
347
348 return strlen(buf);
349 }
350
fsl_sata_rx_watermark_show(struct device * dev,struct device_attribute * attr,char * buf)351 static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
352 struct device_attribute *attr, char *buf)
353 {
354 unsigned int rx_watermark;
355 unsigned long flags;
356 struct ata_host *host = dev_get_drvdata(dev);
357 struct sata_fsl_host_priv *host_priv = host->private_data;
358 void __iomem *csr_base = host_priv->csr_base;
359
360 spin_lock_irqsave(&host->lock, flags);
361 rx_watermark = ioread32(csr_base + TRANSCFG);
362 rx_watermark &= 0x1f;
363
364 spin_unlock_irqrestore(&host->lock, flags);
365 return sprintf(buf, "%d\n", rx_watermark);
366 }
367
fsl_sata_rx_watermark_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)368 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
369 struct device_attribute *attr,
370 const char *buf, size_t count)
371 {
372 unsigned int rx_watermark;
373 unsigned long flags;
374 struct ata_host *host = dev_get_drvdata(dev);
375 struct sata_fsl_host_priv *host_priv = host->private_data;
376 void __iomem *csr_base = host_priv->csr_base;
377 u32 temp;
378
379 if (sscanf(buf, "%d", &rx_watermark) != 1) {
380 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
381 return -EINVAL;
382 }
383
384 spin_lock_irqsave(&host->lock, flags);
385 temp = ioread32(csr_base + TRANSCFG);
386 temp &= 0xffffffe0;
387 iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
388
389 spin_unlock_irqrestore(&host->lock, flags);
390 return strlen(buf);
391 }
392
sata_fsl_tag(unsigned int tag,void __iomem * hcr_base)393 static inline unsigned int sata_fsl_tag(unsigned int tag,
394 void __iomem *hcr_base)
395 {
396 /* We let libATA core do actual (queue) tag allocation */
397
398 /* all non NCQ/queued commands should have tag#0 */
399 if (ata_tag_internal(tag)) {
400 DPRINTK("mapping internal cmds to tag#0\n");
401 return 0;
402 }
403
404 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
405 DPRINTK("tag %d invalid : out of range\n", tag);
406 return 0;
407 }
408
409 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
410 DPRINTK("tag %d invalid : in use!!\n", tag);
411 return 0;
412 }
413
414 return tag;
415 }
416
sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv * pp,unsigned int tag,u32 desc_info,u32 data_xfer_len,u8 num_prde,u8 fis_len)417 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
418 unsigned int tag, u32 desc_info,
419 u32 data_xfer_len, u8 num_prde,
420 u8 fis_len)
421 {
422 dma_addr_t cmd_descriptor_address;
423
424 cmd_descriptor_address = pp->cmdentry_paddr +
425 tag * SATA_FSL_CMD_DESC_SIZE;
426
427 /* NOTE: both data_xfer_len & fis_len are Dword counts */
428
429 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
430 pp->cmdslot[tag].prde_fis_len =
431 cpu_to_le32((num_prde << 16) | (fis_len << 2));
432 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
433 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
434
435 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
436 pp->cmdslot[tag].cda,
437 pp->cmdslot[tag].prde_fis_len,
438 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
439
440 }
441
sata_fsl_fill_sg(struct ata_queued_cmd * qc,void * cmd_desc,u32 * ttl,dma_addr_t cmd_desc_paddr,int data_snoop)442 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
443 u32 *ttl, dma_addr_t cmd_desc_paddr,
444 int data_snoop)
445 {
446 struct scatterlist *sg;
447 unsigned int num_prde = 0;
448 u32 ttl_dwords = 0;
449
450 /*
451 * NOTE : direct & indirect prdt's are contiguously allocated
452 */
453 struct prde *prd = (struct prde *)&((struct command_desc *)
454 cmd_desc)->prdt;
455
456 struct prde *prd_ptr_to_indirect_ext = NULL;
457 unsigned indirect_ext_segment_sz = 0;
458 dma_addr_t indirect_ext_segment_paddr;
459 unsigned int si;
460
461 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
462
463 indirect_ext_segment_paddr = cmd_desc_paddr +
464 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
465
466 for_each_sg(qc->sg, sg, qc->n_elem, si) {
467 dma_addr_t sg_addr = sg_dma_address(sg);
468 u32 sg_len = sg_dma_len(sg);
469
470 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
471 (unsigned long long)sg_addr, sg_len);
472
473 /* warn if each s/g element is not dword aligned */
474 if (unlikely(sg_addr & 0x03))
475 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
476 (unsigned long long)sg_addr);
477 if (unlikely(sg_len & 0x03))
478 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
479 sg_len);
480
481 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
482 sg_next(sg) != NULL) {
483 VPRINTK("setting indirect prde\n");
484 prd_ptr_to_indirect_ext = prd;
485 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
486 indirect_ext_segment_sz = 0;
487 ++prd;
488 ++num_prde;
489 }
490
491 ttl_dwords += sg_len;
492 prd->dba = cpu_to_le32(sg_addr);
493 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
494
495 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
496 ttl_dwords, prd->dba, prd->ddc_and_ext);
497
498 ++num_prde;
499 ++prd;
500 if (prd_ptr_to_indirect_ext)
501 indirect_ext_segment_sz += sg_len;
502 }
503
504 if (prd_ptr_to_indirect_ext) {
505 /* set indirect extension flag along with indirect ext. size */
506 prd_ptr_to_indirect_ext->ddc_and_ext =
507 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
508 data_snoop |
509 (indirect_ext_segment_sz & ~0x03)));
510 }
511
512 *ttl = ttl_dwords;
513 return num_prde;
514 }
515
sata_fsl_qc_prep(struct ata_queued_cmd * qc)516 static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
517 {
518 struct ata_port *ap = qc->ap;
519 struct sata_fsl_port_priv *pp = ap->private_data;
520 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
521 void __iomem *hcr_base = host_priv->hcr_base;
522 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
523 struct command_desc *cd;
524 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
525 u32 num_prde = 0;
526 u32 ttl_dwords = 0;
527 dma_addr_t cd_paddr;
528
529 cd = (struct command_desc *)pp->cmdentry + tag;
530 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
531
532 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
533
534 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
535 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
536
537 if (qc->tf.protocol == ATA_PROT_NCQ) {
538 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
539 cd->cfis[3], cd->cfis[11]);
540 }
541
542 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
543 if (ata_is_atapi(qc->tf.protocol)) {
544 desc_info |= ATAPI_CMD;
545 memset((void *)&cd->acmd, 0, 32);
546 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
547 }
548
549 if (qc->flags & ATA_QCFLAG_DMAMAP)
550 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
551 &ttl_dwords, cd_paddr,
552 host_priv->data_snoop);
553
554 if (qc->tf.protocol == ATA_PROT_NCQ)
555 desc_info |= FPDMA_QUEUED_CMD;
556
557 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
558 num_prde, 5);
559
560 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
561 desc_info, ttl_dwords, num_prde);
562
563 return AC_ERR_OK;
564 }
565
sata_fsl_qc_issue(struct ata_queued_cmd * qc)566 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
567 {
568 struct ata_port *ap = qc->ap;
569 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
570 void __iomem *hcr_base = host_priv->hcr_base;
571 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
572
573 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
574 ioread32(CQ + hcr_base),
575 ioread32(CA + hcr_base),
576 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
577
578 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
579
580 /* Simply queue command to the controller/device */
581 iowrite32(1 << tag, CQ + hcr_base);
582
583 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
584 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
585
586 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
587 ioread32(CE + hcr_base),
588 ioread32(DE + hcr_base),
589 ioread32(CC + hcr_base),
590 ioread32(COMMANDSTAT + host_priv->csr_base));
591
592 return 0;
593 }
594
sata_fsl_qc_fill_rtf(struct ata_queued_cmd * qc)595 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
596 {
597 struct sata_fsl_port_priv *pp = qc->ap->private_data;
598 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
599 void __iomem *hcr_base = host_priv->hcr_base;
600 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
601 struct command_desc *cd;
602
603 cd = pp->cmdentry + tag;
604
605 ata_tf_from_fis(cd->sfis, &qc->result_tf);
606 return true;
607 }
608
sata_fsl_scr_write(struct ata_link * link,unsigned int sc_reg_in,u32 val)609 static int sata_fsl_scr_write(struct ata_link *link,
610 unsigned int sc_reg_in, u32 val)
611 {
612 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
613 void __iomem *ssr_base = host_priv->ssr_base;
614 unsigned int sc_reg;
615
616 switch (sc_reg_in) {
617 case SCR_STATUS:
618 case SCR_ERROR:
619 case SCR_CONTROL:
620 case SCR_ACTIVE:
621 sc_reg = sc_reg_in;
622 break;
623 default:
624 return -EINVAL;
625 }
626
627 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
628
629 iowrite32(val, ssr_base + (sc_reg * 4));
630 return 0;
631 }
632
sata_fsl_scr_read(struct ata_link * link,unsigned int sc_reg_in,u32 * val)633 static int sata_fsl_scr_read(struct ata_link *link,
634 unsigned int sc_reg_in, u32 *val)
635 {
636 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
637 void __iomem *ssr_base = host_priv->ssr_base;
638 unsigned int sc_reg;
639
640 switch (sc_reg_in) {
641 case SCR_STATUS:
642 case SCR_ERROR:
643 case SCR_CONTROL:
644 case SCR_ACTIVE:
645 sc_reg = sc_reg_in;
646 break;
647 default:
648 return -EINVAL;
649 }
650
651 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
652
653 *val = ioread32(ssr_base + (sc_reg * 4));
654 return 0;
655 }
656
sata_fsl_freeze(struct ata_port * ap)657 static void sata_fsl_freeze(struct ata_port *ap)
658 {
659 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
660 void __iomem *hcr_base = host_priv->hcr_base;
661 u32 temp;
662
663 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
664 ioread32(CQ + hcr_base),
665 ioread32(CA + hcr_base),
666 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
667 VPRINTK("CmdStat = 0x%x\n",
668 ioread32(host_priv->csr_base + COMMANDSTAT));
669
670 /* disable interrupts on the controller/port */
671 temp = ioread32(hcr_base + HCONTROL);
672 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
673
674 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
675 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
676 }
677
sata_fsl_thaw(struct ata_port * ap)678 static void sata_fsl_thaw(struct ata_port *ap)
679 {
680 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
681 void __iomem *hcr_base = host_priv->hcr_base;
682 u32 temp;
683
684 /* ack. any pending IRQs for this controller/port */
685 temp = ioread32(hcr_base + HSTATUS);
686
687 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
688
689 if (temp & 0x3F)
690 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
691
692 /* enable interrupts on the controller/port */
693 temp = ioread32(hcr_base + HCONTROL);
694 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
695
696 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
697 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
698 }
699
sata_fsl_pmp_attach(struct ata_port * ap)700 static void sata_fsl_pmp_attach(struct ata_port *ap)
701 {
702 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
703 void __iomem *hcr_base = host_priv->hcr_base;
704 u32 temp;
705
706 temp = ioread32(hcr_base + HCONTROL);
707 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
708 }
709
sata_fsl_pmp_detach(struct ata_port * ap)710 static void sata_fsl_pmp_detach(struct ata_port *ap)
711 {
712 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
713 void __iomem *hcr_base = host_priv->hcr_base;
714 u32 temp;
715
716 temp = ioread32(hcr_base + HCONTROL);
717 temp &= ~HCONTROL_PMP_ATTACHED;
718 iowrite32(temp, hcr_base + HCONTROL);
719
720 /* enable interrupts on the controller/port */
721 temp = ioread32(hcr_base + HCONTROL);
722 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
723
724 }
725
sata_fsl_port_start(struct ata_port * ap)726 static int sata_fsl_port_start(struct ata_port *ap)
727 {
728 struct device *dev = ap->host->dev;
729 struct sata_fsl_port_priv *pp;
730 void *mem;
731 dma_addr_t mem_dma;
732 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
733 void __iomem *hcr_base = host_priv->hcr_base;
734 u32 temp;
735
736 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
737 if (!pp)
738 return -ENOMEM;
739
740 mem = dma_zalloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
741 GFP_KERNEL);
742 if (!mem) {
743 kfree(pp);
744 return -ENOMEM;
745 }
746
747 pp->cmdslot = mem;
748 pp->cmdslot_paddr = mem_dma;
749
750 mem += SATA_FSL_CMD_SLOT_SIZE;
751 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
752
753 pp->cmdentry = mem;
754 pp->cmdentry_paddr = mem_dma;
755
756 ap->private_data = pp;
757
758 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
759 pp->cmdslot_paddr, pp->cmdentry_paddr);
760
761 /* Now, update the CHBA register in host controller cmd register set */
762 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
763
764 /*
765 * Now, we can bring the controller on-line & also initiate
766 * the COMINIT sequence, we simply return here and the boot-probing
767 * & device discovery process is re-initiated by libATA using a
768 * Softreset EH (dummy) session. Hence, boot probing and device
769 * discovey will be part of sata_fsl_softreset() callback.
770 */
771
772 temp = ioread32(hcr_base + HCONTROL);
773 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
774
775 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
776 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
777 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
778
779 return 0;
780 }
781
sata_fsl_port_stop(struct ata_port * ap)782 static void sata_fsl_port_stop(struct ata_port *ap)
783 {
784 struct device *dev = ap->host->dev;
785 struct sata_fsl_port_priv *pp = ap->private_data;
786 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
787 void __iomem *hcr_base = host_priv->hcr_base;
788 u32 temp;
789
790 /*
791 * Force host controller to go off-line, aborting current operations
792 */
793 temp = ioread32(hcr_base + HCONTROL);
794 temp &= ~HCONTROL_ONLINE_PHY_RST;
795 temp |= HCONTROL_FORCE_OFFLINE;
796 iowrite32(temp, hcr_base + HCONTROL);
797
798 /* Poll for controller to go offline - should happen immediately */
799 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
800
801 ap->private_data = NULL;
802 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
803 pp->cmdslot, pp->cmdslot_paddr);
804
805 kfree(pp);
806 }
807
sata_fsl_dev_classify(struct ata_port * ap)808 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
809 {
810 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
811 void __iomem *hcr_base = host_priv->hcr_base;
812 struct ata_taskfile tf;
813 u32 temp;
814
815 temp = ioread32(hcr_base + SIGNATURE);
816
817 VPRINTK("raw sig = 0x%x\n", temp);
818 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
819 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
820
821 tf.lbah = (temp >> 24) & 0xff;
822 tf.lbam = (temp >> 16) & 0xff;
823 tf.lbal = (temp >> 8) & 0xff;
824 tf.nsect = temp & 0xff;
825
826 return ata_dev_classify(&tf);
827 }
828
sata_fsl_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)829 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
830 unsigned long deadline)
831 {
832 struct ata_port *ap = link->ap;
833 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
834 void __iomem *hcr_base = host_priv->hcr_base;
835 u32 temp;
836 int i = 0;
837 unsigned long start_jiffies;
838
839 DPRINTK("in xx_hardreset\n");
840
841 try_offline_again:
842 /*
843 * Force host controller to go off-line, aborting current operations
844 */
845 temp = ioread32(hcr_base + HCONTROL);
846 temp &= ~HCONTROL_ONLINE_PHY_RST;
847 iowrite32(temp, hcr_base + HCONTROL);
848
849 /* Poll for controller to go offline */
850 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
851 1, 500);
852
853 if (temp & ONLINE) {
854 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
855
856 /*
857 * Try to offline controller atleast twice
858 */
859 i++;
860 if (i == 2)
861 goto err;
862 else
863 goto try_offline_again;
864 }
865
866 DPRINTK("hardreset, controller off-lined\n");
867 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
868 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
869
870 /*
871 * PHY reset should remain asserted for atleast 1ms
872 */
873 ata_msleep(ap, 1);
874
875 sata_set_spd(link);
876
877 /*
878 * Now, bring the host controller online again, this can take time
879 * as PHY reset and communication establishment, 1st D2H FIS and
880 * device signature update is done, on safe side assume 500ms
881 * NOTE : Host online status may be indicated immediately!!
882 */
883
884 temp = ioread32(hcr_base + HCONTROL);
885 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
886 temp |= HCONTROL_PMP_ATTACHED;
887 iowrite32(temp, hcr_base + HCONTROL);
888
889 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
890
891 if (!(temp & ONLINE)) {
892 ata_port_err(ap, "Hardreset failed, not on-lined\n");
893 goto err;
894 }
895
896 DPRINTK("hardreset, controller off-lined & on-lined\n");
897 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
898 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
899
900 /*
901 * First, wait for the PHYRDY change to occur before waiting for
902 * the signature, and also verify if SStatus indicates device
903 * presence
904 */
905
906 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
907 if ((!(temp & 0x10)) || ata_link_offline(link)) {
908 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
909 ioread32(hcr_base + HSTATUS));
910 *class = ATA_DEV_NONE;
911 return 0;
912 }
913
914 /*
915 * Wait for the first D2H from device,i.e,signature update notification
916 */
917 start_jiffies = jiffies;
918 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
919 500, jiffies_to_msecs(deadline - start_jiffies));
920
921 if ((temp & 0xFF) != 0x18) {
922 ata_port_warn(ap, "No Signature Update\n");
923 *class = ATA_DEV_NONE;
924 goto do_followup_srst;
925 } else {
926 ata_port_info(ap, "Signature Update detected @ %d msecs\n",
927 jiffies_to_msecs(jiffies - start_jiffies));
928 *class = sata_fsl_dev_classify(ap);
929 return 0;
930 }
931
932 do_followup_srst:
933 /*
934 * request libATA to perform follow-up softreset
935 */
936 return -EAGAIN;
937
938 err:
939 return -EIO;
940 }
941
sata_fsl_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)942 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
943 unsigned long deadline)
944 {
945 struct ata_port *ap = link->ap;
946 struct sata_fsl_port_priv *pp = ap->private_data;
947 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
948 void __iomem *hcr_base = host_priv->hcr_base;
949 int pmp = sata_srst_pmp(link);
950 u32 temp;
951 struct ata_taskfile tf;
952 u8 *cfis;
953 u32 Serror;
954
955 DPRINTK("in xx_softreset\n");
956
957 if (ata_link_offline(link)) {
958 DPRINTK("PHY reports no device\n");
959 *class = ATA_DEV_NONE;
960 return 0;
961 }
962
963 /*
964 * Send a device reset (SRST) explicitly on command slot #0
965 * Check : will the command queue (reg) be cleared during offlining ??
966 * Also we will be online only if Phy commn. has been established
967 * and device presence has been detected, therefore if we have
968 * reached here, we can send a command to the target device
969 */
970
971 DPRINTK("Sending SRST/device reset\n");
972
973 ata_tf_init(link->device, &tf);
974 cfis = (u8 *) &pp->cmdentry->cfis;
975
976 /* device reset/SRST is a control register update FIS, uses tag0 */
977 sata_fsl_setup_cmd_hdr_entry(pp, 0,
978 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
979
980 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
981 ata_tf_to_fis(&tf, pmp, 0, cfis);
982
983 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
984 cfis[0], cfis[1], cfis[2], cfis[3]);
985
986 /*
987 * Queue SRST command to the controller/device, ensure that no
988 * other commands are active on the controller/device
989 */
990
991 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
992 ioread32(CQ + hcr_base),
993 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
994
995 iowrite32(0xFFFF, CC + hcr_base);
996 if (pmp != SATA_PMP_CTRL_PORT)
997 iowrite32(pmp, CQPMP + hcr_base);
998 iowrite32(1, CQ + hcr_base);
999
1000 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
1001 if (temp & 0x1) {
1002 ata_port_warn(ap, "ATA_SRST issue failed\n");
1003
1004 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
1005 ioread32(CQ + hcr_base),
1006 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1007
1008 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
1009
1010 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1011 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1012 DPRINTK("Serror = 0x%x\n", Serror);
1013 goto err;
1014 }
1015
1016 ata_msleep(ap, 1);
1017
1018 /*
1019 * SATA device enters reset state after receiving a Control register
1020 * FIS with SRST bit asserted and it awaits another H2D Control reg.
1021 * FIS with SRST bit cleared, then the device does internal diags &
1022 * initialization, followed by indicating it's initialization status
1023 * using ATA signature D2H register FIS to the host controller.
1024 */
1025
1026 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1027 0, 0, 5);
1028
1029 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
1030 ata_tf_to_fis(&tf, pmp, 0, cfis);
1031
1032 if (pmp != SATA_PMP_CTRL_PORT)
1033 iowrite32(pmp, CQPMP + hcr_base);
1034 iowrite32(1, CQ + hcr_base);
1035 ata_msleep(ap, 150); /* ?? */
1036
1037 /*
1038 * The above command would have signalled an interrupt on command
1039 * complete, which needs special handling, by clearing the Nth
1040 * command bit of the CCreg
1041 */
1042 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1043
1044 DPRINTK("SATA FSL : Now checking device signature\n");
1045
1046 *class = ATA_DEV_NONE;
1047
1048 /* Verify if SStatus indicates device presence */
1049 if (ata_link_online(link)) {
1050 /*
1051 * if we are here, device presence has been detected,
1052 * 1st D2H FIS would have been received, but sfis in
1053 * command desc. is not updated, but signature register
1054 * would have been updated
1055 */
1056
1057 *class = sata_fsl_dev_classify(ap);
1058
1059 DPRINTK("class = %d\n", *class);
1060 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1061 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1062 }
1063
1064 return 0;
1065
1066 err:
1067 return -EIO;
1068 }
1069
sata_fsl_error_handler(struct ata_port * ap)1070 static void sata_fsl_error_handler(struct ata_port *ap)
1071 {
1072
1073 DPRINTK("in xx_error_handler\n");
1074 sata_pmp_error_handler(ap);
1075
1076 }
1077
sata_fsl_post_internal_cmd(struct ata_queued_cmd * qc)1078 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1079 {
1080 if (qc->flags & ATA_QCFLAG_FAILED)
1081 qc->err_mask |= AC_ERR_OTHER;
1082
1083 if (qc->err_mask) {
1084 /* make DMA engine forget about the failed command */
1085
1086 }
1087 }
1088
sata_fsl_error_intr(struct ata_port * ap)1089 static void sata_fsl_error_intr(struct ata_port *ap)
1090 {
1091 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1092 void __iomem *hcr_base = host_priv->hcr_base;
1093 u32 hstatus, dereg=0, cereg = 0, SError = 0;
1094 unsigned int err_mask = 0, action = 0;
1095 int freeze = 0, abort=0;
1096 struct ata_link *link = NULL;
1097 struct ata_queued_cmd *qc = NULL;
1098 struct ata_eh_info *ehi;
1099
1100 hstatus = ioread32(hcr_base + HSTATUS);
1101 cereg = ioread32(hcr_base + CE);
1102
1103 /* first, analyze and record host port events */
1104 link = &ap->link;
1105 ehi = &link->eh_info;
1106 ata_ehi_clear_desc(ehi);
1107
1108 /*
1109 * Handle & Clear SError
1110 */
1111
1112 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1113 if (unlikely(SError & 0xFFFF0000))
1114 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1115
1116 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1117 hstatus, cereg, ioread32(hcr_base + DE), SError);
1118
1119 /* handle fatal errors */
1120 if (hstatus & FATAL_ERROR_DECODE) {
1121 ehi->err_mask |= AC_ERR_ATA_BUS;
1122 ehi->action |= ATA_EH_SOFTRESET;
1123
1124 freeze = 1;
1125 }
1126
1127 /* Handle SDB FIS receive & notify update */
1128 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1129 sata_async_notification(ap);
1130
1131 /* Handle PHYRDY change notification */
1132 if (hstatus & INT_ON_PHYRDY_CHG) {
1133 DPRINTK("SATA FSL: PHYRDY change indication\n");
1134
1135 /* Setup a soft-reset EH action */
1136 ata_ehi_hotplugged(ehi);
1137 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1138 freeze = 1;
1139 }
1140
1141 /* handle single device errors */
1142 if (cereg) {
1143 /*
1144 * clear the command error, also clears queue to the device
1145 * in error, and we can (re)issue commands to this device.
1146 * When a device is in error all commands queued into the
1147 * host controller and at the device are considered aborted
1148 * and the queue for that device is stopped. Now, after
1149 * clearing the device error, we can issue commands to the
1150 * device to interrogate it to find the source of the error.
1151 */
1152 abort = 1;
1153
1154 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1155 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1156
1157 /* find out the offending link and qc */
1158 if (ap->nr_pmp_links) {
1159 unsigned int dev_num;
1160
1161 dereg = ioread32(hcr_base + DE);
1162 iowrite32(dereg, hcr_base + DE);
1163 iowrite32(cereg, hcr_base + CE);
1164
1165 dev_num = ffs(dereg) - 1;
1166 if (dev_num < ap->nr_pmp_links && dereg != 0) {
1167 link = &ap->pmp_link[dev_num];
1168 ehi = &link->eh_info;
1169 qc = ata_qc_from_tag(ap, link->active_tag);
1170 /*
1171 * We should consider this as non fatal error,
1172 * and TF must be updated as done below.
1173 */
1174
1175 err_mask |= AC_ERR_DEV;
1176
1177 } else {
1178 err_mask |= AC_ERR_HSM;
1179 action |= ATA_EH_HARDRESET;
1180 freeze = 1;
1181 }
1182 } else {
1183 dereg = ioread32(hcr_base + DE);
1184 iowrite32(dereg, hcr_base + DE);
1185 iowrite32(cereg, hcr_base + CE);
1186
1187 qc = ata_qc_from_tag(ap, link->active_tag);
1188 /*
1189 * We should consider this as non fatal error,
1190 * and TF must be updated as done below.
1191 */
1192 err_mask |= AC_ERR_DEV;
1193 }
1194 }
1195
1196 /* record error info */
1197 if (qc)
1198 qc->err_mask |= err_mask;
1199 else
1200 ehi->err_mask |= err_mask;
1201
1202 ehi->action |= action;
1203
1204 /* freeze or abort */
1205 if (freeze)
1206 ata_port_freeze(ap);
1207 else if (abort) {
1208 if (qc)
1209 ata_link_abort(qc->dev->link);
1210 else
1211 ata_port_abort(ap);
1212 }
1213 }
1214
sata_fsl_host_intr(struct ata_port * ap)1215 static void sata_fsl_host_intr(struct ata_port *ap)
1216 {
1217 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1218 void __iomem *hcr_base = host_priv->hcr_base;
1219 u32 hstatus, done_mask = 0;
1220 struct ata_queued_cmd *qc;
1221 u32 SError;
1222 u32 tag;
1223 u32 status_mask = INT_ON_ERROR;
1224
1225 hstatus = ioread32(hcr_base + HSTATUS);
1226
1227 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1228
1229 /* Read command completed register */
1230 done_mask = ioread32(hcr_base + CC);
1231
1232 /* Workaround for data length mismatch errata */
1233 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1234 for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
1235 qc = ata_qc_from_tag(ap, tag);
1236 if (qc && ata_is_atapi(qc->tf.protocol)) {
1237 u32 hcontrol;
1238 /* Set HControl[27] to clear error registers */
1239 hcontrol = ioread32(hcr_base + HCONTROL);
1240 iowrite32(hcontrol | CLEAR_ERROR,
1241 hcr_base + HCONTROL);
1242
1243 /* Clear HControl[27] */
1244 iowrite32(hcontrol & ~CLEAR_ERROR,
1245 hcr_base + HCONTROL);
1246
1247 /* Clear SError[E] bit */
1248 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1249 SError);
1250
1251 /* Ignore fatal error and device error */
1252 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1253 | INT_ON_FATAL_ERR);
1254 break;
1255 }
1256 }
1257 }
1258
1259 if (unlikely(SError & 0xFFFF0000)) {
1260 DPRINTK("serror @host_intr : 0x%x\n", SError);
1261 sata_fsl_error_intr(ap);
1262 }
1263
1264 if (unlikely(hstatus & status_mask)) {
1265 DPRINTK("error interrupt!!\n");
1266 sata_fsl_error_intr(ap);
1267 return;
1268 }
1269
1270 VPRINTK("Status of all queues :\n");
1271 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1272 done_mask,
1273 ioread32(hcr_base + CA),
1274 ioread32(hcr_base + CE),
1275 ioread32(hcr_base + CQ),
1276 ap->qc_active);
1277
1278 if (done_mask & ap->qc_active) {
1279 int i;
1280 /* clear CC bit, this will also complete the interrupt */
1281 iowrite32(done_mask, hcr_base + CC);
1282
1283 DPRINTK("Status of all queues :\n");
1284 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1285 done_mask, ioread32(hcr_base + CA),
1286 ioread32(hcr_base + CE));
1287
1288 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1289 if (done_mask & (1 << i))
1290 DPRINTK
1291 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1292 i, ioread32(hcr_base + CC),
1293 ioread32(hcr_base + CA));
1294 }
1295 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
1296 return;
1297
1298 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1299 iowrite32(1, hcr_base + CC);
1300 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1301
1302 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1303 ioread32(hcr_base + CC));
1304
1305 if (qc) {
1306 ata_qc_complete(qc);
1307 }
1308 } else {
1309 /* Spurious Interrupt!! */
1310 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1311 ioread32(hcr_base + CC));
1312 iowrite32(done_mask, hcr_base + CC);
1313 return;
1314 }
1315 }
1316
sata_fsl_interrupt(int irq,void * dev_instance)1317 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1318 {
1319 struct ata_host *host = dev_instance;
1320 struct sata_fsl_host_priv *host_priv = host->private_data;
1321 void __iomem *hcr_base = host_priv->hcr_base;
1322 u32 interrupt_enables;
1323 unsigned handled = 0;
1324 struct ata_port *ap;
1325
1326 /* ack. any pending IRQs for this controller/port */
1327 interrupt_enables = ioread32(hcr_base + HSTATUS);
1328 interrupt_enables &= 0x3F;
1329
1330 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1331
1332 if (!interrupt_enables)
1333 return IRQ_NONE;
1334
1335 spin_lock(&host->lock);
1336
1337 /* Assuming one port per host controller */
1338
1339 ap = host->ports[0];
1340 if (ap) {
1341 sata_fsl_host_intr(ap);
1342 } else {
1343 dev_warn(host->dev, "interrupt on disabled port 0\n");
1344 }
1345
1346 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1347 handled = 1;
1348
1349 spin_unlock(&host->lock);
1350
1351 return IRQ_RETVAL(handled);
1352 }
1353
1354 /*
1355 * Multiple ports are represented by multiple SATA controllers with
1356 * one port per controller
1357 */
sata_fsl_init_controller(struct ata_host * host)1358 static int sata_fsl_init_controller(struct ata_host *host)
1359 {
1360 struct sata_fsl_host_priv *host_priv = host->private_data;
1361 void __iomem *hcr_base = host_priv->hcr_base;
1362 u32 temp;
1363
1364 /*
1365 * NOTE : We cannot bring the controller online before setting
1366 * the CHBA, hence main controller initialization is done as
1367 * part of the port_start() callback
1368 */
1369
1370 /* sata controller to operate in enterprise mode */
1371 temp = ioread32(hcr_base + HCONTROL);
1372 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1373
1374 /* ack. any pending IRQs for this controller/port */
1375 temp = ioread32(hcr_base + HSTATUS);
1376 if (temp & 0x3F)
1377 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1378
1379 /* Keep interrupts disabled on the controller */
1380 temp = ioread32(hcr_base + HCONTROL);
1381 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1382
1383 /* Disable interrupt coalescing control(icc), for the moment */
1384 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1385 iowrite32(0x01000000, hcr_base + ICC);
1386
1387 /* clear error registers, SError is cleared by libATA */
1388 iowrite32(0x00000FFFF, hcr_base + CE);
1389 iowrite32(0x00000FFFF, hcr_base + DE);
1390
1391 /*
1392 * reset the number of command complete bits which will cause the
1393 * interrupt to be signaled
1394 */
1395 fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1396 intr_coalescing_ticks);
1397
1398 /*
1399 * host controller will be brought on-line, during xx_port_start()
1400 * callback, that should also initiate the OOB, COMINIT sequence
1401 */
1402
1403 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1404 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1405
1406 return 0;
1407 }
1408
sata_fsl_host_stop(struct ata_host * host)1409 static void sata_fsl_host_stop(struct ata_host *host)
1410 {
1411 struct sata_fsl_host_priv *host_priv = host->private_data;
1412
1413 iounmap(host_priv->hcr_base);
1414 kfree(host_priv);
1415 }
1416
1417 /*
1418 * scsi mid-layer and libata interface structures
1419 */
1420 static struct scsi_host_template sata_fsl_sht = {
1421 ATA_NCQ_SHT("sata_fsl"),
1422 .can_queue = SATA_FSL_QUEUE_DEPTH,
1423 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1424 .dma_boundary = ATA_DMA_BOUNDARY,
1425 };
1426
1427 static struct ata_port_operations sata_fsl_ops = {
1428 .inherits = &sata_pmp_port_ops,
1429
1430 .qc_defer = ata_std_qc_defer,
1431 .qc_prep = sata_fsl_qc_prep,
1432 .qc_issue = sata_fsl_qc_issue,
1433 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1434
1435 .scr_read = sata_fsl_scr_read,
1436 .scr_write = sata_fsl_scr_write,
1437
1438 .freeze = sata_fsl_freeze,
1439 .thaw = sata_fsl_thaw,
1440 .softreset = sata_fsl_softreset,
1441 .hardreset = sata_fsl_hardreset,
1442 .pmp_softreset = sata_fsl_softreset,
1443 .error_handler = sata_fsl_error_handler,
1444 .post_internal_cmd = sata_fsl_post_internal_cmd,
1445
1446 .port_start = sata_fsl_port_start,
1447 .port_stop = sata_fsl_port_stop,
1448
1449 .host_stop = sata_fsl_host_stop,
1450
1451 .pmp_attach = sata_fsl_pmp_attach,
1452 .pmp_detach = sata_fsl_pmp_detach,
1453 };
1454
1455 static const struct ata_port_info sata_fsl_port_info[] = {
1456 {
1457 .flags = SATA_FSL_HOST_FLAGS,
1458 .pio_mask = ATA_PIO4,
1459 .udma_mask = ATA_UDMA6,
1460 .port_ops = &sata_fsl_ops,
1461 },
1462 };
1463
sata_fsl_probe(struct platform_device * ofdev)1464 static int sata_fsl_probe(struct platform_device *ofdev)
1465 {
1466 int retval = -ENXIO;
1467 void __iomem *hcr_base = NULL;
1468 void __iomem *ssr_base = NULL;
1469 void __iomem *csr_base = NULL;
1470 struct sata_fsl_host_priv *host_priv = NULL;
1471 int irq;
1472 struct ata_host *host = NULL;
1473 u32 temp;
1474
1475 struct ata_port_info pi = sata_fsl_port_info[0];
1476 const struct ata_port_info *ppi[] = { &pi, NULL };
1477
1478 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1479
1480 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1481 if (!hcr_base)
1482 goto error_exit_with_cleanup;
1483
1484 ssr_base = hcr_base + 0x100;
1485 csr_base = hcr_base + 0x140;
1486
1487 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1488 temp = ioread32(csr_base + TRANSCFG);
1489 temp = temp & 0xffffffe0;
1490 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1491 }
1492
1493 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1494 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1495 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1496
1497 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1498 if (!host_priv)
1499 goto error_exit_with_cleanup;
1500
1501 host_priv->hcr_base = hcr_base;
1502 host_priv->ssr_base = ssr_base;
1503 host_priv->csr_base = csr_base;
1504
1505 irq = platform_get_irq(ofdev, 0);
1506 if (irq < 0) {
1507 retval = irq;
1508 goto error_exit_with_cleanup;
1509 }
1510 host_priv->irq = irq;
1511
1512 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1513 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1514 else
1515 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1516
1517 /* allocate host structure */
1518 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1519 if (!host) {
1520 retval = -ENOMEM;
1521 goto error_exit_with_cleanup;
1522 }
1523
1524 /* host->iomap is not used currently */
1525 host->private_data = host_priv;
1526
1527 /* initialize host controller */
1528 sata_fsl_init_controller(host);
1529
1530 /*
1531 * Now, register with libATA core, this will also initiate the
1532 * device discovery process, invoking our port_start() handler &
1533 * error_handler() to execute a dummy Softreset EH session
1534 */
1535 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1536 &sata_fsl_sht);
1537
1538 platform_set_drvdata(ofdev, host);
1539
1540 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1541 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1542 sysfs_attr_init(&host_priv->intr_coalescing.attr);
1543 host_priv->intr_coalescing.attr.name = "intr_coalescing";
1544 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1545 retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1546 if (retval)
1547 goto error_exit_with_cleanup;
1548
1549 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1550 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1551 sysfs_attr_init(&host_priv->rx_watermark.attr);
1552 host_priv->rx_watermark.attr.name = "rx_watermark";
1553 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1554 retval = device_create_file(host->dev, &host_priv->rx_watermark);
1555 if (retval) {
1556 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1557 goto error_exit_with_cleanup;
1558 }
1559
1560 return 0;
1561
1562 error_exit_with_cleanup:
1563
1564 if (host)
1565 ata_host_detach(host);
1566
1567 if (hcr_base)
1568 iounmap(hcr_base);
1569 kfree(host_priv);
1570
1571 return retval;
1572 }
1573
sata_fsl_remove(struct platform_device * ofdev)1574 static int sata_fsl_remove(struct platform_device *ofdev)
1575 {
1576 struct ata_host *host = platform_get_drvdata(ofdev);
1577 struct sata_fsl_host_priv *host_priv = host->private_data;
1578
1579 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1580 device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1581
1582 ata_host_detach(host);
1583
1584 return 0;
1585 }
1586
1587 #ifdef CONFIG_PM_SLEEP
sata_fsl_suspend(struct platform_device * op,pm_message_t state)1588 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1589 {
1590 struct ata_host *host = platform_get_drvdata(op);
1591 return ata_host_suspend(host, state);
1592 }
1593
sata_fsl_resume(struct platform_device * op)1594 static int sata_fsl_resume(struct platform_device *op)
1595 {
1596 struct ata_host *host = platform_get_drvdata(op);
1597 struct sata_fsl_host_priv *host_priv = host->private_data;
1598 int ret;
1599 void __iomem *hcr_base = host_priv->hcr_base;
1600 struct ata_port *ap = host->ports[0];
1601 struct sata_fsl_port_priv *pp = ap->private_data;
1602
1603 ret = sata_fsl_init_controller(host);
1604 if (ret) {
1605 dev_err(&op->dev, "Error initializing hardware\n");
1606 return ret;
1607 }
1608
1609 /* Recovery the CHBA register in host controller cmd register set */
1610 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1611
1612 iowrite32((ioread32(hcr_base + HCONTROL)
1613 | HCONTROL_ONLINE_PHY_RST
1614 | HCONTROL_SNOOP_ENABLE
1615 | HCONTROL_PMP_ATTACHED),
1616 hcr_base + HCONTROL);
1617
1618 ata_host_resume(host);
1619 return 0;
1620 }
1621 #endif
1622
1623 static struct of_device_id fsl_sata_match[] = {
1624 {
1625 .compatible = "fsl,pq-sata",
1626 },
1627 {
1628 .compatible = "fsl,pq-sata-v2",
1629 },
1630 {},
1631 };
1632
1633 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1634
1635 static struct platform_driver fsl_sata_driver = {
1636 .driver = {
1637 .name = "fsl-sata",
1638 .of_match_table = fsl_sata_match,
1639 },
1640 .probe = sata_fsl_probe,
1641 .remove = sata_fsl_remove,
1642 #ifdef CONFIG_PM_SLEEP
1643 .suspend = sata_fsl_suspend,
1644 .resume = sata_fsl_resume,
1645 #endif
1646 };
1647
1648 module_platform_driver(fsl_sata_driver);
1649
1650 MODULE_LICENSE("GPL");
1651 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1652 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1653 MODULE_VERSION("1.10");
1654