1 /*
2 * Copyright (C) 2014 Intel Corporation
3 *
4 * Authors:
5 * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
6 *
7 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
8 *
9 * This device driver implements the TPM interface as defined in
10 * the TCG CRB 2.0 TPM specification.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; version 2
15 * of the License.
16 */
17
18 #include <linux/acpi.h>
19 #include <linux/highmem.h>
20 #include <linux/rculist.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include "tpm.h"
24
25 #define ACPI_SIG_TPM2 "TPM2"
26
27 static const u8 CRB_ACPI_START_UUID[] = {
28 /* 0000 */ 0xAB, 0x6C, 0xBF, 0x6B, 0x63, 0x54, 0x14, 0x47,
29 /* 0008 */ 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4
30 };
31
32 enum crb_defaults {
33 CRB_ACPI_START_REVISION_ID = 1,
34 CRB_ACPI_START_INDEX = 1,
35 };
36
37 struct acpi_tpm2 {
38 struct acpi_table_header hdr;
39 u16 platform_class;
40 u16 reserved;
41 u64 control_area_pa;
42 u32 start_method;
43 } __packed;
44
45 enum crb_ca_request {
46 CRB_CA_REQ_GO_IDLE = BIT(0),
47 CRB_CA_REQ_CMD_READY = BIT(1),
48 };
49
50 enum crb_ca_status {
51 CRB_CA_STS_ERROR = BIT(0),
52 CRB_CA_STS_TPM_IDLE = BIT(1),
53 };
54
55 enum crb_start {
56 CRB_START_INVOKE = BIT(0),
57 };
58
59 enum crb_cancel {
60 CRB_CANCEL_INVOKE = BIT(0),
61 };
62
63 struct crb_control_area {
64 u32 req;
65 u32 sts;
66 u32 cancel;
67 u32 start;
68 u32 int_enable;
69 u32 int_sts;
70 u32 cmd_size;
71 u32 cmd_pa_low;
72 u32 cmd_pa_high;
73 u32 rsp_size;
74 u64 rsp_pa;
75 } __packed;
76
77 enum crb_status {
78 CRB_STS_COMPLETE = BIT(0),
79 };
80
81 enum crb_flags {
82 CRB_FL_ACPI_START = BIT(0),
83 CRB_FL_CRB_START = BIT(1),
84 };
85
86 struct crb_priv {
87 unsigned int flags;
88 struct crb_control_area __iomem *cca;
89 u8 __iomem *cmd;
90 u8 __iomem *rsp;
91 };
92
93 static SIMPLE_DEV_PM_OPS(crb_pm, tpm_pm_suspend, tpm_pm_resume);
94
crb_status(struct tpm_chip * chip)95 static u8 crb_status(struct tpm_chip *chip)
96 {
97 struct crb_priv *priv = chip->vendor.priv;
98 u8 sts = 0;
99
100 if ((le32_to_cpu(ioread32(&priv->cca->start)) & CRB_START_INVOKE) !=
101 CRB_START_INVOKE)
102 sts |= CRB_STS_COMPLETE;
103
104 return sts;
105 }
106
crb_recv(struct tpm_chip * chip,u8 * buf,size_t count)107 static int crb_recv(struct tpm_chip *chip, u8 *buf, size_t count)
108 {
109 struct crb_priv *priv = chip->vendor.priv;
110 unsigned int expected;
111
112 /* A sanity check that the upper layer wants to get at least the header
113 * as that is the minimum size for any TPM response.
114 */
115 if (count < TPM_HEADER_SIZE)
116 return -EIO;
117
118 /* If this bit is set, according to the spec, the TPM is in
119 * unrecoverable condition.
120 */
121 if (le32_to_cpu(ioread32(&priv->cca->sts)) & CRB_CA_STS_ERROR)
122 return -EIO;
123
124 /* Read the first 8 bytes in order to get the length of the response.
125 * We read exactly a quad word in order to make sure that the remaining
126 * reads will be aligned.
127 */
128 memcpy_fromio(buf, priv->rsp, 8);
129
130 expected = be32_to_cpup((__be32 *)&buf[2]);
131 if (expected > count || expected < TPM_HEADER_SIZE)
132 return -EIO;
133
134 memcpy_fromio(&buf[8], &priv->rsp[8], expected - 8);
135
136 return expected;
137 }
138
crb_do_acpi_start(struct tpm_chip * chip)139 static int crb_do_acpi_start(struct tpm_chip *chip)
140 {
141 union acpi_object *obj;
142 int rc;
143
144 obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
145 CRB_ACPI_START_UUID,
146 CRB_ACPI_START_REVISION_ID,
147 CRB_ACPI_START_INDEX,
148 NULL);
149 if (!obj)
150 return -ENXIO;
151 rc = obj->integer.value == 0 ? 0 : -ENXIO;
152 ACPI_FREE(obj);
153 return rc;
154 }
155
crb_send(struct tpm_chip * chip,u8 * buf,size_t len)156 static int crb_send(struct tpm_chip *chip, u8 *buf, size_t len)
157 {
158 struct crb_priv *priv = chip->vendor.priv;
159 int rc = 0;
160
161 /* Zero the cancel register so that the next command will not get
162 * canceled.
163 */
164 iowrite32(0, &priv->cca->cancel);
165
166 if (len > le32_to_cpu(ioread32(&priv->cca->cmd_size))) {
167 dev_err(&chip->dev,
168 "invalid command count value %x %zx\n",
169 (unsigned int) len,
170 (size_t) le32_to_cpu(ioread32(&priv->cca->cmd_size)));
171 return -E2BIG;
172 }
173
174 memcpy_toio(priv->cmd, buf, len);
175
176 /* Make sure that cmd is populated before issuing start. */
177 wmb();
178
179 if (priv->flags & CRB_FL_CRB_START)
180 iowrite32(cpu_to_le32(CRB_START_INVOKE), &priv->cca->start);
181
182 if (priv->flags & CRB_FL_ACPI_START)
183 rc = crb_do_acpi_start(chip);
184
185 return rc;
186 }
187
crb_cancel(struct tpm_chip * chip)188 static void crb_cancel(struct tpm_chip *chip)
189 {
190 struct crb_priv *priv = chip->vendor.priv;
191
192 iowrite32(cpu_to_le32(CRB_CANCEL_INVOKE), &priv->cca->cancel);
193
194 /* Make sure that cmd is populated before issuing cancel. */
195 wmb();
196
197 if ((priv->flags & CRB_FL_ACPI_START) && crb_do_acpi_start(chip))
198 dev_err(&chip->dev, "ACPI Start failed\n");
199 }
200
crb_req_canceled(struct tpm_chip * chip,u8 status)201 static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
202 {
203 struct crb_priv *priv = chip->vendor.priv;
204 u32 cancel = le32_to_cpu(ioread32(&priv->cca->cancel));
205
206 return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
207 }
208
209 static const struct tpm_class_ops tpm_crb = {
210 .status = crb_status,
211 .recv = crb_recv,
212 .send = crb_send,
213 .cancel = crb_cancel,
214 .req_canceled = crb_req_canceled,
215 .req_complete_mask = CRB_STS_COMPLETE,
216 .req_complete_val = CRB_STS_COMPLETE,
217 };
218
crb_acpi_add(struct acpi_device * device)219 static int crb_acpi_add(struct acpi_device *device)
220 {
221 struct tpm_chip *chip;
222 struct acpi_tpm2 *buf;
223 struct crb_priv *priv;
224 struct device *dev = &device->dev;
225 acpi_status status;
226 u32 sm;
227 u64 pa;
228 int rc;
229
230 status = acpi_get_table(ACPI_SIG_TPM2, 1,
231 (struct acpi_table_header **) &buf);
232 if (ACPI_FAILURE(status)) {
233 dev_err(dev, "failed to get TPM2 ACPI table\n");
234 return -ENODEV;
235 }
236
237 /* Should the FIFO driver handle this? */
238 if (buf->start_method == TPM2_START_FIFO)
239 return -ENODEV;
240
241 chip = tpmm_chip_alloc(dev, &tpm_crb);
242 if (IS_ERR(chip))
243 return PTR_ERR(chip);
244
245 chip->flags = TPM_CHIP_FLAG_TPM2;
246
247 if (buf->hdr.length < sizeof(struct acpi_tpm2)) {
248 dev_err(dev, "TPM2 ACPI table has wrong size");
249 return -EINVAL;
250 }
251
252 priv = (struct crb_priv *) devm_kzalloc(dev, sizeof(struct crb_priv),
253 GFP_KERNEL);
254 if (!priv) {
255 dev_err(dev, "failed to devm_kzalloc for private data\n");
256 return -ENOMEM;
257 }
258
259 sm = le32_to_cpu(buf->start_method);
260
261 /* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
262 * report only ACPI start but in practice seems to require both
263 * ACPI start and CRB start.
264 */
265 if (sm == TPM2_START_CRB || sm == TPM2_START_FIFO ||
266 !strcmp(acpi_device_hid(device), "MSFT0101"))
267 priv->flags |= CRB_FL_CRB_START;
268
269 if (sm == TPM2_START_ACPI || sm == TPM2_START_CRB_WITH_ACPI)
270 priv->flags |= CRB_FL_ACPI_START;
271
272 priv->cca = (struct crb_control_area __iomem *)
273 devm_ioremap_nocache(dev, buf->control_area_pa, 0x1000);
274 if (!priv->cca) {
275 dev_err(dev, "ioremap of the control area failed\n");
276 return -ENOMEM;
277 }
278
279 pa = ((u64) le32_to_cpu(ioread32(&priv->cca->cmd_pa_high)) << 32) |
280 (u64) le32_to_cpu(ioread32(&priv->cca->cmd_pa_low));
281 priv->cmd = devm_ioremap_nocache(dev, pa,
282 ioread32(&priv->cca->cmd_size));
283 if (!priv->cmd) {
284 dev_err(dev, "ioremap of the command buffer failed\n");
285 return -ENOMEM;
286 }
287
288 memcpy_fromio(&pa, &priv->cca->rsp_pa, 8);
289 pa = le64_to_cpu(pa);
290 priv->rsp = devm_ioremap_nocache(dev, pa,
291 ioread32(&priv->cca->rsp_size));
292 if (!priv->rsp) {
293 dev_err(dev, "ioremap of the response buffer failed\n");
294 return -ENOMEM;
295 }
296
297 chip->vendor.priv = priv;
298
299 /* Default timeouts and durations */
300 chip->vendor.timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
301 chip->vendor.timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
302 chip->vendor.timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
303 chip->vendor.timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
304 chip->vendor.duration[TPM_SHORT] =
305 msecs_to_jiffies(TPM2_DURATION_SHORT);
306 chip->vendor.duration[TPM_MEDIUM] =
307 msecs_to_jiffies(TPM2_DURATION_MEDIUM);
308 chip->vendor.duration[TPM_LONG] =
309 msecs_to_jiffies(TPM2_DURATION_LONG);
310
311 chip->acpi_dev_handle = device->handle;
312
313 rc = tpm2_do_selftest(chip);
314 if (rc)
315 return rc;
316
317 return tpm_chip_register(chip);
318 }
319
crb_acpi_remove(struct acpi_device * device)320 static int crb_acpi_remove(struct acpi_device *device)
321 {
322 struct device *dev = &device->dev;
323 struct tpm_chip *chip = dev_get_drvdata(dev);
324
325 if (chip->flags & TPM_CHIP_FLAG_TPM2)
326 tpm2_shutdown(chip, TPM2_SU_CLEAR);
327
328 tpm_chip_unregister(chip);
329
330 return 0;
331 }
332
333 static struct acpi_device_id crb_device_ids[] = {
334 {"MSFT0101", 0},
335 {"", 0},
336 };
337 MODULE_DEVICE_TABLE(acpi, crb_device_ids);
338
339 static struct acpi_driver crb_acpi_driver = {
340 .name = "tpm_crb",
341 .ids = crb_device_ids,
342 .ops = {
343 .add = crb_acpi_add,
344 .remove = crb_acpi_remove,
345 },
346 .drv = {
347 .pm = &crb_pm,
348 },
349 };
350
351 module_acpi_driver(crb_acpi_driver);
352 MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
353 MODULE_DESCRIPTION("TPM2 Driver");
354 MODULE_VERSION("0.1");
355 MODULE_LICENSE("GPL");
356