1 /*
2 * common clks module for all SiRF SoCs
3 *
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10 #include <linux/clk.h>
11
12 #define KHZ 1000
13 #define MHZ (KHZ * KHZ)
14
15 static void __iomem *sirfsoc_clk_vbase;
16 static void __iomem *sirfsoc_rsc_vbase;
17 static struct clk_onecell_data clk_data;
18
19 /*
20 * SiRFprimaII clock controller
21 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
22 * - 3 standard configurable plls: pll1, pll2 & pll3
23 * - 2 exclusive plls: usb phy pll and sata phy pll
24 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
25 * display and sdphy.
26 * Each clock domain can select its own clock source from five clock sources,
27 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
28 * clock of the group clock.
29 * - dsp domain: gps, mf
30 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
31 * - sys domain: security
32 */
33
34 struct clk_pll {
35 struct clk_hw hw;
36 unsigned short regofs; /* register offset */
37 };
38
39 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
40
41 struct clk_dmn {
42 struct clk_hw hw;
43 signed char enable_bit; /* enable bit: 0 ~ 63 */
44 unsigned short regofs; /* register offset */
45 };
46
47 #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
48
49 struct clk_std {
50 struct clk_hw hw;
51 signed char enable_bit; /* enable bit: 0 ~ 63 */
52 };
53
54 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
55
56 static int std_clk_is_enabled(struct clk_hw *hw);
57 static int std_clk_enable(struct clk_hw *hw);
58 static void std_clk_disable(struct clk_hw *hw);
59
clkc_readl(unsigned reg)60 static inline unsigned long clkc_readl(unsigned reg)
61 {
62 return readl(sirfsoc_clk_vbase + reg);
63 }
64
clkc_writel(u32 val,unsigned reg)65 static inline void clkc_writel(u32 val, unsigned reg)
66 {
67 writel(val, sirfsoc_clk_vbase + reg);
68 }
69
70 /*
71 * std pll
72 */
73
pll_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)74 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
75 unsigned long parent_rate)
76 {
77 unsigned long fin = parent_rate;
78 struct clk_pll *clk = to_pllclk(hw);
79 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
80 SIRFSOC_CLKC_PLL1_CFG0;
81
82 if (clkc_readl(regcfg2) & BIT(2)) {
83 /* pll bypass mode */
84 return fin;
85 } else {
86 /* fout = fin * nf / nr / od */
87 u32 cfg0 = clkc_readl(clk->regofs);
88 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
89 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
90 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
91 WARN_ON(fin % MHZ);
92 return fin / MHZ * nf / nr / od * MHZ;
93 }
94 }
95
pll_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)96 static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
97 unsigned long *parent_rate)
98 {
99 unsigned long fin, nf, nr, od;
100 u64 dividend;
101
102 /*
103 * fout = fin * nf / (nr * od);
104 * set od = 1, nr = fin/MHz, so fout = nf * MHz
105 */
106 rate = rate - rate % MHZ;
107
108 nf = rate / MHZ;
109 if (nf > BIT(13))
110 nf = BIT(13);
111 if (nf < 1)
112 nf = 1;
113
114 fin = *parent_rate;
115
116 nr = fin / MHZ;
117 if (nr > BIT(6))
118 nr = BIT(6);
119 od = 1;
120
121 dividend = (u64)fin * nf;
122 do_div(dividend, nr * od);
123
124 return (long)dividend;
125 }
126
pll_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)127 static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
128 unsigned long parent_rate)
129 {
130 struct clk_pll *clk = to_pllclk(hw);
131 unsigned long fin, nf, nr, od, reg;
132
133 /*
134 * fout = fin * nf / (nr * od);
135 * set od = 1, nr = fin/MHz, so fout = nf * MHz
136 */
137
138 nf = rate / MHZ;
139 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
140 return -EINVAL;
141
142 fin = parent_rate;
143 BUG_ON(fin < MHZ);
144
145 nr = fin / MHZ;
146 BUG_ON((fin % MHZ) || nr > BIT(6));
147
148 od = 1;
149
150 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
151 clkc_writel(reg, clk->regofs);
152
153 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
154 clkc_writel((nf >> 1) - 1, reg);
155
156 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
157 while (!(clkc_readl(reg) & BIT(6)))
158 cpu_relax();
159
160 return 0;
161 }
162
cpu_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)163 static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
164 unsigned long *parent_rate)
165 {
166 /*
167 * SiRF SoC has not cpu clock control,
168 * So bypass to it's parent pll.
169 */
170 struct clk_hw *parent_clk = clk_hw_get_parent(hw);
171 struct clk_hw *pll_parent_clk = clk_hw_get_parent(parent_clk);
172 unsigned long pll_parent_rate = clk_hw_get_rate(pll_parent_clk);
173 return pll_clk_round_rate(parent_clk, rate, &pll_parent_rate);
174 }
175
cpu_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)176 static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
177 unsigned long parent_rate)
178 {
179 /*
180 * SiRF SoC has not cpu clock control,
181 * So return the parent pll rate.
182 */
183 struct clk_hw *parent_clk = clk_hw_get_parent(hw);
184 return clk_hw_get_rate(parent_clk);
185 }
186
187 static struct clk_ops std_pll_ops = {
188 .recalc_rate = pll_clk_recalc_rate,
189 .round_rate = pll_clk_round_rate,
190 .set_rate = pll_clk_set_rate,
191 };
192
193 static const char * const pll_clk_parents[] = {
194 "osc",
195 };
196
197 static struct clk_init_data clk_pll1_init = {
198 .name = "pll1",
199 .ops = &std_pll_ops,
200 .parent_names = pll_clk_parents,
201 .num_parents = ARRAY_SIZE(pll_clk_parents),
202 };
203
204 static struct clk_init_data clk_pll2_init = {
205 .name = "pll2",
206 .ops = &std_pll_ops,
207 .parent_names = pll_clk_parents,
208 .num_parents = ARRAY_SIZE(pll_clk_parents),
209 };
210
211 static struct clk_init_data clk_pll3_init = {
212 .name = "pll3",
213 .ops = &std_pll_ops,
214 .parent_names = pll_clk_parents,
215 .num_parents = ARRAY_SIZE(pll_clk_parents),
216 };
217
218 static struct clk_pll clk_pll1 = {
219 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
220 .hw = {
221 .init = &clk_pll1_init,
222 },
223 };
224
225 static struct clk_pll clk_pll2 = {
226 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
227 .hw = {
228 .init = &clk_pll2_init,
229 },
230 };
231
232 static struct clk_pll clk_pll3 = {
233 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
234 .hw = {
235 .init = &clk_pll3_init,
236 },
237 };
238
239 /*
240 * usb uses specified pll
241 */
242
usb_pll_clk_enable(struct clk_hw * hw)243 static int usb_pll_clk_enable(struct clk_hw *hw)
244 {
245 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
246 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
247 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
248 while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
249 SIRFSOC_USBPHY_PLL_LOCK))
250 cpu_relax();
251
252 return 0;
253 }
254
usb_pll_clk_disable(struct clk_hw * clk)255 static void usb_pll_clk_disable(struct clk_hw *clk)
256 {
257 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
258 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
259 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
260 }
261
usb_pll_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)262 static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
263 {
264 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
265 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
266 }
267
268 static struct clk_ops usb_pll_ops = {
269 .enable = usb_pll_clk_enable,
270 .disable = usb_pll_clk_disable,
271 .recalc_rate = usb_pll_clk_recalc_rate,
272 };
273
274 static struct clk_init_data clk_usb_pll_init = {
275 .name = "usb_pll",
276 .ops = &usb_pll_ops,
277 .parent_names = pll_clk_parents,
278 .num_parents = ARRAY_SIZE(pll_clk_parents),
279 };
280
281 static struct clk_hw usb_pll_clk_hw = {
282 .init = &clk_usb_pll_init,
283 };
284
285 /*
286 * clock domains - cpu, mem, sys/io, dsp, gfx
287 */
288
289 static const char * const dmn_clk_parents[] = {
290 "rtc",
291 "osc",
292 "pll1",
293 "pll2",
294 "pll3",
295 };
296
dmn_clk_get_parent(struct clk_hw * hw)297 static u8 dmn_clk_get_parent(struct clk_hw *hw)
298 {
299 struct clk_dmn *clk = to_dmnclk(hw);
300 u32 cfg = clkc_readl(clk->regofs);
301 const char *name = clk_hw_get_name(hw);
302
303 /* parent of io domain can only be pll3 */
304 if (strcmp(name, "io") == 0)
305 return 4;
306
307 WARN_ON((cfg & (BIT(3) - 1)) > 4);
308
309 return cfg & (BIT(3) - 1);
310 }
311
dmn_clk_set_parent(struct clk_hw * hw,u8 parent)312 static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
313 {
314 struct clk_dmn *clk = to_dmnclk(hw);
315 u32 cfg = clkc_readl(clk->regofs);
316 const char *name = clk_hw_get_name(hw);
317
318 /* parent of io domain can only be pll3 */
319 if (strcmp(name, "io") == 0)
320 return -EINVAL;
321
322 cfg &= ~(BIT(3) - 1);
323 clkc_writel(cfg | parent, clk->regofs);
324 /* BIT(3) - switching status: 1 - busy, 0 - done */
325 while (clkc_readl(clk->regofs) & BIT(3))
326 cpu_relax();
327
328 return 0;
329 }
330
dmn_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)331 static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
332 unsigned long parent_rate)
333
334 {
335 unsigned long fin = parent_rate;
336 struct clk_dmn *clk = to_dmnclk(hw);
337
338 u32 cfg = clkc_readl(clk->regofs);
339
340 if (cfg & BIT(24)) {
341 /* fcd bypass mode */
342 return fin;
343 } else {
344 /*
345 * wait count: bit[19:16], hold count: bit[23:20]
346 */
347 u32 wait = (cfg >> 16) & (BIT(4) - 1);
348 u32 hold = (cfg >> 20) & (BIT(4) - 1);
349
350 return fin / (wait + hold + 2);
351 }
352 }
353
dmn_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)354 static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
355 unsigned long *parent_rate)
356 {
357 unsigned long fin;
358 unsigned ratio, wait, hold;
359 const char *name = clk_hw_get_name(hw);
360 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
361
362 fin = *parent_rate;
363 ratio = fin / rate;
364
365 if (ratio < 2)
366 ratio = 2;
367 if (ratio > BIT(bits + 1))
368 ratio = BIT(bits + 1);
369
370 wait = (ratio >> 1) - 1;
371 hold = ratio - wait - 2;
372
373 return fin / (wait + hold + 2);
374 }
375
dmn_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)376 static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
377 unsigned long parent_rate)
378 {
379 struct clk_dmn *clk = to_dmnclk(hw);
380 unsigned long fin;
381 unsigned ratio, wait, hold, reg;
382 const char *name = clk_hw_get_name(hw);
383 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
384
385 fin = parent_rate;
386 ratio = fin / rate;
387
388 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
389 return -EINVAL;
390
391 WARN_ON(fin % rate);
392
393 wait = (ratio >> 1) - 1;
394 hold = ratio - wait - 2;
395
396 reg = clkc_readl(clk->regofs);
397 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
398 reg |= (wait << 16) | (hold << 20) | BIT(25);
399 clkc_writel(reg, clk->regofs);
400
401 /* waiting FCD been effective */
402 while (clkc_readl(clk->regofs) & BIT(25))
403 cpu_relax();
404
405 return 0;
406 }
407
cpu_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)408 static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
409 unsigned long parent_rate)
410 {
411 int ret1, ret2;
412 struct clk *cur_parent;
413
414 if (rate == clk_get_rate(clk_pll1.hw.clk)) {
415 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
416 return ret1;
417 }
418
419 if (rate == clk_get_rate(clk_pll2.hw.clk)) {
420 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
421 return ret1;
422 }
423
424 if (rate == clk_get_rate(clk_pll3.hw.clk)) {
425 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);
426 return ret1;
427 }
428
429 cur_parent = clk_get_parent(hw->clk);
430
431 /* switch to tmp pll before setting parent clock's rate */
432 if (cur_parent == clk_pll1.hw.clk) {
433 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
434 BUG_ON(ret1);
435 }
436
437 ret2 = clk_set_rate(clk_pll1.hw.clk, rate);
438
439 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
440
441 return ret2 ? ret2 : ret1;
442 }
443
444 static struct clk_ops msi_ops = {
445 .set_rate = dmn_clk_set_rate,
446 .round_rate = dmn_clk_round_rate,
447 .recalc_rate = dmn_clk_recalc_rate,
448 .set_parent = dmn_clk_set_parent,
449 .get_parent = dmn_clk_get_parent,
450 };
451
452 static struct clk_init_data clk_mem_init = {
453 .name = "mem",
454 .ops = &msi_ops,
455 .parent_names = dmn_clk_parents,
456 .num_parents = ARRAY_SIZE(dmn_clk_parents),
457 };
458
459 static struct clk_dmn clk_mem = {
460 .regofs = SIRFSOC_CLKC_MEM_CFG,
461 .hw = {
462 .init = &clk_mem_init,
463 },
464 };
465
466 static struct clk_init_data clk_sys_init = {
467 .name = "sys",
468 .ops = &msi_ops,
469 .parent_names = dmn_clk_parents,
470 .num_parents = ARRAY_SIZE(dmn_clk_parents),
471 .flags = CLK_SET_RATE_GATE,
472 };
473
474 static struct clk_dmn clk_sys = {
475 .regofs = SIRFSOC_CLKC_SYS_CFG,
476 .hw = {
477 .init = &clk_sys_init,
478 },
479 };
480
481 static struct clk_init_data clk_io_init = {
482 .name = "io",
483 .ops = &msi_ops,
484 .parent_names = dmn_clk_parents,
485 .num_parents = ARRAY_SIZE(dmn_clk_parents),
486 };
487
488 static struct clk_dmn clk_io = {
489 .regofs = SIRFSOC_CLKC_IO_CFG,
490 .hw = {
491 .init = &clk_io_init,
492 },
493 };
494
495 static struct clk_ops cpu_ops = {
496 .set_parent = dmn_clk_set_parent,
497 .get_parent = dmn_clk_get_parent,
498 .set_rate = cpu_clk_set_rate,
499 .round_rate = cpu_clk_round_rate,
500 .recalc_rate = cpu_clk_recalc_rate,
501 };
502
503 static struct clk_init_data clk_cpu_init = {
504 .name = "cpu",
505 .ops = &cpu_ops,
506 .parent_names = dmn_clk_parents,
507 .num_parents = ARRAY_SIZE(dmn_clk_parents),
508 .flags = CLK_SET_RATE_PARENT,
509 };
510
511 static struct clk_dmn clk_cpu = {
512 .regofs = SIRFSOC_CLKC_CPU_CFG,
513 .hw = {
514 .init = &clk_cpu_init,
515 },
516 };
517
518 static struct clk_ops dmn_ops = {
519 .is_enabled = std_clk_is_enabled,
520 .enable = std_clk_enable,
521 .disable = std_clk_disable,
522 .set_rate = dmn_clk_set_rate,
523 .round_rate = dmn_clk_round_rate,
524 .recalc_rate = dmn_clk_recalc_rate,
525 .set_parent = dmn_clk_set_parent,
526 .get_parent = dmn_clk_get_parent,
527 };
528
529 /* dsp, gfx, mm, lcd and vpp domain */
530
531 static struct clk_init_data clk_dsp_init = {
532 .name = "dsp",
533 .ops = &dmn_ops,
534 .parent_names = dmn_clk_parents,
535 .num_parents = ARRAY_SIZE(dmn_clk_parents),
536 };
537
538 static struct clk_dmn clk_dsp = {
539 .regofs = SIRFSOC_CLKC_DSP_CFG,
540 .enable_bit = 0,
541 .hw = {
542 .init = &clk_dsp_init,
543 },
544 };
545
546 static struct clk_init_data clk_gfx_init = {
547 .name = "gfx",
548 .ops = &dmn_ops,
549 .parent_names = dmn_clk_parents,
550 .num_parents = ARRAY_SIZE(dmn_clk_parents),
551 };
552
553 static struct clk_dmn clk_gfx = {
554 .regofs = SIRFSOC_CLKC_GFX_CFG,
555 .enable_bit = 8,
556 .hw = {
557 .init = &clk_gfx_init,
558 },
559 };
560
561 static struct clk_init_data clk_mm_init = {
562 .name = "mm",
563 .ops = &dmn_ops,
564 .parent_names = dmn_clk_parents,
565 .num_parents = ARRAY_SIZE(dmn_clk_parents),
566 };
567
568 static struct clk_dmn clk_mm = {
569 .regofs = SIRFSOC_CLKC_MM_CFG,
570 .enable_bit = 9,
571 .hw = {
572 .init = &clk_mm_init,
573 },
574 };
575
576 /*
577 * for atlas6, gfx2d holds the bit of prima2's clk_mm
578 */
579 #define clk_gfx2d clk_mm
580
581 static struct clk_init_data clk_lcd_init = {
582 .name = "lcd",
583 .ops = &dmn_ops,
584 .parent_names = dmn_clk_parents,
585 .num_parents = ARRAY_SIZE(dmn_clk_parents),
586 };
587
588 static struct clk_dmn clk_lcd = {
589 .regofs = SIRFSOC_CLKC_LCD_CFG,
590 .enable_bit = 10,
591 .hw = {
592 .init = &clk_lcd_init,
593 },
594 };
595
596 static struct clk_init_data clk_vpp_init = {
597 .name = "vpp",
598 .ops = &dmn_ops,
599 .parent_names = dmn_clk_parents,
600 .num_parents = ARRAY_SIZE(dmn_clk_parents),
601 };
602
603 static struct clk_dmn clk_vpp = {
604 .regofs = SIRFSOC_CLKC_LCD_CFG,
605 .enable_bit = 11,
606 .hw = {
607 .init = &clk_vpp_init,
608 },
609 };
610
611 static struct clk_init_data clk_mmc01_init = {
612 .name = "mmc01",
613 .ops = &dmn_ops,
614 .parent_names = dmn_clk_parents,
615 .num_parents = ARRAY_SIZE(dmn_clk_parents),
616 };
617
618 static struct clk_init_data clk_mmc23_init = {
619 .name = "mmc23",
620 .ops = &dmn_ops,
621 .parent_names = dmn_clk_parents,
622 .num_parents = ARRAY_SIZE(dmn_clk_parents),
623 };
624
625 static struct clk_init_data clk_mmc45_init = {
626 .name = "mmc45",
627 .ops = &dmn_ops,
628 .parent_names = dmn_clk_parents,
629 .num_parents = ARRAY_SIZE(dmn_clk_parents),
630 };
631
632 /*
633 * peripheral controllers in io domain
634 */
635
std_clk_is_enabled(struct clk_hw * hw)636 static int std_clk_is_enabled(struct clk_hw *hw)
637 {
638 u32 reg;
639 int bit;
640 struct clk_std *clk = to_stdclk(hw);
641
642 bit = clk->enable_bit % 32;
643 reg = clk->enable_bit / 32;
644 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
645
646 return !!(clkc_readl(reg) & BIT(bit));
647 }
648
std_clk_enable(struct clk_hw * hw)649 static int std_clk_enable(struct clk_hw *hw)
650 {
651 u32 val, reg;
652 int bit;
653 struct clk_std *clk = to_stdclk(hw);
654
655 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
656
657 bit = clk->enable_bit % 32;
658 reg = clk->enable_bit / 32;
659 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
660
661 val = clkc_readl(reg) | BIT(bit);
662 clkc_writel(val, reg);
663 return 0;
664 }
665
std_clk_disable(struct clk_hw * hw)666 static void std_clk_disable(struct clk_hw *hw)
667 {
668 u32 val, reg;
669 int bit;
670 struct clk_std *clk = to_stdclk(hw);
671
672 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
673
674 bit = clk->enable_bit % 32;
675 reg = clk->enable_bit / 32;
676 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
677
678 val = clkc_readl(reg) & ~BIT(bit);
679 clkc_writel(val, reg);
680 }
681
682 static const char * const std_clk_io_parents[] = {
683 "io",
684 };
685
686 static struct clk_ops ios_ops = {
687 .is_enabled = std_clk_is_enabled,
688 .enable = std_clk_enable,
689 .disable = std_clk_disable,
690 };
691
692 static struct clk_init_data clk_cphif_init = {
693 .name = "cphif",
694 .ops = &ios_ops,
695 .parent_names = std_clk_io_parents,
696 .num_parents = ARRAY_SIZE(std_clk_io_parents),
697 };
698
699 static struct clk_std clk_cphif = {
700 .enable_bit = 20,
701 .hw = {
702 .init = &clk_cphif_init,
703 },
704 };
705
706 static struct clk_init_data clk_dmac0_init = {
707 .name = "dmac0",
708 .ops = &ios_ops,
709 .parent_names = std_clk_io_parents,
710 .num_parents = ARRAY_SIZE(std_clk_io_parents),
711 };
712
713 static struct clk_std clk_dmac0 = {
714 .enable_bit = 32,
715 .hw = {
716 .init = &clk_dmac0_init,
717 },
718 };
719
720 static struct clk_init_data clk_dmac1_init = {
721 .name = "dmac1",
722 .ops = &ios_ops,
723 .parent_names = std_clk_io_parents,
724 .num_parents = ARRAY_SIZE(std_clk_io_parents),
725 };
726
727 static struct clk_std clk_dmac1 = {
728 .enable_bit = 33,
729 .hw = {
730 .init = &clk_dmac1_init,
731 },
732 };
733
734 static struct clk_init_data clk_audio_init = {
735 .name = "audio",
736 .ops = &ios_ops,
737 .parent_names = std_clk_io_parents,
738 .num_parents = ARRAY_SIZE(std_clk_io_parents),
739 };
740
741 static struct clk_std clk_audio = {
742 .enable_bit = 35,
743 .hw = {
744 .init = &clk_audio_init,
745 },
746 };
747
748 static struct clk_init_data clk_uart0_init = {
749 .name = "uart0",
750 .ops = &ios_ops,
751 .parent_names = std_clk_io_parents,
752 .num_parents = ARRAY_SIZE(std_clk_io_parents),
753 };
754
755 static struct clk_std clk_uart0 = {
756 .enable_bit = 36,
757 .hw = {
758 .init = &clk_uart0_init,
759 },
760 };
761
762 static struct clk_init_data clk_uart1_init = {
763 .name = "uart1",
764 .ops = &ios_ops,
765 .parent_names = std_clk_io_parents,
766 .num_parents = ARRAY_SIZE(std_clk_io_parents),
767 };
768
769 static struct clk_std clk_uart1 = {
770 .enable_bit = 37,
771 .hw = {
772 .init = &clk_uart1_init,
773 },
774 };
775
776 static struct clk_init_data clk_uart2_init = {
777 .name = "uart2",
778 .ops = &ios_ops,
779 .parent_names = std_clk_io_parents,
780 .num_parents = ARRAY_SIZE(std_clk_io_parents),
781 };
782
783 static struct clk_std clk_uart2 = {
784 .enable_bit = 38,
785 .hw = {
786 .init = &clk_uart2_init,
787 },
788 };
789
790 static struct clk_init_data clk_usp0_init = {
791 .name = "usp0",
792 .ops = &ios_ops,
793 .parent_names = std_clk_io_parents,
794 .num_parents = ARRAY_SIZE(std_clk_io_parents),
795 };
796
797 static struct clk_std clk_usp0 = {
798 .enable_bit = 39,
799 .hw = {
800 .init = &clk_usp0_init,
801 },
802 };
803
804 static struct clk_init_data clk_usp1_init = {
805 .name = "usp1",
806 .ops = &ios_ops,
807 .parent_names = std_clk_io_parents,
808 .num_parents = ARRAY_SIZE(std_clk_io_parents),
809 };
810
811 static struct clk_std clk_usp1 = {
812 .enable_bit = 40,
813 .hw = {
814 .init = &clk_usp1_init,
815 },
816 };
817
818 static struct clk_init_data clk_usp2_init = {
819 .name = "usp2",
820 .ops = &ios_ops,
821 .parent_names = std_clk_io_parents,
822 .num_parents = ARRAY_SIZE(std_clk_io_parents),
823 };
824
825 static struct clk_std clk_usp2 = {
826 .enable_bit = 41,
827 .hw = {
828 .init = &clk_usp2_init,
829 },
830 };
831
832 static struct clk_init_data clk_vip_init = {
833 .name = "vip",
834 .ops = &ios_ops,
835 .parent_names = std_clk_io_parents,
836 .num_parents = ARRAY_SIZE(std_clk_io_parents),
837 };
838
839 static struct clk_std clk_vip = {
840 .enable_bit = 42,
841 .hw = {
842 .init = &clk_vip_init,
843 },
844 };
845
846 static struct clk_init_data clk_spi0_init = {
847 .name = "spi0",
848 .ops = &ios_ops,
849 .parent_names = std_clk_io_parents,
850 .num_parents = ARRAY_SIZE(std_clk_io_parents),
851 };
852
853 static struct clk_std clk_spi0 = {
854 .enable_bit = 43,
855 .hw = {
856 .init = &clk_spi0_init,
857 },
858 };
859
860 static struct clk_init_data clk_spi1_init = {
861 .name = "spi1",
862 .ops = &ios_ops,
863 .parent_names = std_clk_io_parents,
864 .num_parents = ARRAY_SIZE(std_clk_io_parents),
865 };
866
867 static struct clk_std clk_spi1 = {
868 .enable_bit = 44,
869 .hw = {
870 .init = &clk_spi1_init,
871 },
872 };
873
874 static struct clk_init_data clk_tsc_init = {
875 .name = "tsc",
876 .ops = &ios_ops,
877 .parent_names = std_clk_io_parents,
878 .num_parents = ARRAY_SIZE(std_clk_io_parents),
879 };
880
881 static struct clk_std clk_tsc = {
882 .enable_bit = 45,
883 .hw = {
884 .init = &clk_tsc_init,
885 },
886 };
887
888 static struct clk_init_data clk_i2c0_init = {
889 .name = "i2c0",
890 .ops = &ios_ops,
891 .parent_names = std_clk_io_parents,
892 .num_parents = ARRAY_SIZE(std_clk_io_parents),
893 };
894
895 static struct clk_std clk_i2c0 = {
896 .enable_bit = 46,
897 .hw = {
898 .init = &clk_i2c0_init,
899 },
900 };
901
902 static struct clk_init_data clk_i2c1_init = {
903 .name = "i2c1",
904 .ops = &ios_ops,
905 .parent_names = std_clk_io_parents,
906 .num_parents = ARRAY_SIZE(std_clk_io_parents),
907 };
908
909 static struct clk_std clk_i2c1 = {
910 .enable_bit = 47,
911 .hw = {
912 .init = &clk_i2c1_init,
913 },
914 };
915
916 static struct clk_init_data clk_pwmc_init = {
917 .name = "pwmc",
918 .ops = &ios_ops,
919 .parent_names = std_clk_io_parents,
920 .num_parents = ARRAY_SIZE(std_clk_io_parents),
921 };
922
923 static struct clk_std clk_pwmc = {
924 .enable_bit = 48,
925 .hw = {
926 .init = &clk_pwmc_init,
927 },
928 };
929
930 static struct clk_init_data clk_efuse_init = {
931 .name = "efuse",
932 .ops = &ios_ops,
933 .parent_names = std_clk_io_parents,
934 .num_parents = ARRAY_SIZE(std_clk_io_parents),
935 };
936
937 static struct clk_std clk_efuse = {
938 .enable_bit = 49,
939 .hw = {
940 .init = &clk_efuse_init,
941 },
942 };
943
944 static struct clk_init_data clk_pulse_init = {
945 .name = "pulse",
946 .ops = &ios_ops,
947 .parent_names = std_clk_io_parents,
948 .num_parents = ARRAY_SIZE(std_clk_io_parents),
949 };
950
951 static struct clk_std clk_pulse = {
952 .enable_bit = 50,
953 .hw = {
954 .init = &clk_pulse_init,
955 },
956 };
957
958 static const char * const std_clk_dsp_parents[] = {
959 "dsp",
960 };
961
962 static struct clk_init_data clk_gps_init = {
963 .name = "gps",
964 .ops = &ios_ops,
965 .parent_names = std_clk_dsp_parents,
966 .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
967 };
968
969 static struct clk_std clk_gps = {
970 .enable_bit = 1,
971 .hw = {
972 .init = &clk_gps_init,
973 },
974 };
975
976 static struct clk_init_data clk_mf_init = {
977 .name = "mf",
978 .ops = &ios_ops,
979 .parent_names = std_clk_io_parents,
980 .num_parents = ARRAY_SIZE(std_clk_io_parents),
981 };
982
983 static struct clk_std clk_mf = {
984 .enable_bit = 2,
985 .hw = {
986 .init = &clk_mf_init,
987 },
988 };
989
990 static const char * const std_clk_sys_parents[] = {
991 "sys",
992 };
993
994 static struct clk_init_data clk_security_init = {
995 .name = "security",
996 .ops = &ios_ops,
997 .parent_names = std_clk_sys_parents,
998 .num_parents = ARRAY_SIZE(std_clk_sys_parents),
999 };
1000
1001 static struct clk_std clk_security = {
1002 .enable_bit = 19,
1003 .hw = {
1004 .init = &clk_security_init,
1005 },
1006 };
1007
1008 static const char * const std_clk_usb_parents[] = {
1009 "usb_pll",
1010 };
1011
1012 static struct clk_init_data clk_usb0_init = {
1013 .name = "usb0",
1014 .ops = &ios_ops,
1015 .parent_names = std_clk_usb_parents,
1016 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1017 };
1018
1019 static struct clk_std clk_usb0 = {
1020 .enable_bit = 16,
1021 .hw = {
1022 .init = &clk_usb0_init,
1023 },
1024 };
1025
1026 static struct clk_init_data clk_usb1_init = {
1027 .name = "usb1",
1028 .ops = &ios_ops,
1029 .parent_names = std_clk_usb_parents,
1030 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1031 };
1032
1033 static struct clk_std clk_usb1 = {
1034 .enable_bit = 17,
1035 .hw = {
1036 .init = &clk_usb1_init,
1037 },
1038 };
1039