1 /*
2 * OMAP APLL clock support
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * J Keerthy <j-keerthy@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/io.h>
23 #include <linux/err.h>
24 #include <linux/string.h>
25 #include <linux/log2.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/clk/ti.h>
29 #include <linux/delay.h>
30
31 #include "clock.h"
32
33 #define APLL_FORCE_LOCK 0x1
34 #define APLL_AUTO_IDLE 0x2
35 #define MAX_APLL_WAIT_TRIES 1000000
36
37 #undef pr_fmt
38 #define pr_fmt(fmt) "%s: " fmt, __func__
39
dra7_apll_enable(struct clk_hw * hw)40 static int dra7_apll_enable(struct clk_hw *hw)
41 {
42 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
43 int r = 0, i = 0;
44 struct dpll_data *ad;
45 const char *clk_name;
46 u8 state = 1;
47 u32 v;
48
49 ad = clk->dpll_data;
50 if (!ad)
51 return -EINVAL;
52
53 clk_name = clk_hw_get_name(&clk->hw);
54
55 state <<= __ffs(ad->idlest_mask);
56
57 /* Check is already locked */
58 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
59
60 if ((v & ad->idlest_mask) == state)
61 return r;
62
63 v = ti_clk_ll_ops->clk_readl(ad->control_reg);
64 v &= ~ad->enable_mask;
65 v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
66 ti_clk_ll_ops->clk_writel(v, ad->control_reg);
67
68 state <<= __ffs(ad->idlest_mask);
69
70 while (1) {
71 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
72 if ((v & ad->idlest_mask) == state)
73 break;
74 if (i > MAX_APLL_WAIT_TRIES)
75 break;
76 i++;
77 udelay(1);
78 }
79
80 if (i == MAX_APLL_WAIT_TRIES) {
81 pr_warn("clock: %s failed transition to '%s'\n",
82 clk_name, (state) ? "locked" : "bypassed");
83 r = -EBUSY;
84 } else
85 pr_debug("clock: %s transition to '%s' in %d loops\n",
86 clk_name, (state) ? "locked" : "bypassed", i);
87
88 return r;
89 }
90
dra7_apll_disable(struct clk_hw * hw)91 static void dra7_apll_disable(struct clk_hw *hw)
92 {
93 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
94 struct dpll_data *ad;
95 u8 state = 1;
96 u32 v;
97
98 ad = clk->dpll_data;
99
100 state <<= __ffs(ad->idlest_mask);
101
102 v = ti_clk_ll_ops->clk_readl(ad->control_reg);
103 v &= ~ad->enable_mask;
104 v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
105 ti_clk_ll_ops->clk_writel(v, ad->control_reg);
106 }
107
dra7_apll_is_enabled(struct clk_hw * hw)108 static int dra7_apll_is_enabled(struct clk_hw *hw)
109 {
110 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
111 struct dpll_data *ad;
112 u32 v;
113
114 ad = clk->dpll_data;
115
116 v = ti_clk_ll_ops->clk_readl(ad->control_reg);
117 v &= ad->enable_mask;
118
119 v >>= __ffs(ad->enable_mask);
120
121 return v == APLL_AUTO_IDLE ? 0 : 1;
122 }
123
dra7_init_apll_parent(struct clk_hw * hw)124 static u8 dra7_init_apll_parent(struct clk_hw *hw)
125 {
126 return 0;
127 }
128
129 static const struct clk_ops apll_ck_ops = {
130 .enable = &dra7_apll_enable,
131 .disable = &dra7_apll_disable,
132 .is_enabled = &dra7_apll_is_enabled,
133 .get_parent = &dra7_init_apll_parent,
134 };
135
omap_clk_register_apll(struct clk_hw * hw,struct device_node * node)136 static void __init omap_clk_register_apll(struct clk_hw *hw,
137 struct device_node *node)
138 {
139 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
140 struct dpll_data *ad = clk_hw->dpll_data;
141 struct clk *clk;
142
143 ad->clk_ref = of_clk_get(node, 0);
144 ad->clk_bypass = of_clk_get(node, 1);
145
146 if (IS_ERR(ad->clk_ref) || IS_ERR(ad->clk_bypass)) {
147 pr_debug("clk-ref or clk-bypass for %s not ready, retry\n",
148 node->name);
149 if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
150 return;
151
152 goto cleanup;
153 }
154
155 clk = clk_register(NULL, &clk_hw->hw);
156 if (!IS_ERR(clk)) {
157 of_clk_add_provider(node, of_clk_src_simple_get, clk);
158 kfree(clk_hw->hw.init->parent_names);
159 kfree(clk_hw->hw.init);
160 return;
161 }
162
163 cleanup:
164 kfree(clk_hw->dpll_data);
165 kfree(clk_hw->hw.init->parent_names);
166 kfree(clk_hw->hw.init);
167 kfree(clk_hw);
168 }
169
of_dra7_apll_setup(struct device_node * node)170 static void __init of_dra7_apll_setup(struct device_node *node)
171 {
172 struct dpll_data *ad = NULL;
173 struct clk_hw_omap *clk_hw = NULL;
174 struct clk_init_data *init = NULL;
175 const char **parent_names = NULL;
176
177 ad = kzalloc(sizeof(*ad), GFP_KERNEL);
178 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
179 init = kzalloc(sizeof(*init), GFP_KERNEL);
180 if (!ad || !clk_hw || !init)
181 goto cleanup;
182
183 clk_hw->dpll_data = ad;
184 clk_hw->hw.init = init;
185 clk_hw->flags = MEMMAP_ADDRESSING;
186
187 init->name = node->name;
188 init->ops = &apll_ck_ops;
189
190 init->num_parents = of_clk_get_parent_count(node);
191 if (init->num_parents < 1) {
192 pr_err("dra7 apll %s must have parent(s)\n", node->name);
193 goto cleanup;
194 }
195
196 parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
197 if (!parent_names)
198 goto cleanup;
199
200 of_clk_parent_fill(node, parent_names, init->num_parents);
201
202 init->parent_names = parent_names;
203
204 ad->control_reg = ti_clk_get_reg_addr(node, 0);
205 ad->idlest_reg = ti_clk_get_reg_addr(node, 1);
206
207 if (IS_ERR(ad->control_reg) || IS_ERR(ad->idlest_reg))
208 goto cleanup;
209
210 ad->idlest_mask = 0x1;
211 ad->enable_mask = 0x3;
212
213 omap_clk_register_apll(&clk_hw->hw, node);
214 return;
215
216 cleanup:
217 kfree(parent_names);
218 kfree(ad);
219 kfree(clk_hw);
220 kfree(init);
221 }
222 CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
223
224 #define OMAP2_EN_APLL_LOCKED 0x3
225 #define OMAP2_EN_APLL_STOPPED 0x0
226
omap2_apll_is_enabled(struct clk_hw * hw)227 static int omap2_apll_is_enabled(struct clk_hw *hw)
228 {
229 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
230 struct dpll_data *ad = clk->dpll_data;
231 u32 v;
232
233 v = ti_clk_ll_ops->clk_readl(ad->control_reg);
234 v &= ad->enable_mask;
235
236 v >>= __ffs(ad->enable_mask);
237
238 return v == OMAP2_EN_APLL_LOCKED ? 1 : 0;
239 }
240
omap2_apll_recalc(struct clk_hw * hw,unsigned long parent_rate)241 static unsigned long omap2_apll_recalc(struct clk_hw *hw,
242 unsigned long parent_rate)
243 {
244 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
245
246 if (omap2_apll_is_enabled(hw))
247 return clk->fixed_rate;
248
249 return 0;
250 }
251
omap2_apll_enable(struct clk_hw * hw)252 static int omap2_apll_enable(struct clk_hw *hw)
253 {
254 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
255 struct dpll_data *ad = clk->dpll_data;
256 u32 v;
257 int i = 0;
258
259 v = ti_clk_ll_ops->clk_readl(ad->control_reg);
260 v &= ~ad->enable_mask;
261 v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
262 ti_clk_ll_ops->clk_writel(v, ad->control_reg);
263
264 while (1) {
265 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg);
266 if (v & ad->idlest_mask)
267 break;
268 if (i > MAX_APLL_WAIT_TRIES)
269 break;
270 i++;
271 udelay(1);
272 }
273
274 if (i == MAX_APLL_WAIT_TRIES) {
275 pr_warn("%s failed to transition to locked\n",
276 clk_hw_get_name(&clk->hw));
277 return -EBUSY;
278 }
279
280 return 0;
281 }
282
omap2_apll_disable(struct clk_hw * hw)283 static void omap2_apll_disable(struct clk_hw *hw)
284 {
285 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
286 struct dpll_data *ad = clk->dpll_data;
287 u32 v;
288
289 v = ti_clk_ll_ops->clk_readl(ad->control_reg);
290 v &= ~ad->enable_mask;
291 v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
292 ti_clk_ll_ops->clk_writel(v, ad->control_reg);
293 }
294
295 static struct clk_ops omap2_apll_ops = {
296 .enable = &omap2_apll_enable,
297 .disable = &omap2_apll_disable,
298 .is_enabled = &omap2_apll_is_enabled,
299 .recalc_rate = &omap2_apll_recalc,
300 };
301
omap2_apll_set_autoidle(struct clk_hw_omap * clk,u32 val)302 static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)
303 {
304 struct dpll_data *ad = clk->dpll_data;
305 u32 v;
306
307 v = ti_clk_ll_ops->clk_readl(ad->autoidle_reg);
308 v &= ~ad->autoidle_mask;
309 v |= val << __ffs(ad->autoidle_mask);
310 ti_clk_ll_ops->clk_writel(v, ad->control_reg);
311 }
312
313 #define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
314 #define OMAP2_APLL_AUTOIDLE_DISABLE 0x0
315
omap2_apll_allow_idle(struct clk_hw_omap * clk)316 static void omap2_apll_allow_idle(struct clk_hw_omap *clk)
317 {
318 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP);
319 }
320
omap2_apll_deny_idle(struct clk_hw_omap * clk)321 static void omap2_apll_deny_idle(struct clk_hw_omap *clk)
322 {
323 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE);
324 }
325
326 static struct clk_hw_omap_ops omap2_apll_hwops = {
327 .allow_idle = &omap2_apll_allow_idle,
328 .deny_idle = &omap2_apll_deny_idle,
329 };
330
of_omap2_apll_setup(struct device_node * node)331 static void __init of_omap2_apll_setup(struct device_node *node)
332 {
333 struct dpll_data *ad = NULL;
334 struct clk_hw_omap *clk_hw = NULL;
335 struct clk_init_data *init = NULL;
336 struct clk *clk;
337 const char *parent_name;
338 u32 val;
339
340 ad = kzalloc(sizeof(*ad), GFP_KERNEL);
341 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
342 init = kzalloc(sizeof(*init), GFP_KERNEL);
343
344 if (!ad || !clk_hw || !init)
345 goto cleanup;
346
347 clk_hw->dpll_data = ad;
348 clk_hw->hw.init = init;
349 init->ops = &omap2_apll_ops;
350 init->name = node->name;
351 clk_hw->ops = &omap2_apll_hwops;
352
353 init->num_parents = of_clk_get_parent_count(node);
354 if (init->num_parents != 1) {
355 pr_err("%s must have one parent\n", node->name);
356 goto cleanup;
357 }
358
359 parent_name = of_clk_get_parent_name(node, 0);
360 init->parent_names = &parent_name;
361
362 if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
363 pr_err("%s missing clock-frequency\n", node->name);
364 goto cleanup;
365 }
366 clk_hw->fixed_rate = val;
367
368 if (of_property_read_u32(node, "ti,bit-shift", &val)) {
369 pr_err("%s missing bit-shift\n", node->name);
370 goto cleanup;
371 }
372
373 clk_hw->enable_bit = val;
374 ad->enable_mask = 0x3 << val;
375 ad->autoidle_mask = 0x3 << val;
376
377 if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
378 pr_err("%s missing idlest-shift\n", node->name);
379 goto cleanup;
380 }
381
382 ad->idlest_mask = 1 << val;
383
384 ad->control_reg = ti_clk_get_reg_addr(node, 0);
385 ad->autoidle_reg = ti_clk_get_reg_addr(node, 1);
386 ad->idlest_reg = ti_clk_get_reg_addr(node, 2);
387
388 if (IS_ERR(ad->control_reg) || IS_ERR(ad->autoidle_reg) ||
389 IS_ERR(ad->idlest_reg))
390 goto cleanup;
391
392 clk = clk_register(NULL, &clk_hw->hw);
393 if (!IS_ERR(clk)) {
394 of_clk_add_provider(node, of_clk_src_simple_get, clk);
395 kfree(init);
396 return;
397 }
398 cleanup:
399 kfree(ad);
400 kfree(clk_hw);
401 kfree(init);
402 }
403 CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
404 of_omap2_apll_setup);
405