1 /*
2 * Clock driver for the ARM RealView boards
3 * Copyright (C) 2012 Linus Walleij
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9 #include <linux/clkdev.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/clk-provider.h>
13
14 #include <mach/hardware.h>
15 #include <mach/platform.h>
16
17 #include "clk-icst.h"
18
19 /*
20 * Implementation of the ARM RealView clock trees.
21 */
22
23 static const struct icst_params realview_oscvco_params = {
24 .ref = 24000000,
25 .vco_max = ICST307_VCO_MAX,
26 .vco_min = ICST307_VCO_MIN,
27 .vd_min = 4 + 8,
28 .vd_max = 511 + 8,
29 .rd_min = 1 + 2,
30 .rd_max = 127 + 2,
31 .s2div = icst307_s2div,
32 .idx2s = icst307_idx2s,
33 };
34
35 static const struct clk_icst_desc realview_osc0_desc __initconst = {
36 .params = &realview_oscvco_params,
37 .vco_offset = REALVIEW_SYS_OSC0_OFFSET,
38 .lock_offset = REALVIEW_SYS_LOCK_OFFSET,
39 };
40
41 static const struct clk_icst_desc realview_osc4_desc __initconst = {
42 .params = &realview_oscvco_params,
43 .vco_offset = REALVIEW_SYS_OSC4_OFFSET,
44 .lock_offset = REALVIEW_SYS_LOCK_OFFSET,
45 };
46
47 /*
48 * realview_clk_init() - set up the RealView clock tree
49 */
realview_clk_init(void __iomem * sysbase,bool is_pb1176)50 void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176)
51 {
52 struct clk *clk;
53
54 /* APB clock dummy */
55 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
56 clk_register_clkdev(clk, "apb_pclk", NULL);
57
58 /* 24 MHz clock */
59 clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
60 24000000);
61 clk_register_clkdev(clk, NULL, "dev:uart0");
62 clk_register_clkdev(clk, NULL, "dev:uart1");
63 clk_register_clkdev(clk, NULL, "dev:uart2");
64 clk_register_clkdev(clk, NULL, "fpga:kmi0");
65 clk_register_clkdev(clk, NULL, "fpga:kmi1");
66 clk_register_clkdev(clk, NULL, "fpga:mmc0");
67 clk_register_clkdev(clk, NULL, "dev:ssp0");
68 if (is_pb1176) {
69 /*
70 * UART3 is on the dev chip in PB1176
71 * UART4 only exists in PB1176
72 */
73 clk_register_clkdev(clk, NULL, "dev:uart3");
74 clk_register_clkdev(clk, NULL, "dev:uart4");
75 } else
76 clk_register_clkdev(clk, NULL, "fpga:uart3");
77
78
79 /* 1 MHz clock */
80 clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT,
81 1000000);
82 clk_register_clkdev(clk, NULL, "sp804");
83
84 /* ICST VCO clock */
85 if (is_pb1176)
86 clk = icst_clk_register(NULL, &realview_osc0_desc,
87 "osc0", NULL, sysbase);
88 else
89 clk = icst_clk_register(NULL, &realview_osc4_desc,
90 "osc4", NULL, sysbase);
91
92 clk_register_clkdev(clk, NULL, "dev:clcd");
93 clk_register_clkdev(clk, NULL, "issp:clcd");
94 }
95