1 /*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/cpu.h>
11 #include <linux/cpufreq.h>
12 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pm_opp.h>
16 #include <linux/platform_device.h>
17 #include <linux/regulator/consumer.h>
18
19 #define PU_SOC_VOLTAGE_NORMAL 1250000
20 #define PU_SOC_VOLTAGE_HIGH 1275000
21 #define FREQ_1P2_GHZ 1200000000
22
23 static struct regulator *arm_reg;
24 static struct regulator *pu_reg;
25 static struct regulator *soc_reg;
26
27 static struct clk *arm_clk;
28 static struct clk *pll1_sys_clk;
29 static struct clk *pll1_sw_clk;
30 static struct clk *step_clk;
31 static struct clk *pll2_pfd2_396m_clk;
32
33 /* clk used by i.MX6UL */
34 static struct clk *pll2_bus_clk;
35 static struct clk *secondary_sel_clk;
36
37 static struct device *cpu_dev;
38 static bool free_opp;
39 static struct cpufreq_frequency_table *freq_table;
40 static unsigned int transition_latency;
41
42 static u32 *imx6_soc_volt;
43 static u32 soc_opp_count;
44
imx6q_set_target(struct cpufreq_policy * policy,unsigned int index)45 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
46 {
47 struct dev_pm_opp *opp;
48 unsigned long freq_hz, volt, volt_old;
49 unsigned int old_freq, new_freq;
50 int ret;
51
52 new_freq = freq_table[index].frequency;
53 freq_hz = new_freq * 1000;
54 old_freq = clk_get_rate(arm_clk) / 1000;
55
56 rcu_read_lock();
57 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
58 if (IS_ERR(opp)) {
59 rcu_read_unlock();
60 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
61 return PTR_ERR(opp);
62 }
63
64 volt = dev_pm_opp_get_voltage(opp);
65 rcu_read_unlock();
66 volt_old = regulator_get_voltage(arm_reg);
67
68 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
69 old_freq / 1000, volt_old / 1000,
70 new_freq / 1000, volt / 1000);
71
72 /* scaling up? scale voltage before frequency */
73 if (new_freq > old_freq) {
74 if (!IS_ERR(pu_reg)) {
75 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
76 if (ret) {
77 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
78 return ret;
79 }
80 }
81 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
82 if (ret) {
83 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
84 return ret;
85 }
86 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
87 if (ret) {
88 dev_err(cpu_dev,
89 "failed to scale vddarm up: %d\n", ret);
90 return ret;
91 }
92 }
93
94 /*
95 * The setpoints are selected per PLL/PDF frequencies, so we need to
96 * reprogram PLL for frequency scaling. The procedure of reprogramming
97 * PLL1 is as below.
98 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
99 * flow is slightly different from other i.MX6 OSC.
100 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
101 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
102 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
103 * - Disable pll2_pfd2_396m_clk
104 */
105 if (of_machine_is_compatible("fsl,imx6ul")) {
106 /*
107 * When changing pll1_sw_clk's parent to pll1_sys_clk,
108 * CPU may run at higher than 528MHz, this will lead to
109 * the system unstable if the voltage is lower than the
110 * voltage of 528MHz, so lower the CPU frequency to one
111 * half before changing CPU frequency.
112 */
113 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
114 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
115 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
116 clk_set_parent(secondary_sel_clk, pll2_bus_clk);
117 else
118 clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
119 clk_set_parent(step_clk, secondary_sel_clk);
120 clk_set_parent(pll1_sw_clk, step_clk);
121 } else {
122 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
123 clk_set_parent(pll1_sw_clk, step_clk);
124 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
125 clk_set_rate(pll1_sys_clk, new_freq * 1000);
126 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
127 }
128 }
129
130 /* Ensure the arm clock divider is what we expect */
131 ret = clk_set_rate(arm_clk, new_freq * 1000);
132 if (ret) {
133 int ret1;
134
135 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
136 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
137 if (ret1)
138 dev_warn(cpu_dev,
139 "failed to restore vddarm voltage: %d\n", ret1);
140 return ret;
141 }
142
143 /* scaling down? scale voltage after frequency */
144 if (new_freq < old_freq) {
145 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
146 if (ret) {
147 dev_warn(cpu_dev,
148 "failed to scale vddarm down: %d\n", ret);
149 ret = 0;
150 }
151 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
152 if (ret) {
153 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
154 ret = 0;
155 }
156 if (!IS_ERR(pu_reg)) {
157 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
158 if (ret) {
159 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
160 ret = 0;
161 }
162 }
163 }
164
165 return 0;
166 }
167
imx6q_cpufreq_init(struct cpufreq_policy * policy)168 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
169 {
170 policy->clk = arm_clk;
171 return cpufreq_generic_init(policy, freq_table, transition_latency);
172 }
173
174 static struct cpufreq_driver imx6q_cpufreq_driver = {
175 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
176 .verify = cpufreq_generic_frequency_table_verify,
177 .target_index = imx6q_set_target,
178 .get = cpufreq_generic_get,
179 .init = imx6q_cpufreq_init,
180 .name = "imx6q-cpufreq",
181 .attr = cpufreq_generic_attr,
182 };
183
imx6q_cpufreq_probe(struct platform_device * pdev)184 static int imx6q_cpufreq_probe(struct platform_device *pdev)
185 {
186 struct device_node *np;
187 struct dev_pm_opp *opp;
188 unsigned long min_volt, max_volt;
189 int num, ret;
190 const struct property *prop;
191 const __be32 *val;
192 u32 nr, i, j;
193
194 cpu_dev = get_cpu_device(0);
195 if (!cpu_dev) {
196 pr_err("failed to get cpu0 device\n");
197 return -ENODEV;
198 }
199
200 np = of_node_get(cpu_dev->of_node);
201 if (!np) {
202 dev_err(cpu_dev, "failed to find cpu0 node\n");
203 return -ENOENT;
204 }
205
206 arm_clk = clk_get(cpu_dev, "arm");
207 pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
208 pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
209 step_clk = clk_get(cpu_dev, "step");
210 pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
211 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
212 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
213 dev_err(cpu_dev, "failed to get clocks\n");
214 ret = -ENOENT;
215 goto put_clk;
216 }
217
218 if (of_machine_is_compatible("fsl,imx6ul")) {
219 pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
220 secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
221 if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
222 dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
223 ret = -ENOENT;
224 goto put_clk;
225 }
226 }
227
228 arm_reg = regulator_get(cpu_dev, "arm");
229 pu_reg = regulator_get_optional(cpu_dev, "pu");
230 soc_reg = regulator_get(cpu_dev, "soc");
231 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
232 dev_err(cpu_dev, "failed to get regulators\n");
233 ret = -ENOENT;
234 goto put_reg;
235 }
236
237 /*
238 * We expect an OPP table supplied by platform.
239 * Just, incase the platform did not supply the OPP
240 * table, it will try to get it.
241 */
242 num = dev_pm_opp_get_opp_count(cpu_dev);
243 if (num < 0) {
244 ret = dev_pm_opp_of_add_table(cpu_dev);
245 if (ret < 0) {
246 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
247 goto put_reg;
248 }
249
250 /* Because we have added the OPPs here, we must free them */
251 free_opp = true;
252
253 num = dev_pm_opp_get_opp_count(cpu_dev);
254 if (num < 0) {
255 ret = num;
256 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
257 goto out_free_opp;
258 }
259 }
260
261 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
262 if (ret) {
263 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
264 goto put_reg;
265 }
266
267 /* Make imx6_soc_volt array's size same as arm opp number */
268 imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
269 if (imx6_soc_volt == NULL) {
270 ret = -ENOMEM;
271 goto free_freq_table;
272 }
273
274 prop = of_find_property(np, "fsl,soc-operating-points", NULL);
275 if (!prop || !prop->value)
276 goto soc_opp_out;
277
278 /*
279 * Each OPP is a set of tuples consisting of frequency and
280 * voltage like <freq-kHz vol-uV>.
281 */
282 nr = prop->length / sizeof(u32);
283 if (nr % 2 || (nr / 2) < num)
284 goto soc_opp_out;
285
286 for (j = 0; j < num; j++) {
287 val = prop->value;
288 for (i = 0; i < nr / 2; i++) {
289 unsigned long freq = be32_to_cpup(val++);
290 unsigned long volt = be32_to_cpup(val++);
291 if (freq_table[j].frequency == freq) {
292 imx6_soc_volt[soc_opp_count++] = volt;
293 break;
294 }
295 }
296 }
297
298 soc_opp_out:
299 /* use fixed soc opp volt if no valid soc opp info found in dtb */
300 if (soc_opp_count != num) {
301 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
302 for (j = 0; j < num; j++)
303 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
304 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
305 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
306 }
307
308 if (of_property_read_u32(np, "clock-latency", &transition_latency))
309 transition_latency = CPUFREQ_ETERNAL;
310
311 /*
312 * Calculate the ramp time for max voltage change in the
313 * VDDSOC and VDDPU regulators.
314 */
315 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
316 if (ret > 0)
317 transition_latency += ret * 1000;
318 if (!IS_ERR(pu_reg)) {
319 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
320 if (ret > 0)
321 transition_latency += ret * 1000;
322 }
323
324 /*
325 * OPP is maintained in order of increasing frequency, and
326 * freq_table initialised from OPP is therefore sorted in the
327 * same order.
328 */
329 rcu_read_lock();
330 opp = dev_pm_opp_find_freq_exact(cpu_dev,
331 freq_table[0].frequency * 1000, true);
332 min_volt = dev_pm_opp_get_voltage(opp);
333 opp = dev_pm_opp_find_freq_exact(cpu_dev,
334 freq_table[--num].frequency * 1000, true);
335 max_volt = dev_pm_opp_get_voltage(opp);
336 rcu_read_unlock();
337 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
338 if (ret > 0)
339 transition_latency += ret * 1000;
340
341 ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
342 if (ret) {
343 dev_err(cpu_dev, "failed register driver: %d\n", ret);
344 goto free_freq_table;
345 }
346
347 of_node_put(np);
348 return 0;
349
350 free_freq_table:
351 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
352 out_free_opp:
353 if (free_opp)
354 dev_pm_opp_of_remove_table(cpu_dev);
355 put_reg:
356 if (!IS_ERR(arm_reg))
357 regulator_put(arm_reg);
358 if (!IS_ERR(pu_reg))
359 regulator_put(pu_reg);
360 if (!IS_ERR(soc_reg))
361 regulator_put(soc_reg);
362 put_clk:
363 if (!IS_ERR(arm_clk))
364 clk_put(arm_clk);
365 if (!IS_ERR(pll1_sys_clk))
366 clk_put(pll1_sys_clk);
367 if (!IS_ERR(pll1_sw_clk))
368 clk_put(pll1_sw_clk);
369 if (!IS_ERR(step_clk))
370 clk_put(step_clk);
371 if (!IS_ERR(pll2_pfd2_396m_clk))
372 clk_put(pll2_pfd2_396m_clk);
373 if (!IS_ERR(pll2_bus_clk))
374 clk_put(pll2_bus_clk);
375 if (!IS_ERR(secondary_sel_clk))
376 clk_put(secondary_sel_clk);
377 of_node_put(np);
378 return ret;
379 }
380
imx6q_cpufreq_remove(struct platform_device * pdev)381 static int imx6q_cpufreq_remove(struct platform_device *pdev)
382 {
383 cpufreq_unregister_driver(&imx6q_cpufreq_driver);
384 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
385 if (free_opp)
386 dev_pm_opp_of_remove_table(cpu_dev);
387 regulator_put(arm_reg);
388 if (!IS_ERR(pu_reg))
389 regulator_put(pu_reg);
390 regulator_put(soc_reg);
391 clk_put(arm_clk);
392 clk_put(pll1_sys_clk);
393 clk_put(pll1_sw_clk);
394 clk_put(step_clk);
395 clk_put(pll2_pfd2_396m_clk);
396 clk_put(pll2_bus_clk);
397 clk_put(secondary_sel_clk);
398
399 return 0;
400 }
401
402 static struct platform_driver imx6q_cpufreq_platdrv = {
403 .driver = {
404 .name = "imx6q-cpufreq",
405 },
406 .probe = imx6q_cpufreq_probe,
407 .remove = imx6q_cpufreq_remove,
408 };
409 module_platform_driver(imx6q_cpufreq_platdrv);
410
411 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
412 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
413 MODULE_LICENSE("GPL");
414