1 /*
2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 *
12 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
13 * The only Atmel DMA Controller that is not covered by this driver is the one
14 * found on AT91SAM9263.
15 */
16
17 #include <dt-bindings/dma/at91.h>
18 #include <linux/clk.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dmapool.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_dma.h>
29
30 #include "at_hdmac_regs.h"
31 #include "dmaengine.h"
32
33 /*
34 * Glossary
35 * --------
36 *
37 * at_hdmac : Name of the ATmel AHB DMA Controller
38 * at_dma_ / atdma : ATmel DMA controller entity related
39 * atc_ / atchan : ATmel DMA Channel entity related
40 */
41
42 #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
43 #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
44 |ATC_DIF(AT_DMA_MEM_IF))
45 #define ATC_DMA_BUSWIDTHS\
46 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
47 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
48 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
49 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
50
51 #define ATC_MAX_DSCR_TRIALS 10
52
53 /*
54 * Initial number of descriptors to allocate for each channel. This could
55 * be increased during dma usage.
56 */
57 static unsigned int init_nr_desc_per_channel = 64;
58 module_param(init_nr_desc_per_channel, uint, 0644);
59 MODULE_PARM_DESC(init_nr_desc_per_channel,
60 "initial descriptors per channel (default: 64)");
61
62
63 /* prototypes */
64 static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
65 static void atc_issue_pending(struct dma_chan *chan);
66
67
68 /*----------------------------------------------------------------------*/
69
atc_get_xfer_width(dma_addr_t src,dma_addr_t dst,size_t len)70 static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst,
71 size_t len)
72 {
73 unsigned int width;
74
75 if (!((src | dst | len) & 3))
76 width = 2;
77 else if (!((src | dst | len) & 1))
78 width = 1;
79 else
80 width = 0;
81
82 return width;
83 }
84
atc_first_active(struct at_dma_chan * atchan)85 static struct at_desc *atc_first_active(struct at_dma_chan *atchan)
86 {
87 return list_first_entry(&atchan->active_list,
88 struct at_desc, desc_node);
89 }
90
atc_first_queued(struct at_dma_chan * atchan)91 static struct at_desc *atc_first_queued(struct at_dma_chan *atchan)
92 {
93 return list_first_entry(&atchan->queue,
94 struct at_desc, desc_node);
95 }
96
97 /**
98 * atc_alloc_descriptor - allocate and return an initialized descriptor
99 * @chan: the channel to allocate descriptors for
100 * @gfp_flags: GFP allocation flags
101 *
102 * Note: The ack-bit is positioned in the descriptor flag at creation time
103 * to make initial allocation more convenient. This bit will be cleared
104 * and control will be given to client at usage time (during
105 * preparation functions).
106 */
atc_alloc_descriptor(struct dma_chan * chan,gfp_t gfp_flags)107 static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan,
108 gfp_t gfp_flags)
109 {
110 struct at_desc *desc = NULL;
111 struct at_dma *atdma = to_at_dma(chan->device);
112 dma_addr_t phys;
113
114 desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys);
115 if (desc) {
116 memset(desc, 0, sizeof(struct at_desc));
117 INIT_LIST_HEAD(&desc->tx_list);
118 dma_async_tx_descriptor_init(&desc->txd, chan);
119 /* txd.flags will be overwritten in prep functions */
120 desc->txd.flags = DMA_CTRL_ACK;
121 desc->txd.tx_submit = atc_tx_submit;
122 desc->txd.phys = phys;
123 }
124
125 return desc;
126 }
127
128 /**
129 * atc_desc_get - get an unused descriptor from free_list
130 * @atchan: channel we want a new descriptor for
131 */
atc_desc_get(struct at_dma_chan * atchan)132 static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
133 {
134 struct at_desc *desc, *_desc;
135 struct at_desc *ret = NULL;
136 unsigned long flags;
137 unsigned int i = 0;
138 LIST_HEAD(tmp_list);
139
140 spin_lock_irqsave(&atchan->lock, flags);
141 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
142 i++;
143 if (async_tx_test_ack(&desc->txd)) {
144 list_del(&desc->desc_node);
145 ret = desc;
146 break;
147 }
148 dev_dbg(chan2dev(&atchan->chan_common),
149 "desc %p not ACKed\n", desc);
150 }
151 spin_unlock_irqrestore(&atchan->lock, flags);
152 dev_vdbg(chan2dev(&atchan->chan_common),
153 "scanned %u descriptors on freelist\n", i);
154
155 /* no more descriptor available in initial pool: create one more */
156 if (!ret) {
157 ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC);
158 if (ret) {
159 spin_lock_irqsave(&atchan->lock, flags);
160 atchan->descs_allocated++;
161 spin_unlock_irqrestore(&atchan->lock, flags);
162 } else {
163 dev_err(chan2dev(&atchan->chan_common),
164 "not enough descriptors available\n");
165 }
166 }
167
168 return ret;
169 }
170
171 /**
172 * atc_desc_put - move a descriptor, including any children, to the free list
173 * @atchan: channel we work on
174 * @desc: descriptor, at the head of a chain, to move to free list
175 */
atc_desc_put(struct at_dma_chan * atchan,struct at_desc * desc)176 static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
177 {
178 if (desc) {
179 struct at_desc *child;
180 unsigned long flags;
181
182 spin_lock_irqsave(&atchan->lock, flags);
183 list_for_each_entry(child, &desc->tx_list, desc_node)
184 dev_vdbg(chan2dev(&atchan->chan_common),
185 "moving child desc %p to freelist\n",
186 child);
187 list_splice_init(&desc->tx_list, &atchan->free_list);
188 dev_vdbg(chan2dev(&atchan->chan_common),
189 "moving desc %p to freelist\n", desc);
190 list_add(&desc->desc_node, &atchan->free_list);
191 spin_unlock_irqrestore(&atchan->lock, flags);
192 }
193 }
194
195 /**
196 * atc_desc_chain - build chain adding a descriptor
197 * @first: address of first descriptor of the chain
198 * @prev: address of previous descriptor of the chain
199 * @desc: descriptor to queue
200 *
201 * Called from prep_* functions
202 */
atc_desc_chain(struct at_desc ** first,struct at_desc ** prev,struct at_desc * desc)203 static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
204 struct at_desc *desc)
205 {
206 if (!(*first)) {
207 *first = desc;
208 } else {
209 /* inform the HW lli about chaining */
210 (*prev)->lli.dscr = desc->txd.phys;
211 /* insert the link descriptor to the LD ring */
212 list_add_tail(&desc->desc_node,
213 &(*first)->tx_list);
214 }
215 *prev = desc;
216 }
217
218 /**
219 * atc_dostart - starts the DMA engine for real
220 * @atchan: the channel we want to start
221 * @first: first descriptor in the list we want to begin with
222 *
223 * Called with atchan->lock held and bh disabled
224 */
atc_dostart(struct at_dma_chan * atchan,struct at_desc * first)225 static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
226 {
227 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
228
229 /* ASSERT: channel is idle */
230 if (atc_chan_is_enabled(atchan)) {
231 dev_err(chan2dev(&atchan->chan_common),
232 "BUG: Attempted to start non-idle channel\n");
233 dev_err(chan2dev(&atchan->chan_common),
234 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
235 channel_readl(atchan, SADDR),
236 channel_readl(atchan, DADDR),
237 channel_readl(atchan, CTRLA),
238 channel_readl(atchan, CTRLB),
239 channel_readl(atchan, DSCR));
240
241 /* The tasklet will hopefully advance the queue... */
242 return;
243 }
244
245 vdbg_dump_regs(atchan);
246
247 channel_writel(atchan, SADDR, 0);
248 channel_writel(atchan, DADDR, 0);
249 channel_writel(atchan, CTRLA, 0);
250 channel_writel(atchan, CTRLB, 0);
251 channel_writel(atchan, DSCR, first->txd.phys);
252 channel_writel(atchan, SPIP, ATC_SPIP_HOLE(first->src_hole) |
253 ATC_SPIP_BOUNDARY(first->boundary));
254 channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) |
255 ATC_DPIP_BOUNDARY(first->boundary));
256 dma_writel(atdma, CHER, atchan->mask);
257
258 vdbg_dump_regs(atchan);
259 }
260
261 /*
262 * atc_get_desc_by_cookie - get the descriptor of a cookie
263 * @atchan: the DMA channel
264 * @cookie: the cookie to get the descriptor for
265 */
atc_get_desc_by_cookie(struct at_dma_chan * atchan,dma_cookie_t cookie)266 static struct at_desc *atc_get_desc_by_cookie(struct at_dma_chan *atchan,
267 dma_cookie_t cookie)
268 {
269 struct at_desc *desc, *_desc;
270
271 list_for_each_entry_safe(desc, _desc, &atchan->queue, desc_node) {
272 if (desc->txd.cookie == cookie)
273 return desc;
274 }
275
276 list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
277 if (desc->txd.cookie == cookie)
278 return desc;
279 }
280
281 return NULL;
282 }
283
284 /**
285 * atc_calc_bytes_left - calculates the number of bytes left according to the
286 * value read from CTRLA.
287 *
288 * @current_len: the number of bytes left before reading CTRLA
289 * @ctrla: the value of CTRLA
290 */
atc_calc_bytes_left(int current_len,u32 ctrla)291 static inline int atc_calc_bytes_left(int current_len, u32 ctrla)
292 {
293 u32 btsize = (ctrla & ATC_BTSIZE_MAX);
294 u32 src_width = ATC_REG_TO_SRC_WIDTH(ctrla);
295
296 /*
297 * According to the datasheet, when reading the Control A Register
298 * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the
299 * number of transfers completed on the Source Interface.
300 * So btsize is always a number of source width transfers.
301 */
302 return current_len - (btsize << src_width);
303 }
304
305 /**
306 * atc_get_bytes_left - get the number of bytes residue for a cookie
307 * @chan: DMA channel
308 * @cookie: transaction identifier to check status of
309 */
atc_get_bytes_left(struct dma_chan * chan,dma_cookie_t cookie)310 static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie)
311 {
312 struct at_dma_chan *atchan = to_at_dma_chan(chan);
313 struct at_desc *desc_first = atc_first_active(atchan);
314 struct at_desc *desc;
315 int ret;
316 u32 ctrla, dscr, trials;
317
318 /*
319 * If the cookie doesn't match to the currently running transfer then
320 * we can return the total length of the associated DMA transfer,
321 * because it is still queued.
322 */
323 desc = atc_get_desc_by_cookie(atchan, cookie);
324 if (desc == NULL)
325 return -EINVAL;
326 else if (desc != desc_first)
327 return desc->total_len;
328
329 /* cookie matches to the currently running transfer */
330 ret = desc_first->total_len;
331
332 if (desc_first->lli.dscr) {
333 /* hardware linked list transfer */
334
335 /*
336 * Calculate the residue by removing the length of the child
337 * descriptors already transferred from the total length.
338 * To get the current child descriptor we can use the value of
339 * the channel's DSCR register and compare it against the value
340 * of the hardware linked list structure of each child
341 * descriptor.
342 *
343 * The CTRLA register provides us with the amount of data
344 * already read from the source for the current child
345 * descriptor. So we can compute a more accurate residue by also
346 * removing the number of bytes corresponding to this amount of
347 * data.
348 *
349 * However, the DSCR and CTRLA registers cannot be read both
350 * atomically. Hence a race condition may occur: the first read
351 * register may refer to one child descriptor whereas the second
352 * read may refer to a later child descriptor in the list
353 * because of the DMA transfer progression inbetween the two
354 * reads.
355 *
356 * One solution could have been to pause the DMA transfer, read
357 * the DSCR and CTRLA then resume the DMA transfer. Nonetheless,
358 * this approach presents some drawbacks:
359 * - If the DMA transfer is paused, RX overruns or TX underruns
360 * are more likey to occur depending on the system latency.
361 * Taking the USART driver as an example, it uses a cyclic DMA
362 * transfer to read data from the Receive Holding Register
363 * (RHR) to avoid RX overruns since the RHR is not protected
364 * by any FIFO on most Atmel SoCs. So pausing the DMA transfer
365 * to compute the residue would break the USART driver design.
366 * - The atc_pause() function masks interrupts but we'd rather
367 * avoid to do so for system latency purpose.
368 *
369 * Then we'd rather use another solution: the DSCR is read a
370 * first time, the CTRLA is read in turn, next the DSCR is read
371 * a second time. If the two consecutive read values of the DSCR
372 * are the same then we assume both refers to the very same
373 * child descriptor as well as the CTRLA value read inbetween
374 * does. For cyclic tranfers, the assumption is that a full loop
375 * is "not so fast".
376 * If the two DSCR values are different, we read again the CTRLA
377 * then the DSCR till two consecutive read values from DSCR are
378 * equal or till the maxium trials is reach.
379 * This algorithm is very unlikely not to find a stable value for
380 * DSCR.
381 */
382
383 dscr = channel_readl(atchan, DSCR);
384 rmb(); /* ensure DSCR is read before CTRLA */
385 ctrla = channel_readl(atchan, CTRLA);
386 for (trials = 0; trials < ATC_MAX_DSCR_TRIALS; ++trials) {
387 u32 new_dscr;
388
389 rmb(); /* ensure DSCR is read after CTRLA */
390 new_dscr = channel_readl(atchan, DSCR);
391
392 /*
393 * If the DSCR register value has not changed inside the
394 * DMA controller since the previous read, we assume
395 * that both the dscr and ctrla values refers to the
396 * very same descriptor.
397 */
398 if (likely(new_dscr == dscr))
399 break;
400
401 /*
402 * DSCR has changed inside the DMA controller, so the
403 * previouly read value of CTRLA may refer to an already
404 * processed descriptor hence could be outdated.
405 * We need to update ctrla to match the current
406 * descriptor.
407 */
408 dscr = new_dscr;
409 rmb(); /* ensure DSCR is read before CTRLA */
410 ctrla = channel_readl(atchan, CTRLA);
411 }
412 if (unlikely(trials >= ATC_MAX_DSCR_TRIALS))
413 return -ETIMEDOUT;
414
415 /* for the first descriptor we can be more accurate */
416 if (desc_first->lli.dscr == dscr)
417 return atc_calc_bytes_left(ret, ctrla);
418
419 ret -= desc_first->len;
420 list_for_each_entry(desc, &desc_first->tx_list, desc_node) {
421 if (desc->lli.dscr == dscr)
422 break;
423
424 ret -= desc->len;
425 }
426
427 /*
428 * For the current descriptor in the chain we can calculate
429 * the remaining bytes using the channel's register.
430 */
431 ret = atc_calc_bytes_left(ret, ctrla);
432 } else {
433 /* single transfer */
434 ctrla = channel_readl(atchan, CTRLA);
435 ret = atc_calc_bytes_left(ret, ctrla);
436 }
437
438 return ret;
439 }
440
441 /**
442 * atc_chain_complete - finish work for one transaction chain
443 * @atchan: channel we work on
444 * @desc: descriptor at the head of the chain we want do complete
445 *
446 * Called with atchan->lock held and bh disabled */
447 static void
atc_chain_complete(struct at_dma_chan * atchan,struct at_desc * desc)448 atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
449 {
450 struct dma_async_tx_descriptor *txd = &desc->txd;
451 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
452
453 dev_vdbg(chan2dev(&atchan->chan_common),
454 "descriptor %u complete\n", txd->cookie);
455
456 /* mark the descriptor as complete for non cyclic cases only */
457 if (!atc_chan_is_cyclic(atchan))
458 dma_cookie_complete(txd);
459
460 /* If the transfer was a memset, free our temporary buffer */
461 if (desc->memset_buffer) {
462 dma_pool_free(atdma->memset_pool, desc->memset_vaddr,
463 desc->memset_paddr);
464 desc->memset_buffer = false;
465 }
466
467 /* move children to free_list */
468 list_splice_init(&desc->tx_list, &atchan->free_list);
469 /* move myself to free_list */
470 list_move(&desc->desc_node, &atchan->free_list);
471
472 dma_descriptor_unmap(txd);
473 /* for cyclic transfers,
474 * no need to replay callback function while stopping */
475 if (!atc_chan_is_cyclic(atchan)) {
476 dma_async_tx_callback callback = txd->callback;
477 void *param = txd->callback_param;
478
479 /*
480 * The API requires that no submissions are done from a
481 * callback, so we don't need to drop the lock here
482 */
483 if (callback)
484 callback(param);
485 }
486
487 dma_run_dependencies(txd);
488 }
489
490 /**
491 * atc_complete_all - finish work for all transactions
492 * @atchan: channel to complete transactions for
493 *
494 * Eventually submit queued descriptors if any
495 *
496 * Assume channel is idle while calling this function
497 * Called with atchan->lock held and bh disabled
498 */
atc_complete_all(struct at_dma_chan * atchan)499 static void atc_complete_all(struct at_dma_chan *atchan)
500 {
501 struct at_desc *desc, *_desc;
502 LIST_HEAD(list);
503
504 dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
505
506 /*
507 * Submit queued descriptors ASAP, i.e. before we go through
508 * the completed ones.
509 */
510 if (!list_empty(&atchan->queue))
511 atc_dostart(atchan, atc_first_queued(atchan));
512 /* empty active_list now it is completed */
513 list_splice_init(&atchan->active_list, &list);
514 /* empty queue list by moving descriptors (if any) to active_list */
515 list_splice_init(&atchan->queue, &atchan->active_list);
516
517 list_for_each_entry_safe(desc, _desc, &list, desc_node)
518 atc_chain_complete(atchan, desc);
519 }
520
521 /**
522 * atc_advance_work - at the end of a transaction, move forward
523 * @atchan: channel where the transaction ended
524 *
525 * Called with atchan->lock held and bh disabled
526 */
atc_advance_work(struct at_dma_chan * atchan)527 static void atc_advance_work(struct at_dma_chan *atchan)
528 {
529 dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
530
531 if (atc_chan_is_enabled(atchan))
532 return;
533
534 if (list_empty(&atchan->active_list) ||
535 list_is_singular(&atchan->active_list)) {
536 atc_complete_all(atchan);
537 } else {
538 atc_chain_complete(atchan, atc_first_active(atchan));
539 /* advance work */
540 atc_dostart(atchan, atc_first_active(atchan));
541 }
542 }
543
544
545 /**
546 * atc_handle_error - handle errors reported by DMA controller
547 * @atchan: channel where error occurs
548 *
549 * Called with atchan->lock held and bh disabled
550 */
atc_handle_error(struct at_dma_chan * atchan)551 static void atc_handle_error(struct at_dma_chan *atchan)
552 {
553 struct at_desc *bad_desc;
554 struct at_desc *child;
555
556 /*
557 * The descriptor currently at the head of the active list is
558 * broked. Since we don't have any way to report errors, we'll
559 * just have to scream loudly and try to carry on.
560 */
561 bad_desc = atc_first_active(atchan);
562 list_del_init(&bad_desc->desc_node);
563
564 /* As we are stopped, take advantage to push queued descriptors
565 * in active_list */
566 list_splice_init(&atchan->queue, atchan->active_list.prev);
567
568 /* Try to restart the controller */
569 if (!list_empty(&atchan->active_list))
570 atc_dostart(atchan, atc_first_active(atchan));
571
572 /*
573 * KERN_CRITICAL may seem harsh, but since this only happens
574 * when someone submits a bad physical address in a
575 * descriptor, we should consider ourselves lucky that the
576 * controller flagged an error instead of scribbling over
577 * random memory locations.
578 */
579 dev_crit(chan2dev(&atchan->chan_common),
580 "Bad descriptor submitted for DMA!\n");
581 dev_crit(chan2dev(&atchan->chan_common),
582 " cookie: %d\n", bad_desc->txd.cookie);
583 atc_dump_lli(atchan, &bad_desc->lli);
584 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
585 atc_dump_lli(atchan, &child->lli);
586
587 /* Pretend the descriptor completed successfully */
588 atc_chain_complete(atchan, bad_desc);
589 }
590
591 /**
592 * atc_handle_cyclic - at the end of a period, run callback function
593 * @atchan: channel used for cyclic operations
594 *
595 * Called with atchan->lock held and bh disabled
596 */
atc_handle_cyclic(struct at_dma_chan * atchan)597 static void atc_handle_cyclic(struct at_dma_chan *atchan)
598 {
599 struct at_desc *first = atc_first_active(atchan);
600 struct dma_async_tx_descriptor *txd = &first->txd;
601 dma_async_tx_callback callback = txd->callback;
602 void *param = txd->callback_param;
603
604 dev_vdbg(chan2dev(&atchan->chan_common),
605 "new cyclic period llp 0x%08x\n",
606 channel_readl(atchan, DSCR));
607
608 if (callback)
609 callback(param);
610 }
611
612 /*-- IRQ & Tasklet ---------------------------------------------------*/
613
atc_tasklet(unsigned long data)614 static void atc_tasklet(unsigned long data)
615 {
616 struct at_dma_chan *atchan = (struct at_dma_chan *)data;
617 unsigned long flags;
618
619 spin_lock_irqsave(&atchan->lock, flags);
620 if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
621 atc_handle_error(atchan);
622 else if (atc_chan_is_cyclic(atchan))
623 atc_handle_cyclic(atchan);
624 else
625 atc_advance_work(atchan);
626
627 spin_unlock_irqrestore(&atchan->lock, flags);
628 }
629
at_dma_interrupt(int irq,void * dev_id)630 static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
631 {
632 struct at_dma *atdma = (struct at_dma *)dev_id;
633 struct at_dma_chan *atchan;
634 int i;
635 u32 status, pending, imr;
636 int ret = IRQ_NONE;
637
638 do {
639 imr = dma_readl(atdma, EBCIMR);
640 status = dma_readl(atdma, EBCISR);
641 pending = status & imr;
642
643 if (!pending)
644 break;
645
646 dev_vdbg(atdma->dma_common.dev,
647 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
648 status, imr, pending);
649
650 for (i = 0; i < atdma->dma_common.chancnt; i++) {
651 atchan = &atdma->chan[i];
652 if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) {
653 if (pending & AT_DMA_ERR(i)) {
654 /* Disable channel on AHB error */
655 dma_writel(atdma, CHDR,
656 AT_DMA_RES(i) | atchan->mask);
657 /* Give information to tasklet */
658 set_bit(ATC_IS_ERROR, &atchan->status);
659 }
660 tasklet_schedule(&atchan->tasklet);
661 ret = IRQ_HANDLED;
662 }
663 }
664
665 } while (pending);
666
667 return ret;
668 }
669
670
671 /*-- DMA Engine API --------------------------------------------------*/
672
673 /**
674 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
675 * @desc: descriptor at the head of the transaction chain
676 *
677 * Queue chain if DMA engine is working already
678 *
679 * Cookie increment and adding to active_list or queue must be atomic
680 */
atc_tx_submit(struct dma_async_tx_descriptor * tx)681 static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
682 {
683 struct at_desc *desc = txd_to_at_desc(tx);
684 struct at_dma_chan *atchan = to_at_dma_chan(tx->chan);
685 dma_cookie_t cookie;
686 unsigned long flags;
687
688 spin_lock_irqsave(&atchan->lock, flags);
689 cookie = dma_cookie_assign(tx);
690
691 if (list_empty(&atchan->active_list)) {
692 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
693 desc->txd.cookie);
694 atc_dostart(atchan, desc);
695 list_add_tail(&desc->desc_node, &atchan->active_list);
696 } else {
697 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
698 desc->txd.cookie);
699 list_add_tail(&desc->desc_node, &atchan->queue);
700 }
701
702 spin_unlock_irqrestore(&atchan->lock, flags);
703
704 return cookie;
705 }
706
707 /**
708 * atc_prep_dma_interleaved - prepare memory to memory interleaved operation
709 * @chan: the channel to prepare operation on
710 * @xt: Interleaved transfer template
711 * @flags: tx descriptor status flags
712 */
713 static struct dma_async_tx_descriptor *
atc_prep_dma_interleaved(struct dma_chan * chan,struct dma_interleaved_template * xt,unsigned long flags)714 atc_prep_dma_interleaved(struct dma_chan *chan,
715 struct dma_interleaved_template *xt,
716 unsigned long flags)
717 {
718 struct at_dma_chan *atchan = to_at_dma_chan(chan);
719 struct data_chunk *first;
720 struct at_desc *desc = NULL;
721 size_t xfer_count;
722 unsigned int dwidth;
723 u32 ctrla;
724 u32 ctrlb;
725 size_t len = 0;
726 int i;
727
728 if (unlikely(!xt || xt->numf != 1 || !xt->frame_size))
729 return NULL;
730
731 first = xt->sgl;
732
733 dev_info(chan2dev(chan),
734 "%s: src=%pad, dest=%pad, numf=%d, frame_size=%d, flags=0x%lx\n",
735 __func__, &xt->src_start, &xt->dst_start, xt->numf,
736 xt->frame_size, flags);
737
738 /*
739 * The controller can only "skip" X bytes every Y bytes, so we
740 * need to make sure we are given a template that fit that
741 * description, ie a template with chunks that always have the
742 * same size, with the same ICGs.
743 */
744 for (i = 0; i < xt->frame_size; i++) {
745 struct data_chunk *chunk = xt->sgl + i;
746
747 if ((chunk->size != xt->sgl->size) ||
748 (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) ||
749 (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) {
750 dev_err(chan2dev(chan),
751 "%s: the controller can transfer only identical chunks\n",
752 __func__);
753 return NULL;
754 }
755
756 len += chunk->size;
757 }
758
759 dwidth = atc_get_xfer_width(xt->src_start,
760 xt->dst_start, len);
761
762 xfer_count = len >> dwidth;
763 if (xfer_count > ATC_BTSIZE_MAX) {
764 dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__);
765 return NULL;
766 }
767
768 ctrla = ATC_SRC_WIDTH(dwidth) |
769 ATC_DST_WIDTH(dwidth);
770
771 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
772 | ATC_SRC_ADDR_MODE_INCR
773 | ATC_DST_ADDR_MODE_INCR
774 | ATC_SRC_PIP
775 | ATC_DST_PIP
776 | ATC_FC_MEM2MEM;
777
778 /* create the transfer */
779 desc = atc_desc_get(atchan);
780 if (!desc) {
781 dev_err(chan2dev(chan),
782 "%s: couldn't allocate our descriptor\n", __func__);
783 return NULL;
784 }
785
786 desc->lli.saddr = xt->src_start;
787 desc->lli.daddr = xt->dst_start;
788 desc->lli.ctrla = ctrla | xfer_count;
789 desc->lli.ctrlb = ctrlb;
790
791 desc->boundary = first->size >> dwidth;
792 desc->dst_hole = (dmaengine_get_dst_icg(xt, first) >> dwidth) + 1;
793 desc->src_hole = (dmaengine_get_src_icg(xt, first) >> dwidth) + 1;
794
795 desc->txd.cookie = -EBUSY;
796 desc->total_len = desc->len = len;
797
798 /* set end-of-link to the last link descriptor of list*/
799 set_desc_eol(desc);
800
801 desc->txd.flags = flags; /* client is in control of this ack */
802
803 return &desc->txd;
804 }
805
806 /**
807 * atc_prep_dma_memcpy - prepare a memcpy operation
808 * @chan: the channel to prepare operation on
809 * @dest: operation virtual destination address
810 * @src: operation virtual source address
811 * @len: operation length
812 * @flags: tx descriptor status flags
813 */
814 static struct dma_async_tx_descriptor *
atc_prep_dma_memcpy(struct dma_chan * chan,dma_addr_t dest,dma_addr_t src,size_t len,unsigned long flags)815 atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
816 size_t len, unsigned long flags)
817 {
818 struct at_dma_chan *atchan = to_at_dma_chan(chan);
819 struct at_desc *desc = NULL;
820 struct at_desc *first = NULL;
821 struct at_desc *prev = NULL;
822 size_t xfer_count;
823 size_t offset;
824 unsigned int src_width;
825 unsigned int dst_width;
826 u32 ctrla;
827 u32 ctrlb;
828
829 dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d%pad s%pad l0x%zx f0x%lx\n",
830 &dest, &src, len, flags);
831
832 if (unlikely(!len)) {
833 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
834 return NULL;
835 }
836
837 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
838 | ATC_SRC_ADDR_MODE_INCR
839 | ATC_DST_ADDR_MODE_INCR
840 | ATC_FC_MEM2MEM;
841
842 /*
843 * We can be a lot more clever here, but this should take care
844 * of the most common optimization.
845 */
846 src_width = dst_width = atc_get_xfer_width(src, dest, len);
847
848 ctrla = ATC_SRC_WIDTH(src_width) |
849 ATC_DST_WIDTH(dst_width);
850
851 for (offset = 0; offset < len; offset += xfer_count << src_width) {
852 xfer_count = min_t(size_t, (len - offset) >> src_width,
853 ATC_BTSIZE_MAX);
854
855 desc = atc_desc_get(atchan);
856 if (!desc)
857 goto err_desc_get;
858
859 desc->lli.saddr = src + offset;
860 desc->lli.daddr = dest + offset;
861 desc->lli.ctrla = ctrla | xfer_count;
862 desc->lli.ctrlb = ctrlb;
863
864 desc->txd.cookie = 0;
865 desc->len = xfer_count << src_width;
866
867 atc_desc_chain(&first, &prev, desc);
868 }
869
870 /* First descriptor of the chain embedds additional information */
871 first->txd.cookie = -EBUSY;
872 first->total_len = len;
873
874 /* set end-of-link to the last link descriptor of list*/
875 set_desc_eol(desc);
876
877 first->txd.flags = flags; /* client is in control of this ack */
878
879 return &first->txd;
880
881 err_desc_get:
882 atc_desc_put(atchan, first);
883 return NULL;
884 }
885
atc_create_memset_desc(struct dma_chan * chan,dma_addr_t psrc,dma_addr_t pdst,size_t len)886 static struct at_desc *atc_create_memset_desc(struct dma_chan *chan,
887 dma_addr_t psrc,
888 dma_addr_t pdst,
889 size_t len)
890 {
891 struct at_dma_chan *atchan = to_at_dma_chan(chan);
892 struct at_desc *desc;
893 size_t xfer_count;
894
895 u32 ctrla = ATC_SRC_WIDTH(2) | ATC_DST_WIDTH(2);
896 u32 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
897 ATC_SRC_ADDR_MODE_FIXED |
898 ATC_DST_ADDR_MODE_INCR |
899 ATC_FC_MEM2MEM;
900
901 xfer_count = len >> 2;
902 if (xfer_count > ATC_BTSIZE_MAX) {
903 dev_err(chan2dev(chan), "%s: buffer is too big\n",
904 __func__);
905 return NULL;
906 }
907
908 desc = atc_desc_get(atchan);
909 if (!desc) {
910 dev_err(chan2dev(chan), "%s: can't get a descriptor\n",
911 __func__);
912 return NULL;
913 }
914
915 desc->lli.saddr = psrc;
916 desc->lli.daddr = pdst;
917 desc->lli.ctrla = ctrla | xfer_count;
918 desc->lli.ctrlb = ctrlb;
919
920 desc->txd.cookie = 0;
921 desc->len = len;
922
923 return desc;
924 }
925
926 /**
927 * atc_prep_dma_memset - prepare a memcpy operation
928 * @chan: the channel to prepare operation on
929 * @dest: operation virtual destination address
930 * @value: value to set memory buffer to
931 * @len: operation length
932 * @flags: tx descriptor status flags
933 */
934 static struct dma_async_tx_descriptor *
atc_prep_dma_memset(struct dma_chan * chan,dma_addr_t dest,int value,size_t len,unsigned long flags)935 atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
936 size_t len, unsigned long flags)
937 {
938 struct at_dma *atdma = to_at_dma(chan->device);
939 struct at_desc *desc;
940 void __iomem *vaddr;
941 dma_addr_t paddr;
942
943 dev_vdbg(chan2dev(chan), "%s: d%pad v0x%x l0x%zx f0x%lx\n", __func__,
944 &dest, value, len, flags);
945
946 if (unlikely(!len)) {
947 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
948 return NULL;
949 }
950
951 if (!is_dma_fill_aligned(chan->device, dest, 0, len)) {
952 dev_dbg(chan2dev(chan), "%s: buffer is not aligned\n",
953 __func__);
954 return NULL;
955 }
956
957 vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, &paddr);
958 if (!vaddr) {
959 dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n",
960 __func__);
961 return NULL;
962 }
963 *(u32*)vaddr = value;
964
965 desc = atc_create_memset_desc(chan, paddr, dest, len);
966 if (!desc) {
967 dev_err(chan2dev(chan), "%s: couldn't get a descriptor\n",
968 __func__);
969 goto err_free_buffer;
970 }
971
972 desc->memset_paddr = paddr;
973 desc->memset_vaddr = vaddr;
974 desc->memset_buffer = true;
975
976 desc->txd.cookie = -EBUSY;
977 desc->total_len = len;
978
979 /* set end-of-link on the descriptor */
980 set_desc_eol(desc);
981
982 desc->txd.flags = flags;
983
984 return &desc->txd;
985
986 err_free_buffer:
987 dma_pool_free(atdma->memset_pool, vaddr, paddr);
988 return NULL;
989 }
990
991 static struct dma_async_tx_descriptor *
atc_prep_dma_memset_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,int value,unsigned long flags)992 atc_prep_dma_memset_sg(struct dma_chan *chan,
993 struct scatterlist *sgl,
994 unsigned int sg_len, int value,
995 unsigned long flags)
996 {
997 struct at_dma_chan *atchan = to_at_dma_chan(chan);
998 struct at_dma *atdma = to_at_dma(chan->device);
999 struct at_desc *desc = NULL, *first = NULL, *prev = NULL;
1000 struct scatterlist *sg;
1001 void __iomem *vaddr;
1002 dma_addr_t paddr;
1003 size_t total_len = 0;
1004 int i;
1005
1006 dev_vdbg(chan2dev(chan), "%s: v0x%x l0x%zx f0x%lx\n", __func__,
1007 value, sg_len, flags);
1008
1009 if (unlikely(!sgl || !sg_len)) {
1010 dev_dbg(chan2dev(chan), "%s: scatterlist is empty!\n",
1011 __func__);
1012 return NULL;
1013 }
1014
1015 vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, &paddr);
1016 if (!vaddr) {
1017 dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n",
1018 __func__);
1019 return NULL;
1020 }
1021 *(u32*)vaddr = value;
1022
1023 for_each_sg(sgl, sg, sg_len, i) {
1024 dma_addr_t dest = sg_dma_address(sg);
1025 size_t len = sg_dma_len(sg);
1026
1027 dev_vdbg(chan2dev(chan), "%s: d%pad, l0x%zx\n",
1028 __func__, &dest, len);
1029
1030 if (!is_dma_fill_aligned(chan->device, dest, 0, len)) {
1031 dev_err(chan2dev(chan), "%s: buffer is not aligned\n",
1032 __func__);
1033 goto err_put_desc;
1034 }
1035
1036 desc = atc_create_memset_desc(chan, paddr, dest, len);
1037 if (!desc)
1038 goto err_put_desc;
1039
1040 atc_desc_chain(&first, &prev, desc);
1041
1042 total_len += len;
1043 }
1044
1045 /*
1046 * Only set the buffer pointers on the last descriptor to
1047 * avoid free'ing while we have our transfer still going
1048 */
1049 desc->memset_paddr = paddr;
1050 desc->memset_vaddr = vaddr;
1051 desc->memset_buffer = true;
1052
1053 first->txd.cookie = -EBUSY;
1054 first->total_len = total_len;
1055
1056 /* set end-of-link on the descriptor */
1057 set_desc_eol(desc);
1058
1059 first->txd.flags = flags;
1060
1061 return &first->txd;
1062
1063 err_put_desc:
1064 atc_desc_put(atchan, first);
1065 return NULL;
1066 }
1067
1068 /**
1069 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
1070 * @chan: DMA channel
1071 * @sgl: scatterlist to transfer to/from
1072 * @sg_len: number of entries in @scatterlist
1073 * @direction: DMA direction
1074 * @flags: tx descriptor status flags
1075 * @context: transaction context (ignored)
1076 */
1077 static struct dma_async_tx_descriptor *
atc_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)1078 atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1079 unsigned int sg_len, enum dma_transfer_direction direction,
1080 unsigned long flags, void *context)
1081 {
1082 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1083 struct at_dma_slave *atslave = chan->private;
1084 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
1085 struct at_desc *first = NULL;
1086 struct at_desc *prev = NULL;
1087 u32 ctrla;
1088 u32 ctrlb;
1089 dma_addr_t reg;
1090 unsigned int reg_width;
1091 unsigned int mem_width;
1092 unsigned int i;
1093 struct scatterlist *sg;
1094 size_t total_len = 0;
1095
1096 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
1097 sg_len,
1098 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
1099 flags);
1100
1101 if (unlikely(!atslave || !sg_len)) {
1102 dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n");
1103 return NULL;
1104 }
1105
1106 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
1107 | ATC_DCSIZE(sconfig->dst_maxburst);
1108 ctrlb = ATC_IEN;
1109
1110 switch (direction) {
1111 case DMA_MEM_TO_DEV:
1112 reg_width = convert_buswidth(sconfig->dst_addr_width);
1113 ctrla |= ATC_DST_WIDTH(reg_width);
1114 ctrlb |= ATC_DST_ADDR_MODE_FIXED
1115 | ATC_SRC_ADDR_MODE_INCR
1116 | ATC_FC_MEM2PER
1117 | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if);
1118 reg = sconfig->dst_addr;
1119 for_each_sg(sgl, sg, sg_len, i) {
1120 struct at_desc *desc;
1121 u32 len;
1122 u32 mem;
1123
1124 desc = atc_desc_get(atchan);
1125 if (!desc)
1126 goto err_desc_get;
1127
1128 mem = sg_dma_address(sg);
1129 len = sg_dma_len(sg);
1130 if (unlikely(!len)) {
1131 dev_dbg(chan2dev(chan),
1132 "prep_slave_sg: sg(%d) data length is zero\n", i);
1133 goto err;
1134 }
1135 mem_width = 2;
1136 if (unlikely(mem & 3 || len & 3))
1137 mem_width = 0;
1138
1139 desc->lli.saddr = mem;
1140 desc->lli.daddr = reg;
1141 desc->lli.ctrla = ctrla
1142 | ATC_SRC_WIDTH(mem_width)
1143 | len >> mem_width;
1144 desc->lli.ctrlb = ctrlb;
1145 desc->len = len;
1146
1147 atc_desc_chain(&first, &prev, desc);
1148 total_len += len;
1149 }
1150 break;
1151 case DMA_DEV_TO_MEM:
1152 reg_width = convert_buswidth(sconfig->src_addr_width);
1153 ctrla |= ATC_SRC_WIDTH(reg_width);
1154 ctrlb |= ATC_DST_ADDR_MODE_INCR
1155 | ATC_SRC_ADDR_MODE_FIXED
1156 | ATC_FC_PER2MEM
1157 | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if);
1158
1159 reg = sconfig->src_addr;
1160 for_each_sg(sgl, sg, sg_len, i) {
1161 struct at_desc *desc;
1162 u32 len;
1163 u32 mem;
1164
1165 desc = atc_desc_get(atchan);
1166 if (!desc)
1167 goto err_desc_get;
1168
1169 mem = sg_dma_address(sg);
1170 len = sg_dma_len(sg);
1171 if (unlikely(!len)) {
1172 dev_dbg(chan2dev(chan),
1173 "prep_slave_sg: sg(%d) data length is zero\n", i);
1174 goto err;
1175 }
1176 mem_width = 2;
1177 if (unlikely(mem & 3 || len & 3))
1178 mem_width = 0;
1179
1180 desc->lli.saddr = reg;
1181 desc->lli.daddr = mem;
1182 desc->lli.ctrla = ctrla
1183 | ATC_DST_WIDTH(mem_width)
1184 | len >> reg_width;
1185 desc->lli.ctrlb = ctrlb;
1186 desc->len = len;
1187
1188 atc_desc_chain(&first, &prev, desc);
1189 total_len += len;
1190 }
1191 break;
1192 default:
1193 return NULL;
1194 }
1195
1196 /* set end-of-link to the last link descriptor of list*/
1197 set_desc_eol(prev);
1198
1199 /* First descriptor of the chain embedds additional information */
1200 first->txd.cookie = -EBUSY;
1201 first->total_len = total_len;
1202
1203 /* first link descriptor of list is responsible of flags */
1204 first->txd.flags = flags; /* client is in control of this ack */
1205
1206 return &first->txd;
1207
1208 err_desc_get:
1209 dev_err(chan2dev(chan), "not enough descriptors available\n");
1210 err:
1211 atc_desc_put(atchan, first);
1212 return NULL;
1213 }
1214
1215 /**
1216 * atc_prep_dma_sg - prepare memory to memory scather-gather operation
1217 * @chan: the channel to prepare operation on
1218 * @dst_sg: destination scatterlist
1219 * @dst_nents: number of destination scatterlist entries
1220 * @src_sg: source scatterlist
1221 * @src_nents: number of source scatterlist entries
1222 * @flags: tx descriptor status flags
1223 */
1224 static struct dma_async_tx_descriptor *
atc_prep_dma_sg(struct dma_chan * chan,struct scatterlist * dst_sg,unsigned int dst_nents,struct scatterlist * src_sg,unsigned int src_nents,unsigned long flags)1225 atc_prep_dma_sg(struct dma_chan *chan,
1226 struct scatterlist *dst_sg, unsigned int dst_nents,
1227 struct scatterlist *src_sg, unsigned int src_nents,
1228 unsigned long flags)
1229 {
1230 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1231 struct at_desc *desc = NULL;
1232 struct at_desc *first = NULL;
1233 struct at_desc *prev = NULL;
1234 unsigned int src_width;
1235 unsigned int dst_width;
1236 size_t xfer_count;
1237 u32 ctrla;
1238 u32 ctrlb;
1239 size_t dst_len = 0, src_len = 0;
1240 dma_addr_t dst = 0, src = 0;
1241 size_t len = 0, total_len = 0;
1242
1243 if (unlikely(dst_nents == 0 || src_nents == 0))
1244 return NULL;
1245
1246 if (unlikely(dst_sg == NULL || src_sg == NULL))
1247 return NULL;
1248
1249 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
1250 | ATC_SRC_ADDR_MODE_INCR
1251 | ATC_DST_ADDR_MODE_INCR
1252 | ATC_FC_MEM2MEM;
1253
1254 /*
1255 * loop until there is either no more source or no more destination
1256 * scatterlist entry
1257 */
1258 while (true) {
1259
1260 /* prepare the next transfer */
1261 if (dst_len == 0) {
1262
1263 /* no more destination scatterlist entries */
1264 if (!dst_sg || !dst_nents)
1265 break;
1266
1267 dst = sg_dma_address(dst_sg);
1268 dst_len = sg_dma_len(dst_sg);
1269
1270 dst_sg = sg_next(dst_sg);
1271 dst_nents--;
1272 }
1273
1274 if (src_len == 0) {
1275
1276 /* no more source scatterlist entries */
1277 if (!src_sg || !src_nents)
1278 break;
1279
1280 src = sg_dma_address(src_sg);
1281 src_len = sg_dma_len(src_sg);
1282
1283 src_sg = sg_next(src_sg);
1284 src_nents--;
1285 }
1286
1287 len = min_t(size_t, src_len, dst_len);
1288 if (len == 0)
1289 continue;
1290
1291 /* take care for the alignment */
1292 src_width = dst_width = atc_get_xfer_width(src, dst, len);
1293
1294 ctrla = ATC_SRC_WIDTH(src_width) |
1295 ATC_DST_WIDTH(dst_width);
1296
1297 /*
1298 * The number of transfers to set up refer to the source width
1299 * that depends on the alignment.
1300 */
1301 xfer_count = len >> src_width;
1302 if (xfer_count > ATC_BTSIZE_MAX) {
1303 xfer_count = ATC_BTSIZE_MAX;
1304 len = ATC_BTSIZE_MAX << src_width;
1305 }
1306
1307 /* create the transfer */
1308 desc = atc_desc_get(atchan);
1309 if (!desc)
1310 goto err_desc_get;
1311
1312 desc->lli.saddr = src;
1313 desc->lli.daddr = dst;
1314 desc->lli.ctrla = ctrla | xfer_count;
1315 desc->lli.ctrlb = ctrlb;
1316
1317 desc->txd.cookie = 0;
1318 desc->len = len;
1319
1320 atc_desc_chain(&first, &prev, desc);
1321
1322 /* update the lengths and addresses for the next loop cycle */
1323 dst_len -= len;
1324 src_len -= len;
1325 dst += len;
1326 src += len;
1327
1328 total_len += len;
1329 }
1330
1331 /* First descriptor of the chain embedds additional information */
1332 first->txd.cookie = -EBUSY;
1333 first->total_len = total_len;
1334
1335 /* set end-of-link to the last link descriptor of list*/
1336 set_desc_eol(desc);
1337
1338 first->txd.flags = flags; /* client is in control of this ack */
1339
1340 return &first->txd;
1341
1342 err_desc_get:
1343 atc_desc_put(atchan, first);
1344 return NULL;
1345 }
1346
1347 /**
1348 * atc_dma_cyclic_check_values
1349 * Check for too big/unaligned periods and unaligned DMA buffer
1350 */
1351 static int
atc_dma_cyclic_check_values(unsigned int reg_width,dma_addr_t buf_addr,size_t period_len)1352 atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
1353 size_t period_len)
1354 {
1355 if (period_len > (ATC_BTSIZE_MAX << reg_width))
1356 goto err_out;
1357 if (unlikely(period_len & ((1 << reg_width) - 1)))
1358 goto err_out;
1359 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1360 goto err_out;
1361
1362 return 0;
1363
1364 err_out:
1365 return -EINVAL;
1366 }
1367
1368 /**
1369 * atc_dma_cyclic_fill_desc - Fill one period descriptor
1370 */
1371 static int
atc_dma_cyclic_fill_desc(struct dma_chan * chan,struct at_desc * desc,unsigned int period_index,dma_addr_t buf_addr,unsigned int reg_width,size_t period_len,enum dma_transfer_direction direction)1372 atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
1373 unsigned int period_index, dma_addr_t buf_addr,
1374 unsigned int reg_width, size_t period_len,
1375 enum dma_transfer_direction direction)
1376 {
1377 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1378 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
1379 u32 ctrla;
1380
1381 /* prepare common CRTLA value */
1382 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
1383 | ATC_DCSIZE(sconfig->dst_maxburst)
1384 | ATC_DST_WIDTH(reg_width)
1385 | ATC_SRC_WIDTH(reg_width)
1386 | period_len >> reg_width;
1387
1388 switch (direction) {
1389 case DMA_MEM_TO_DEV:
1390 desc->lli.saddr = buf_addr + (period_len * period_index);
1391 desc->lli.daddr = sconfig->dst_addr;
1392 desc->lli.ctrla = ctrla;
1393 desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
1394 | ATC_SRC_ADDR_MODE_INCR
1395 | ATC_FC_MEM2PER
1396 | ATC_SIF(atchan->mem_if)
1397 | ATC_DIF(atchan->per_if);
1398 desc->len = period_len;
1399 break;
1400
1401 case DMA_DEV_TO_MEM:
1402 desc->lli.saddr = sconfig->src_addr;
1403 desc->lli.daddr = buf_addr + (period_len * period_index);
1404 desc->lli.ctrla = ctrla;
1405 desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
1406 | ATC_SRC_ADDR_MODE_FIXED
1407 | ATC_FC_PER2MEM
1408 | ATC_SIF(atchan->per_if)
1409 | ATC_DIF(atchan->mem_if);
1410 desc->len = period_len;
1411 break;
1412
1413 default:
1414 return -EINVAL;
1415 }
1416
1417 return 0;
1418 }
1419
1420 /**
1421 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
1422 * @chan: the DMA channel to prepare
1423 * @buf_addr: physical DMA address where the buffer starts
1424 * @buf_len: total number of bytes for the entire buffer
1425 * @period_len: number of bytes for each period
1426 * @direction: transfer direction, to or from device
1427 * @flags: tx descriptor status flags
1428 */
1429 static struct dma_async_tx_descriptor *
atc_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)1430 atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1431 size_t period_len, enum dma_transfer_direction direction,
1432 unsigned long flags)
1433 {
1434 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1435 struct at_dma_slave *atslave = chan->private;
1436 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
1437 struct at_desc *first = NULL;
1438 struct at_desc *prev = NULL;
1439 unsigned long was_cyclic;
1440 unsigned int reg_width;
1441 unsigned int periods = buf_len / period_len;
1442 unsigned int i;
1443
1444 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@%pad - %d (%d/%d)\n",
1445 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
1446 &buf_addr,
1447 periods, buf_len, period_len);
1448
1449 if (unlikely(!atslave || !buf_len || !period_len)) {
1450 dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n");
1451 return NULL;
1452 }
1453
1454 was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status);
1455 if (was_cyclic) {
1456 dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n");
1457 return NULL;
1458 }
1459
1460 if (unlikely(!is_slave_direction(direction)))
1461 goto err_out;
1462
1463 if (sconfig->direction == DMA_MEM_TO_DEV)
1464 reg_width = convert_buswidth(sconfig->dst_addr_width);
1465 else
1466 reg_width = convert_buswidth(sconfig->src_addr_width);
1467
1468 /* Check for too big/unaligned periods and unaligned DMA buffer */
1469 if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len))
1470 goto err_out;
1471
1472 /* build cyclic linked list */
1473 for (i = 0; i < periods; i++) {
1474 struct at_desc *desc;
1475
1476 desc = atc_desc_get(atchan);
1477 if (!desc)
1478 goto err_desc_get;
1479
1480 if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
1481 reg_width, period_len, direction))
1482 goto err_desc_get;
1483
1484 atc_desc_chain(&first, &prev, desc);
1485 }
1486
1487 /* lets make a cyclic list */
1488 prev->lli.dscr = first->txd.phys;
1489
1490 /* First descriptor of the chain embedds additional information */
1491 first->txd.cookie = -EBUSY;
1492 first->total_len = buf_len;
1493
1494 return &first->txd;
1495
1496 err_desc_get:
1497 dev_err(chan2dev(chan), "not enough descriptors available\n");
1498 atc_desc_put(atchan, first);
1499 err_out:
1500 clear_bit(ATC_IS_CYCLIC, &atchan->status);
1501 return NULL;
1502 }
1503
atc_config(struct dma_chan * chan,struct dma_slave_config * sconfig)1504 static int atc_config(struct dma_chan *chan,
1505 struct dma_slave_config *sconfig)
1506 {
1507 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1508
1509 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1510
1511 /* Check if it is chan is configured for slave transfers */
1512 if (!chan->private)
1513 return -EINVAL;
1514
1515 memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
1516
1517 convert_burst(&atchan->dma_sconfig.src_maxburst);
1518 convert_burst(&atchan->dma_sconfig.dst_maxburst);
1519
1520 return 0;
1521 }
1522
atc_pause(struct dma_chan * chan)1523 static int atc_pause(struct dma_chan *chan)
1524 {
1525 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1526 struct at_dma *atdma = to_at_dma(chan->device);
1527 int chan_id = atchan->chan_common.chan_id;
1528 unsigned long flags;
1529
1530 LIST_HEAD(list);
1531
1532 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1533
1534 spin_lock_irqsave(&atchan->lock, flags);
1535
1536 dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
1537 set_bit(ATC_IS_PAUSED, &atchan->status);
1538
1539 spin_unlock_irqrestore(&atchan->lock, flags);
1540
1541 return 0;
1542 }
1543
atc_resume(struct dma_chan * chan)1544 static int atc_resume(struct dma_chan *chan)
1545 {
1546 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1547 struct at_dma *atdma = to_at_dma(chan->device);
1548 int chan_id = atchan->chan_common.chan_id;
1549 unsigned long flags;
1550
1551 LIST_HEAD(list);
1552
1553 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1554
1555 if (!atc_chan_is_paused(atchan))
1556 return 0;
1557
1558 spin_lock_irqsave(&atchan->lock, flags);
1559
1560 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
1561 clear_bit(ATC_IS_PAUSED, &atchan->status);
1562
1563 spin_unlock_irqrestore(&atchan->lock, flags);
1564
1565 return 0;
1566 }
1567
atc_terminate_all(struct dma_chan * chan)1568 static int atc_terminate_all(struct dma_chan *chan)
1569 {
1570 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1571 struct at_dma *atdma = to_at_dma(chan->device);
1572 int chan_id = atchan->chan_common.chan_id;
1573 struct at_desc *desc, *_desc;
1574 unsigned long flags;
1575
1576 LIST_HEAD(list);
1577
1578 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1579
1580 /*
1581 * This is only called when something went wrong elsewhere, so
1582 * we don't really care about the data. Just disable the
1583 * channel. We still have to poll the channel enable bit due
1584 * to AHB/HSB limitations.
1585 */
1586 spin_lock_irqsave(&atchan->lock, flags);
1587
1588 /* disabling channel: must also remove suspend state */
1589 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
1590
1591 /* confirm that this channel is disabled */
1592 while (dma_readl(atdma, CHSR) & atchan->mask)
1593 cpu_relax();
1594
1595 /* active_list entries will end up before queued entries */
1596 list_splice_init(&atchan->queue, &list);
1597 list_splice_init(&atchan->active_list, &list);
1598
1599 /* Flush all pending and queued descriptors */
1600 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1601 atc_chain_complete(atchan, desc);
1602
1603 clear_bit(ATC_IS_PAUSED, &atchan->status);
1604 /* if channel dedicated to cyclic operations, free it */
1605 clear_bit(ATC_IS_CYCLIC, &atchan->status);
1606
1607 spin_unlock_irqrestore(&atchan->lock, flags);
1608
1609 return 0;
1610 }
1611
1612 /**
1613 * atc_tx_status - poll for transaction completion
1614 * @chan: DMA channel
1615 * @cookie: transaction identifier to check status of
1616 * @txstate: if not %NULL updated with transaction state
1617 *
1618 * If @txstate is passed in, upon return it reflect the driver
1619 * internal state and can be used with dma_async_is_complete() to check
1620 * the status of multiple cookies without re-checking hardware state.
1621 */
1622 static enum dma_status
atc_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)1623 atc_tx_status(struct dma_chan *chan,
1624 dma_cookie_t cookie,
1625 struct dma_tx_state *txstate)
1626 {
1627 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1628 unsigned long flags;
1629 enum dma_status ret;
1630 int bytes = 0;
1631
1632 ret = dma_cookie_status(chan, cookie, txstate);
1633 if (ret == DMA_COMPLETE)
1634 return ret;
1635 /*
1636 * There's no point calculating the residue if there's
1637 * no txstate to store the value.
1638 */
1639 if (!txstate)
1640 return DMA_ERROR;
1641
1642 spin_lock_irqsave(&atchan->lock, flags);
1643
1644 /* Get number of bytes left in the active transactions */
1645 bytes = atc_get_bytes_left(chan, cookie);
1646
1647 spin_unlock_irqrestore(&atchan->lock, flags);
1648
1649 if (unlikely(bytes < 0)) {
1650 dev_vdbg(chan2dev(chan), "get residual bytes error\n");
1651 return DMA_ERROR;
1652 } else {
1653 dma_set_residue(txstate, bytes);
1654 }
1655
1656 dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n",
1657 ret, cookie, bytes);
1658
1659 return ret;
1660 }
1661
1662 /**
1663 * atc_issue_pending - try to finish work
1664 * @chan: target DMA channel
1665 */
atc_issue_pending(struct dma_chan * chan)1666 static void atc_issue_pending(struct dma_chan *chan)
1667 {
1668 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1669 unsigned long flags;
1670
1671 dev_vdbg(chan2dev(chan), "issue_pending\n");
1672
1673 /* Not needed for cyclic transfers */
1674 if (atc_chan_is_cyclic(atchan))
1675 return;
1676
1677 spin_lock_irqsave(&atchan->lock, flags);
1678 atc_advance_work(atchan);
1679 spin_unlock_irqrestore(&atchan->lock, flags);
1680 }
1681
1682 /**
1683 * atc_alloc_chan_resources - allocate resources for DMA channel
1684 * @chan: allocate descriptor resources for this channel
1685 * @client: current client requesting the channel be ready for requests
1686 *
1687 * return - the number of allocated descriptors
1688 */
atc_alloc_chan_resources(struct dma_chan * chan)1689 static int atc_alloc_chan_resources(struct dma_chan *chan)
1690 {
1691 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1692 struct at_dma *atdma = to_at_dma(chan->device);
1693 struct at_desc *desc;
1694 struct at_dma_slave *atslave;
1695 unsigned long flags;
1696 int i;
1697 u32 cfg;
1698 LIST_HEAD(tmp_list);
1699
1700 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1701
1702 /* ASSERT: channel is idle */
1703 if (atc_chan_is_enabled(atchan)) {
1704 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
1705 return -EIO;
1706 }
1707
1708 cfg = ATC_DEFAULT_CFG;
1709
1710 atslave = chan->private;
1711 if (atslave) {
1712 /*
1713 * We need controller-specific data to set up slave
1714 * transfers.
1715 */
1716 BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
1717
1718 /* if cfg configuration specified take it instead of default */
1719 if (atslave->cfg)
1720 cfg = atslave->cfg;
1721 }
1722
1723 /* have we already been set up?
1724 * reconfigure channel but no need to reallocate descriptors */
1725 if (!list_empty(&atchan->free_list))
1726 return atchan->descs_allocated;
1727
1728 /* Allocate initial pool of descriptors */
1729 for (i = 0; i < init_nr_desc_per_channel; i++) {
1730 desc = atc_alloc_descriptor(chan, GFP_KERNEL);
1731 if (!desc) {
1732 dev_err(atdma->dma_common.dev,
1733 "Only %d initial descriptors\n", i);
1734 break;
1735 }
1736 list_add_tail(&desc->desc_node, &tmp_list);
1737 }
1738
1739 spin_lock_irqsave(&atchan->lock, flags);
1740 atchan->descs_allocated = i;
1741 list_splice(&tmp_list, &atchan->free_list);
1742 dma_cookie_init(chan);
1743 spin_unlock_irqrestore(&atchan->lock, flags);
1744
1745 /* channel parameters */
1746 channel_writel(atchan, CFG, cfg);
1747
1748 dev_dbg(chan2dev(chan),
1749 "alloc_chan_resources: allocated %d descriptors\n",
1750 atchan->descs_allocated);
1751
1752 return atchan->descs_allocated;
1753 }
1754
1755 /**
1756 * atc_free_chan_resources - free all channel resources
1757 * @chan: DMA channel
1758 */
atc_free_chan_resources(struct dma_chan * chan)1759 static void atc_free_chan_resources(struct dma_chan *chan)
1760 {
1761 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1762 struct at_dma *atdma = to_at_dma(chan->device);
1763 struct at_desc *desc, *_desc;
1764 LIST_HEAD(list);
1765
1766 dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n",
1767 atchan->descs_allocated);
1768
1769 /* ASSERT: channel is idle */
1770 BUG_ON(!list_empty(&atchan->active_list));
1771 BUG_ON(!list_empty(&atchan->queue));
1772 BUG_ON(atc_chan_is_enabled(atchan));
1773
1774 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
1775 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1776 list_del(&desc->desc_node);
1777 /* free link descriptor */
1778 dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys);
1779 }
1780 list_splice_init(&atchan->free_list, &list);
1781 atchan->descs_allocated = 0;
1782 atchan->status = 0;
1783
1784 /*
1785 * Free atslave allocated in at_dma_xlate()
1786 */
1787 kfree(chan->private);
1788 chan->private = NULL;
1789
1790 dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
1791 }
1792
1793 #ifdef CONFIG_OF
at_dma_filter(struct dma_chan * chan,void * slave)1794 static bool at_dma_filter(struct dma_chan *chan, void *slave)
1795 {
1796 struct at_dma_slave *atslave = slave;
1797
1798 if (atslave->dma_dev == chan->device->dev) {
1799 chan->private = atslave;
1800 return true;
1801 } else {
1802 return false;
1803 }
1804 }
1805
at_dma_xlate(struct of_phandle_args * dma_spec,struct of_dma * of_dma)1806 static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1807 struct of_dma *of_dma)
1808 {
1809 struct dma_chan *chan;
1810 struct at_dma_chan *atchan;
1811 struct at_dma_slave *atslave;
1812 dma_cap_mask_t mask;
1813 unsigned int per_id;
1814 struct platform_device *dmac_pdev;
1815
1816 if (dma_spec->args_count != 2)
1817 return NULL;
1818
1819 dmac_pdev = of_find_device_by_node(dma_spec->np);
1820 if (!dmac_pdev)
1821 return NULL;
1822
1823 dma_cap_zero(mask);
1824 dma_cap_set(DMA_SLAVE, mask);
1825
1826 atslave = kzalloc(sizeof(*atslave), GFP_KERNEL);
1827 if (!atslave)
1828 return NULL;
1829
1830 atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW;
1831 /*
1832 * We can fill both SRC_PER and DST_PER, one of these fields will be
1833 * ignored depending on DMA transfer direction.
1834 */
1835 per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK;
1836 atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id)
1837 | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id);
1838 /*
1839 * We have to translate the value we get from the device tree since
1840 * the half FIFO configuration value had to be 0 to keep backward
1841 * compatibility.
1842 */
1843 switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) {
1844 case AT91_DMA_CFG_FIFOCFG_ALAP:
1845 atslave->cfg |= ATC_FIFOCFG_LARGESTBURST;
1846 break;
1847 case AT91_DMA_CFG_FIFOCFG_ASAP:
1848 atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE;
1849 break;
1850 case AT91_DMA_CFG_FIFOCFG_HALF:
1851 default:
1852 atslave->cfg |= ATC_FIFOCFG_HALFFIFO;
1853 }
1854 atslave->dma_dev = &dmac_pdev->dev;
1855
1856 chan = dma_request_channel(mask, at_dma_filter, atslave);
1857 if (!chan)
1858 return NULL;
1859
1860 atchan = to_at_dma_chan(chan);
1861 atchan->per_if = dma_spec->args[0] & 0xff;
1862 atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff;
1863
1864 return chan;
1865 }
1866 #else
at_dma_xlate(struct of_phandle_args * dma_spec,struct of_dma * of_dma)1867 static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1868 struct of_dma *of_dma)
1869 {
1870 return NULL;
1871 }
1872 #endif
1873
1874 /*-- Module Management -----------------------------------------------*/
1875
1876 /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1877 static struct at_dma_platform_data at91sam9rl_config = {
1878 .nr_channels = 2,
1879 };
1880 static struct at_dma_platform_data at91sam9g45_config = {
1881 .nr_channels = 8,
1882 };
1883
1884 #if defined(CONFIG_OF)
1885 static const struct of_device_id atmel_dma_dt_ids[] = {
1886 {
1887 .compatible = "atmel,at91sam9rl-dma",
1888 .data = &at91sam9rl_config,
1889 }, {
1890 .compatible = "atmel,at91sam9g45-dma",
1891 .data = &at91sam9g45_config,
1892 }, {
1893 /* sentinel */
1894 }
1895 };
1896
1897 MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids);
1898 #endif
1899
1900 static const struct platform_device_id atdma_devtypes[] = {
1901 {
1902 .name = "at91sam9rl_dma",
1903 .driver_data = (unsigned long) &at91sam9rl_config,
1904 }, {
1905 .name = "at91sam9g45_dma",
1906 .driver_data = (unsigned long) &at91sam9g45_config,
1907 }, {
1908 /* sentinel */
1909 }
1910 };
1911
at_dma_get_driver_data(struct platform_device * pdev)1912 static inline const struct at_dma_platform_data * __init at_dma_get_driver_data(
1913 struct platform_device *pdev)
1914 {
1915 if (pdev->dev.of_node) {
1916 const struct of_device_id *match;
1917 match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
1918 if (match == NULL)
1919 return NULL;
1920 return match->data;
1921 }
1922 return (struct at_dma_platform_data *)
1923 platform_get_device_id(pdev)->driver_data;
1924 }
1925
1926 /**
1927 * at_dma_off - disable DMA controller
1928 * @atdma: the Atmel HDAMC device
1929 */
at_dma_off(struct at_dma * atdma)1930 static void at_dma_off(struct at_dma *atdma)
1931 {
1932 dma_writel(atdma, EN, 0);
1933
1934 /* disable all interrupts */
1935 dma_writel(atdma, EBCIDR, -1L);
1936
1937 /* confirm that all channels are disabled */
1938 while (dma_readl(atdma, CHSR) & atdma->all_chan_mask)
1939 cpu_relax();
1940 }
1941
at_dma_probe(struct platform_device * pdev)1942 static int __init at_dma_probe(struct platform_device *pdev)
1943 {
1944 struct resource *io;
1945 struct at_dma *atdma;
1946 size_t size;
1947 int irq;
1948 int err;
1949 int i;
1950 const struct at_dma_platform_data *plat_dat;
1951
1952 /* setup platform data for each SoC */
1953 dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
1954 dma_cap_set(DMA_SG, at91sam9rl_config.cap_mask);
1955 dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask);
1956 dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
1957 dma_cap_set(DMA_MEMSET, at91sam9g45_config.cap_mask);
1958 dma_cap_set(DMA_MEMSET_SG, at91sam9g45_config.cap_mask);
1959 dma_cap_set(DMA_PRIVATE, at91sam9g45_config.cap_mask);
1960 dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
1961 dma_cap_set(DMA_SG, at91sam9g45_config.cap_mask);
1962
1963 /* get DMA parameters from controller type */
1964 plat_dat = at_dma_get_driver_data(pdev);
1965 if (!plat_dat)
1966 return -ENODEV;
1967
1968 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1969 if (!io)
1970 return -EINVAL;
1971
1972 irq = platform_get_irq(pdev, 0);
1973 if (irq < 0)
1974 return irq;
1975
1976 size = sizeof(struct at_dma);
1977 size += plat_dat->nr_channels * sizeof(struct at_dma_chan);
1978 atdma = kzalloc(size, GFP_KERNEL);
1979 if (!atdma)
1980 return -ENOMEM;
1981
1982 /* discover transaction capabilities */
1983 atdma->dma_common.cap_mask = plat_dat->cap_mask;
1984 atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
1985
1986 size = resource_size(io);
1987 if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
1988 err = -EBUSY;
1989 goto err_kfree;
1990 }
1991
1992 atdma->regs = ioremap(io->start, size);
1993 if (!atdma->regs) {
1994 err = -ENOMEM;
1995 goto err_release_r;
1996 }
1997
1998 atdma->clk = clk_get(&pdev->dev, "dma_clk");
1999 if (IS_ERR(atdma->clk)) {
2000 err = PTR_ERR(atdma->clk);
2001 goto err_clk;
2002 }
2003 err = clk_prepare_enable(atdma->clk);
2004 if (err)
2005 goto err_clk_prepare;
2006
2007 /* force dma off, just in case */
2008 at_dma_off(atdma);
2009
2010 err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma);
2011 if (err)
2012 goto err_irq;
2013
2014 platform_set_drvdata(pdev, atdma);
2015
2016 /* create a pool of consistent memory blocks for hardware descriptors */
2017 atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool",
2018 &pdev->dev, sizeof(struct at_desc),
2019 4 /* word alignment */, 0);
2020 if (!atdma->dma_desc_pool) {
2021 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
2022 err = -ENOMEM;
2023 goto err_desc_pool_create;
2024 }
2025
2026 /* create a pool of consistent memory blocks for memset blocks */
2027 atdma->memset_pool = dma_pool_create("at_hdmac_memset_pool",
2028 &pdev->dev, sizeof(int), 4, 0);
2029 if (!atdma->memset_pool) {
2030 dev_err(&pdev->dev, "No memory for memset dma pool\n");
2031 err = -ENOMEM;
2032 goto err_memset_pool_create;
2033 }
2034
2035 /* clear any pending interrupt */
2036 while (dma_readl(atdma, EBCISR))
2037 cpu_relax();
2038
2039 /* initialize channels related values */
2040 INIT_LIST_HEAD(&atdma->dma_common.channels);
2041 for (i = 0; i < plat_dat->nr_channels; i++) {
2042 struct at_dma_chan *atchan = &atdma->chan[i];
2043
2044 atchan->mem_if = AT_DMA_MEM_IF;
2045 atchan->per_if = AT_DMA_PER_IF;
2046 atchan->chan_common.device = &atdma->dma_common;
2047 dma_cookie_init(&atchan->chan_common);
2048 list_add_tail(&atchan->chan_common.device_node,
2049 &atdma->dma_common.channels);
2050
2051 atchan->ch_regs = atdma->regs + ch_regs(i);
2052 spin_lock_init(&atchan->lock);
2053 atchan->mask = 1 << i;
2054
2055 INIT_LIST_HEAD(&atchan->active_list);
2056 INIT_LIST_HEAD(&atchan->queue);
2057 INIT_LIST_HEAD(&atchan->free_list);
2058
2059 tasklet_init(&atchan->tasklet, atc_tasklet,
2060 (unsigned long)atchan);
2061 atc_enable_chan_irq(atdma, i);
2062 }
2063
2064 /* set base routines */
2065 atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources;
2066 atdma->dma_common.device_free_chan_resources = atc_free_chan_resources;
2067 atdma->dma_common.device_tx_status = atc_tx_status;
2068 atdma->dma_common.device_issue_pending = atc_issue_pending;
2069 atdma->dma_common.dev = &pdev->dev;
2070
2071 /* set prep routines based on capability */
2072 if (dma_has_cap(DMA_INTERLEAVE, atdma->dma_common.cap_mask))
2073 atdma->dma_common.device_prep_interleaved_dma = atc_prep_dma_interleaved;
2074
2075 if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
2076 atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
2077
2078 if (dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask)) {
2079 atdma->dma_common.device_prep_dma_memset = atc_prep_dma_memset;
2080 atdma->dma_common.device_prep_dma_memset_sg = atc_prep_dma_memset_sg;
2081 atdma->dma_common.fill_align = DMAENGINE_ALIGN_4_BYTES;
2082 }
2083
2084 if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
2085 atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
2086 /* controller can do slave DMA: can trigger cyclic transfers */
2087 dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask);
2088 atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic;
2089 atdma->dma_common.device_config = atc_config;
2090 atdma->dma_common.device_pause = atc_pause;
2091 atdma->dma_common.device_resume = atc_resume;
2092 atdma->dma_common.device_terminate_all = atc_terminate_all;
2093 atdma->dma_common.src_addr_widths = ATC_DMA_BUSWIDTHS;
2094 atdma->dma_common.dst_addr_widths = ATC_DMA_BUSWIDTHS;
2095 atdma->dma_common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2096 atdma->dma_common.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2097 }
2098
2099 if (dma_has_cap(DMA_SG, atdma->dma_common.cap_mask))
2100 atdma->dma_common.device_prep_dma_sg = atc_prep_dma_sg;
2101
2102 dma_writel(atdma, EN, AT_DMA_ENABLE);
2103
2104 dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s%s), %d channels\n",
2105 dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
2106 dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask) ? "set " : "",
2107 dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
2108 dma_has_cap(DMA_SG, atdma->dma_common.cap_mask) ? "sg-cpy " : "",
2109 plat_dat->nr_channels);
2110
2111 dma_async_device_register(&atdma->dma_common);
2112
2113 /*
2114 * Do not return an error if the dmac node is not present in order to
2115 * not break the existing way of requesting channel with
2116 * dma_request_channel().
2117 */
2118 if (pdev->dev.of_node) {
2119 err = of_dma_controller_register(pdev->dev.of_node,
2120 at_dma_xlate, atdma);
2121 if (err) {
2122 dev_err(&pdev->dev, "could not register of_dma_controller\n");
2123 goto err_of_dma_controller_register;
2124 }
2125 }
2126
2127 return 0;
2128
2129 err_of_dma_controller_register:
2130 dma_async_device_unregister(&atdma->dma_common);
2131 dma_pool_destroy(atdma->memset_pool);
2132 err_memset_pool_create:
2133 dma_pool_destroy(atdma->dma_desc_pool);
2134 err_desc_pool_create:
2135 free_irq(platform_get_irq(pdev, 0), atdma);
2136 err_irq:
2137 clk_disable_unprepare(atdma->clk);
2138 err_clk_prepare:
2139 clk_put(atdma->clk);
2140 err_clk:
2141 iounmap(atdma->regs);
2142 atdma->regs = NULL;
2143 err_release_r:
2144 release_mem_region(io->start, size);
2145 err_kfree:
2146 kfree(atdma);
2147 return err;
2148 }
2149
at_dma_remove(struct platform_device * pdev)2150 static int at_dma_remove(struct platform_device *pdev)
2151 {
2152 struct at_dma *atdma = platform_get_drvdata(pdev);
2153 struct dma_chan *chan, *_chan;
2154 struct resource *io;
2155
2156 at_dma_off(atdma);
2157 if (pdev->dev.of_node)
2158 of_dma_controller_free(pdev->dev.of_node);
2159 dma_async_device_unregister(&atdma->dma_common);
2160
2161 dma_pool_destroy(atdma->memset_pool);
2162 dma_pool_destroy(atdma->dma_desc_pool);
2163 free_irq(platform_get_irq(pdev, 0), atdma);
2164
2165 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
2166 device_node) {
2167 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2168
2169 /* Disable interrupts */
2170 atc_disable_chan_irq(atdma, chan->chan_id);
2171
2172 tasklet_kill(&atchan->tasklet);
2173 list_del(&chan->device_node);
2174 }
2175
2176 clk_disable_unprepare(atdma->clk);
2177 clk_put(atdma->clk);
2178
2179 iounmap(atdma->regs);
2180 atdma->regs = NULL;
2181
2182 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2183 release_mem_region(io->start, resource_size(io));
2184
2185 kfree(atdma);
2186
2187 return 0;
2188 }
2189
at_dma_shutdown(struct platform_device * pdev)2190 static void at_dma_shutdown(struct platform_device *pdev)
2191 {
2192 struct at_dma *atdma = platform_get_drvdata(pdev);
2193
2194 at_dma_off(platform_get_drvdata(pdev));
2195 clk_disable_unprepare(atdma->clk);
2196 }
2197
at_dma_prepare(struct device * dev)2198 static int at_dma_prepare(struct device *dev)
2199 {
2200 struct platform_device *pdev = to_platform_device(dev);
2201 struct at_dma *atdma = platform_get_drvdata(pdev);
2202 struct dma_chan *chan, *_chan;
2203
2204 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
2205 device_node) {
2206 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2207 /* wait for transaction completion (except in cyclic case) */
2208 if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan))
2209 return -EAGAIN;
2210 }
2211 return 0;
2212 }
2213
atc_suspend_cyclic(struct at_dma_chan * atchan)2214 static void atc_suspend_cyclic(struct at_dma_chan *atchan)
2215 {
2216 struct dma_chan *chan = &atchan->chan_common;
2217
2218 /* Channel should be paused by user
2219 * do it anyway even if it is not done already */
2220 if (!atc_chan_is_paused(atchan)) {
2221 dev_warn(chan2dev(chan),
2222 "cyclic channel not paused, should be done by channel user\n");
2223 atc_pause(chan);
2224 }
2225
2226 /* now preserve additional data for cyclic operations */
2227 /* next descriptor address in the cyclic list */
2228 atchan->save_dscr = channel_readl(atchan, DSCR);
2229
2230 vdbg_dump_regs(atchan);
2231 }
2232
at_dma_suspend_noirq(struct device * dev)2233 static int at_dma_suspend_noirq(struct device *dev)
2234 {
2235 struct platform_device *pdev = to_platform_device(dev);
2236 struct at_dma *atdma = platform_get_drvdata(pdev);
2237 struct dma_chan *chan, *_chan;
2238
2239 /* preserve data */
2240 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
2241 device_node) {
2242 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2243
2244 if (atc_chan_is_cyclic(atchan))
2245 atc_suspend_cyclic(atchan);
2246 atchan->save_cfg = channel_readl(atchan, CFG);
2247 }
2248 atdma->save_imr = dma_readl(atdma, EBCIMR);
2249
2250 /* disable DMA controller */
2251 at_dma_off(atdma);
2252 clk_disable_unprepare(atdma->clk);
2253 return 0;
2254 }
2255
atc_resume_cyclic(struct at_dma_chan * atchan)2256 static void atc_resume_cyclic(struct at_dma_chan *atchan)
2257 {
2258 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
2259
2260 /* restore channel status for cyclic descriptors list:
2261 * next descriptor in the cyclic list at the time of suspend */
2262 channel_writel(atchan, SADDR, 0);
2263 channel_writel(atchan, DADDR, 0);
2264 channel_writel(atchan, CTRLA, 0);
2265 channel_writel(atchan, CTRLB, 0);
2266 channel_writel(atchan, DSCR, atchan->save_dscr);
2267 dma_writel(atdma, CHER, atchan->mask);
2268
2269 /* channel pause status should be removed by channel user
2270 * We cannot take the initiative to do it here */
2271
2272 vdbg_dump_regs(atchan);
2273 }
2274
at_dma_resume_noirq(struct device * dev)2275 static int at_dma_resume_noirq(struct device *dev)
2276 {
2277 struct platform_device *pdev = to_platform_device(dev);
2278 struct at_dma *atdma = platform_get_drvdata(pdev);
2279 struct dma_chan *chan, *_chan;
2280
2281 /* bring back DMA controller */
2282 clk_prepare_enable(atdma->clk);
2283 dma_writel(atdma, EN, AT_DMA_ENABLE);
2284
2285 /* clear any pending interrupt */
2286 while (dma_readl(atdma, EBCISR))
2287 cpu_relax();
2288
2289 /* restore saved data */
2290 dma_writel(atdma, EBCIER, atdma->save_imr);
2291 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
2292 device_node) {
2293 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2294
2295 channel_writel(atchan, CFG, atchan->save_cfg);
2296 if (atc_chan_is_cyclic(atchan))
2297 atc_resume_cyclic(atchan);
2298 }
2299 return 0;
2300 }
2301
2302 static const struct dev_pm_ops at_dma_dev_pm_ops = {
2303 .prepare = at_dma_prepare,
2304 .suspend_noirq = at_dma_suspend_noirq,
2305 .resume_noirq = at_dma_resume_noirq,
2306 };
2307
2308 static struct platform_driver at_dma_driver = {
2309 .remove = at_dma_remove,
2310 .shutdown = at_dma_shutdown,
2311 .id_table = atdma_devtypes,
2312 .driver = {
2313 .name = "at_hdmac",
2314 .pm = &at_dma_dev_pm_ops,
2315 .of_match_table = of_match_ptr(atmel_dma_dt_ids),
2316 },
2317 };
2318
at_dma_init(void)2319 static int __init at_dma_init(void)
2320 {
2321 return platform_driver_probe(&at_dma_driver, at_dma_probe);
2322 }
2323 subsys_initcall(at_dma_init);
2324
at_dma_exit(void)2325 static void __exit at_dma_exit(void)
2326 {
2327 platform_driver_unregister(&at_dma_driver);
2328 }
2329 module_exit(at_dma_exit);
2330
2331 MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
2332 MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
2333 MODULE_LICENSE("GPL");
2334 MODULE_ALIAS("platform:at_hdmac");
2335