1 /*
2 * driver/dma/coh901318.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h> /* printk() */
13 #include <linux/fs.h> /* everything... */
14 #include <linux/scatterlist.h>
15 #include <linux/slab.h> /* kmalloc() */
16 #include <linux/dmaengine.h>
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/irqreturn.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/uaccess.h>
23 #include <linux/debugfs.h>
24 #include <linux/platform_data/dma-coh901318.h>
25 #include <linux/of_dma.h>
26
27 #include "coh901318.h"
28 #include "dmaengine.h"
29
30 #define COH901318_MOD32_MASK (0x1F)
31 #define COH901318_WORD_MASK (0xFFFFFFFF)
32 /* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
33 #define COH901318_INT_STATUS1 (0x0000)
34 #define COH901318_INT_STATUS2 (0x0004)
35 /* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
36 #define COH901318_TC_INT_STATUS1 (0x0008)
37 #define COH901318_TC_INT_STATUS2 (0x000C)
38 /* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
39 #define COH901318_TC_INT_CLEAR1 (0x0010)
40 #define COH901318_TC_INT_CLEAR2 (0x0014)
41 /* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
42 #define COH901318_RAW_TC_INT_STATUS1 (0x0018)
43 #define COH901318_RAW_TC_INT_STATUS2 (0x001C)
44 /* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
45 #define COH901318_BE_INT_STATUS1 (0x0020)
46 #define COH901318_BE_INT_STATUS2 (0x0024)
47 /* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
48 #define COH901318_BE_INT_CLEAR1 (0x0028)
49 #define COH901318_BE_INT_CLEAR2 (0x002C)
50 /* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
51 #define COH901318_RAW_BE_INT_STATUS1 (0x0030)
52 #define COH901318_RAW_BE_INT_STATUS2 (0x0034)
53
54 /*
55 * CX_CFG - Channel Configuration Registers 32bit (R/W)
56 */
57 #define COH901318_CX_CFG (0x0100)
58 #define COH901318_CX_CFG_SPACING (0x04)
59 /* Channel enable activates tha dma job */
60 #define COH901318_CX_CFG_CH_ENABLE (0x00000001)
61 #define COH901318_CX_CFG_CH_DISABLE (0x00000000)
62 /* Request Mode */
63 #define COH901318_CX_CFG_RM_MASK (0x00000006)
64 #define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
65 #define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
66 #define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
67 #define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
68 #define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
69 /* Linked channel request field. RM must == 11 */
70 #define COH901318_CX_CFG_LCRF_SHIFT 3
71 #define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
72 #define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
73 /* Terminal Counter Interrupt Request Mask */
74 #define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
75 #define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
76 /* Bus Error interrupt Mask */
77 #define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
78 #define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
79
80 /*
81 * CX_STAT - Channel Status Registers 32bit (R/-)
82 */
83 #define COH901318_CX_STAT (0x0200)
84 #define COH901318_CX_STAT_SPACING (0x04)
85 #define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
86 #define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
87 #define COH901318_CX_STAT_ACTIVE (0x00000002)
88 #define COH901318_CX_STAT_ENABLED (0x00000001)
89
90 /*
91 * CX_CTRL - Channel Control Registers 32bit (R/W)
92 */
93 #define COH901318_CX_CTRL (0x0400)
94 #define COH901318_CX_CTRL_SPACING (0x10)
95 /* Transfer Count Enable */
96 #define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
97 #define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
98 /* Transfer Count Value 0 - 4095 */
99 #define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
100 /* Burst count */
101 #define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
102 #define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
103 #define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
104 #define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
105 #define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
106 #define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
107 #define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
108 #define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
109 #define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
110 /* Source bus size */
111 #define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
112 #define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
113 #define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
114 #define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
115 /* Source address increment */
116 #define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
117 #define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
118 /* Destination Bus Size */
119 #define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
120 #define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
121 #define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
122 #define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
123 /* Destination address increment */
124 #define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
125 #define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
126 /* Master Mode (Master2 is only connected to MSL) */
127 #define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
128 #define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
129 #define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
130 #define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
131 #define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
132 /* Terminal Count flag to PER enable */
133 #define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
134 #define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
135 /* Terminal Count flags to CPU enable */
136 #define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
137 #define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
138 /* Hand shake to peripheral */
139 #define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
140 #define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
141 #define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
142 #define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
143 /* DMA mode */
144 #define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
145 #define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
146 #define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
147 #define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
148 /* Primary Request Data Destination */
149 #define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
150 #define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
151 #define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
152
153 /*
154 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
155 */
156 #define COH901318_CX_SRC_ADDR (0x0404)
157 #define COH901318_CX_SRC_ADDR_SPACING (0x10)
158
159 /*
160 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
161 */
162 #define COH901318_CX_DST_ADDR (0x0408)
163 #define COH901318_CX_DST_ADDR_SPACING (0x10)
164
165 /*
166 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
167 */
168 #define COH901318_CX_LNK_ADDR (0x040C)
169 #define COH901318_CX_LNK_ADDR_SPACING (0x10)
170 #define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
171
172 /**
173 * struct coh901318_params - parameters for DMAC configuration
174 * @config: DMA config register
175 * @ctrl_lli_last: DMA control register for the last lli in the list
176 * @ctrl_lli: DMA control register for an lli
177 * @ctrl_lli_chained: DMA control register for a chained lli
178 */
179 struct coh901318_params {
180 u32 config;
181 u32 ctrl_lli_last;
182 u32 ctrl_lli;
183 u32 ctrl_lli_chained;
184 };
185
186 /**
187 * struct coh_dma_channel - dma channel base
188 * @name: ascii name of dma channel
189 * @number: channel id number
190 * @desc_nbr_max: number of preallocated descriptors
191 * @priority_high: prio of channel, 0 low otherwise high.
192 * @param: configuration parameters
193 */
194 struct coh_dma_channel {
195 const char name[32];
196 const int number;
197 const int desc_nbr_max;
198 const int priority_high;
199 const struct coh901318_params param;
200 };
201
202 /**
203 * struct powersave - DMA power save structure
204 * @lock: lock protecting data in this struct
205 * @started_channels: bit mask indicating active dma channels
206 */
207 struct powersave {
208 spinlock_t lock;
209 u64 started_channels;
210 };
211
212 /* points out all dma slave channels.
213 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
214 * Select all channels from A to B, end of list is marked with -1,-1
215 */
216 static int dma_slave_channels[] = {
217 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
218 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
219
220 /* points out all dma memcpy channels. */
221 static int dma_memcpy_channels[] = {
222 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
223
224 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
225 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
226 COH901318_CX_CFG_LCR_DISABLE | \
227 COH901318_CX_CFG_TC_IRQ_ENABLE | \
228 COH901318_CX_CFG_BE_IRQ_ENABLE)
229 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
230 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
231 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
232 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
233 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
234 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
235 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
236 COH901318_CX_CTRL_TCP_DISABLE | \
237 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
238 COH901318_CX_CTRL_HSP_DISABLE | \
239 COH901318_CX_CTRL_HSS_DISABLE | \
240 COH901318_CX_CTRL_DDMA_LEGACY | \
241 COH901318_CX_CTRL_PRDD_SOURCE)
242 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
243 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
244 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
245 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
246 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
247 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
248 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
249 COH901318_CX_CTRL_TCP_DISABLE | \
250 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
251 COH901318_CX_CTRL_HSP_DISABLE | \
252 COH901318_CX_CTRL_HSS_DISABLE | \
253 COH901318_CX_CTRL_DDMA_LEGACY | \
254 COH901318_CX_CTRL_PRDD_SOURCE)
255 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
256 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
257 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
258 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
259 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
260 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
261 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
262 COH901318_CX_CTRL_TCP_DISABLE | \
263 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
264 COH901318_CX_CTRL_HSP_DISABLE | \
265 COH901318_CX_CTRL_HSS_DISABLE | \
266 COH901318_CX_CTRL_DDMA_LEGACY | \
267 COH901318_CX_CTRL_PRDD_SOURCE)
268
269 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
270 {
271 .number = U300_DMA_MSL_TX_0,
272 .name = "MSL TX 0",
273 .priority_high = 0,
274 },
275 {
276 .number = U300_DMA_MSL_TX_1,
277 .name = "MSL TX 1",
278 .priority_high = 0,
279 .param.config = COH901318_CX_CFG_CH_DISABLE |
280 COH901318_CX_CFG_LCR_DISABLE |
281 COH901318_CX_CFG_TC_IRQ_ENABLE |
282 COH901318_CX_CFG_BE_IRQ_ENABLE,
283 .param.ctrl_lli_chained = 0 |
284 COH901318_CX_CTRL_TC_ENABLE |
285 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
286 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
287 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
288 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
289 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
290 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
291 COH901318_CX_CTRL_TCP_DISABLE |
292 COH901318_CX_CTRL_TC_IRQ_DISABLE |
293 COH901318_CX_CTRL_HSP_ENABLE |
294 COH901318_CX_CTRL_HSS_DISABLE |
295 COH901318_CX_CTRL_DDMA_LEGACY |
296 COH901318_CX_CTRL_PRDD_SOURCE,
297 .param.ctrl_lli = 0 |
298 COH901318_CX_CTRL_TC_ENABLE |
299 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
300 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
301 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
302 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
303 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
304 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
305 COH901318_CX_CTRL_TCP_ENABLE |
306 COH901318_CX_CTRL_TC_IRQ_DISABLE |
307 COH901318_CX_CTRL_HSP_ENABLE |
308 COH901318_CX_CTRL_HSS_DISABLE |
309 COH901318_CX_CTRL_DDMA_LEGACY |
310 COH901318_CX_CTRL_PRDD_SOURCE,
311 .param.ctrl_lli_last = 0 |
312 COH901318_CX_CTRL_TC_ENABLE |
313 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
314 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
315 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
316 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
317 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
318 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
319 COH901318_CX_CTRL_TCP_ENABLE |
320 COH901318_CX_CTRL_TC_IRQ_ENABLE |
321 COH901318_CX_CTRL_HSP_ENABLE |
322 COH901318_CX_CTRL_HSS_DISABLE |
323 COH901318_CX_CTRL_DDMA_LEGACY |
324 COH901318_CX_CTRL_PRDD_SOURCE,
325 },
326 {
327 .number = U300_DMA_MSL_TX_2,
328 .name = "MSL TX 2",
329 .priority_high = 0,
330 .param.config = COH901318_CX_CFG_CH_DISABLE |
331 COH901318_CX_CFG_LCR_DISABLE |
332 COH901318_CX_CFG_TC_IRQ_ENABLE |
333 COH901318_CX_CFG_BE_IRQ_ENABLE,
334 .param.ctrl_lli_chained = 0 |
335 COH901318_CX_CTRL_TC_ENABLE |
336 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
337 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
338 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
339 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
340 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
341 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
342 COH901318_CX_CTRL_TCP_DISABLE |
343 COH901318_CX_CTRL_TC_IRQ_DISABLE |
344 COH901318_CX_CTRL_HSP_ENABLE |
345 COH901318_CX_CTRL_HSS_DISABLE |
346 COH901318_CX_CTRL_DDMA_LEGACY |
347 COH901318_CX_CTRL_PRDD_SOURCE,
348 .param.ctrl_lli = 0 |
349 COH901318_CX_CTRL_TC_ENABLE |
350 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
351 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
352 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
353 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
354 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
355 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
356 COH901318_CX_CTRL_TCP_ENABLE |
357 COH901318_CX_CTRL_TC_IRQ_DISABLE |
358 COH901318_CX_CTRL_HSP_ENABLE |
359 COH901318_CX_CTRL_HSS_DISABLE |
360 COH901318_CX_CTRL_DDMA_LEGACY |
361 COH901318_CX_CTRL_PRDD_SOURCE,
362 .param.ctrl_lli_last = 0 |
363 COH901318_CX_CTRL_TC_ENABLE |
364 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
365 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
366 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
367 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
368 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
369 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
370 COH901318_CX_CTRL_TCP_ENABLE |
371 COH901318_CX_CTRL_TC_IRQ_ENABLE |
372 COH901318_CX_CTRL_HSP_ENABLE |
373 COH901318_CX_CTRL_HSS_DISABLE |
374 COH901318_CX_CTRL_DDMA_LEGACY |
375 COH901318_CX_CTRL_PRDD_SOURCE,
376 .desc_nbr_max = 10,
377 },
378 {
379 .number = U300_DMA_MSL_TX_3,
380 .name = "MSL TX 3",
381 .priority_high = 0,
382 .param.config = COH901318_CX_CFG_CH_DISABLE |
383 COH901318_CX_CFG_LCR_DISABLE |
384 COH901318_CX_CFG_TC_IRQ_ENABLE |
385 COH901318_CX_CFG_BE_IRQ_ENABLE,
386 .param.ctrl_lli_chained = 0 |
387 COH901318_CX_CTRL_TC_ENABLE |
388 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
389 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
390 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
391 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
392 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
393 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
394 COH901318_CX_CTRL_TCP_DISABLE |
395 COH901318_CX_CTRL_TC_IRQ_DISABLE |
396 COH901318_CX_CTRL_HSP_ENABLE |
397 COH901318_CX_CTRL_HSS_DISABLE |
398 COH901318_CX_CTRL_DDMA_LEGACY |
399 COH901318_CX_CTRL_PRDD_SOURCE,
400 .param.ctrl_lli = 0 |
401 COH901318_CX_CTRL_TC_ENABLE |
402 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
403 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
404 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
405 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
406 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
407 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
408 COH901318_CX_CTRL_TCP_ENABLE |
409 COH901318_CX_CTRL_TC_IRQ_DISABLE |
410 COH901318_CX_CTRL_HSP_ENABLE |
411 COH901318_CX_CTRL_HSS_DISABLE |
412 COH901318_CX_CTRL_DDMA_LEGACY |
413 COH901318_CX_CTRL_PRDD_SOURCE,
414 .param.ctrl_lli_last = 0 |
415 COH901318_CX_CTRL_TC_ENABLE |
416 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
417 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
418 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
419 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
420 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
421 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
422 COH901318_CX_CTRL_TCP_ENABLE |
423 COH901318_CX_CTRL_TC_IRQ_ENABLE |
424 COH901318_CX_CTRL_HSP_ENABLE |
425 COH901318_CX_CTRL_HSS_DISABLE |
426 COH901318_CX_CTRL_DDMA_LEGACY |
427 COH901318_CX_CTRL_PRDD_SOURCE,
428 },
429 {
430 .number = U300_DMA_MSL_TX_4,
431 .name = "MSL TX 4",
432 .priority_high = 0,
433 .param.config = COH901318_CX_CFG_CH_DISABLE |
434 COH901318_CX_CFG_LCR_DISABLE |
435 COH901318_CX_CFG_TC_IRQ_ENABLE |
436 COH901318_CX_CFG_BE_IRQ_ENABLE,
437 .param.ctrl_lli_chained = 0 |
438 COH901318_CX_CTRL_TC_ENABLE |
439 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
440 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
441 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
442 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
443 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
444 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
445 COH901318_CX_CTRL_TCP_DISABLE |
446 COH901318_CX_CTRL_TC_IRQ_DISABLE |
447 COH901318_CX_CTRL_HSP_ENABLE |
448 COH901318_CX_CTRL_HSS_DISABLE |
449 COH901318_CX_CTRL_DDMA_LEGACY |
450 COH901318_CX_CTRL_PRDD_SOURCE,
451 .param.ctrl_lli = 0 |
452 COH901318_CX_CTRL_TC_ENABLE |
453 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
454 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
455 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
456 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
457 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
458 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
459 COH901318_CX_CTRL_TCP_ENABLE |
460 COH901318_CX_CTRL_TC_IRQ_DISABLE |
461 COH901318_CX_CTRL_HSP_ENABLE |
462 COH901318_CX_CTRL_HSS_DISABLE |
463 COH901318_CX_CTRL_DDMA_LEGACY |
464 COH901318_CX_CTRL_PRDD_SOURCE,
465 .param.ctrl_lli_last = 0 |
466 COH901318_CX_CTRL_TC_ENABLE |
467 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
468 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
469 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
470 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
471 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
472 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
473 COH901318_CX_CTRL_TCP_ENABLE |
474 COH901318_CX_CTRL_TC_IRQ_ENABLE |
475 COH901318_CX_CTRL_HSP_ENABLE |
476 COH901318_CX_CTRL_HSS_DISABLE |
477 COH901318_CX_CTRL_DDMA_LEGACY |
478 COH901318_CX_CTRL_PRDD_SOURCE,
479 },
480 {
481 .number = U300_DMA_MSL_TX_5,
482 .name = "MSL TX 5",
483 .priority_high = 0,
484 },
485 {
486 .number = U300_DMA_MSL_TX_6,
487 .name = "MSL TX 6",
488 .priority_high = 0,
489 },
490 {
491 .number = U300_DMA_MSL_RX_0,
492 .name = "MSL RX 0",
493 .priority_high = 0,
494 },
495 {
496 .number = U300_DMA_MSL_RX_1,
497 .name = "MSL RX 1",
498 .priority_high = 0,
499 .param.config = COH901318_CX_CFG_CH_DISABLE |
500 COH901318_CX_CFG_LCR_DISABLE |
501 COH901318_CX_CFG_TC_IRQ_ENABLE |
502 COH901318_CX_CFG_BE_IRQ_ENABLE,
503 .param.ctrl_lli_chained = 0 |
504 COH901318_CX_CTRL_TC_ENABLE |
505 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
506 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
507 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
508 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
509 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
510 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
511 COH901318_CX_CTRL_TCP_DISABLE |
512 COH901318_CX_CTRL_TC_IRQ_DISABLE |
513 COH901318_CX_CTRL_HSP_ENABLE |
514 COH901318_CX_CTRL_HSS_DISABLE |
515 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
516 COH901318_CX_CTRL_PRDD_DEST,
517 .param.ctrl_lli = 0,
518 .param.ctrl_lli_last = 0 |
519 COH901318_CX_CTRL_TC_ENABLE |
520 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
521 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
522 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
523 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
524 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
525 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
526 COH901318_CX_CTRL_TCP_DISABLE |
527 COH901318_CX_CTRL_TC_IRQ_ENABLE |
528 COH901318_CX_CTRL_HSP_ENABLE |
529 COH901318_CX_CTRL_HSS_DISABLE |
530 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
531 COH901318_CX_CTRL_PRDD_DEST,
532 },
533 {
534 .number = U300_DMA_MSL_RX_2,
535 .name = "MSL RX 2",
536 .priority_high = 0,
537 .param.config = COH901318_CX_CFG_CH_DISABLE |
538 COH901318_CX_CFG_LCR_DISABLE |
539 COH901318_CX_CFG_TC_IRQ_ENABLE |
540 COH901318_CX_CFG_BE_IRQ_ENABLE,
541 .param.ctrl_lli_chained = 0 |
542 COH901318_CX_CTRL_TC_ENABLE |
543 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
544 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
545 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
546 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
547 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
548 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
549 COH901318_CX_CTRL_TCP_DISABLE |
550 COH901318_CX_CTRL_TC_IRQ_DISABLE |
551 COH901318_CX_CTRL_HSP_ENABLE |
552 COH901318_CX_CTRL_HSS_DISABLE |
553 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
554 COH901318_CX_CTRL_PRDD_DEST,
555 .param.ctrl_lli = 0 |
556 COH901318_CX_CTRL_TC_ENABLE |
557 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
558 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
559 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
560 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
561 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
562 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
563 COH901318_CX_CTRL_TCP_DISABLE |
564 COH901318_CX_CTRL_TC_IRQ_ENABLE |
565 COH901318_CX_CTRL_HSP_ENABLE |
566 COH901318_CX_CTRL_HSS_DISABLE |
567 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
568 COH901318_CX_CTRL_PRDD_DEST,
569 .param.ctrl_lli_last = 0 |
570 COH901318_CX_CTRL_TC_ENABLE |
571 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
572 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
573 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
574 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
575 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
576 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
577 COH901318_CX_CTRL_TCP_DISABLE |
578 COH901318_CX_CTRL_TC_IRQ_ENABLE |
579 COH901318_CX_CTRL_HSP_ENABLE |
580 COH901318_CX_CTRL_HSS_DISABLE |
581 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
582 COH901318_CX_CTRL_PRDD_DEST,
583 },
584 {
585 .number = U300_DMA_MSL_RX_3,
586 .name = "MSL RX 3",
587 .priority_high = 0,
588 .param.config = COH901318_CX_CFG_CH_DISABLE |
589 COH901318_CX_CFG_LCR_DISABLE |
590 COH901318_CX_CFG_TC_IRQ_ENABLE |
591 COH901318_CX_CFG_BE_IRQ_ENABLE,
592 .param.ctrl_lli_chained = 0 |
593 COH901318_CX_CTRL_TC_ENABLE |
594 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
595 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
596 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
597 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
598 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
599 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
600 COH901318_CX_CTRL_TCP_DISABLE |
601 COH901318_CX_CTRL_TC_IRQ_DISABLE |
602 COH901318_CX_CTRL_HSP_ENABLE |
603 COH901318_CX_CTRL_HSS_DISABLE |
604 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
605 COH901318_CX_CTRL_PRDD_DEST,
606 .param.ctrl_lli = 0 |
607 COH901318_CX_CTRL_TC_ENABLE |
608 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
609 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
610 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
611 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
612 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
613 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
614 COH901318_CX_CTRL_TCP_DISABLE |
615 COH901318_CX_CTRL_TC_IRQ_ENABLE |
616 COH901318_CX_CTRL_HSP_ENABLE |
617 COH901318_CX_CTRL_HSS_DISABLE |
618 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
619 COH901318_CX_CTRL_PRDD_DEST,
620 .param.ctrl_lli_last = 0 |
621 COH901318_CX_CTRL_TC_ENABLE |
622 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
623 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
624 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
625 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
626 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
627 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
628 COH901318_CX_CTRL_TCP_DISABLE |
629 COH901318_CX_CTRL_TC_IRQ_ENABLE |
630 COH901318_CX_CTRL_HSP_ENABLE |
631 COH901318_CX_CTRL_HSS_DISABLE |
632 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
633 COH901318_CX_CTRL_PRDD_DEST,
634 },
635 {
636 .number = U300_DMA_MSL_RX_4,
637 .name = "MSL RX 4",
638 .priority_high = 0,
639 .param.config = COH901318_CX_CFG_CH_DISABLE |
640 COH901318_CX_CFG_LCR_DISABLE |
641 COH901318_CX_CFG_TC_IRQ_ENABLE |
642 COH901318_CX_CFG_BE_IRQ_ENABLE,
643 .param.ctrl_lli_chained = 0 |
644 COH901318_CX_CTRL_TC_ENABLE |
645 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
646 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
647 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
648 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
649 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
650 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
651 COH901318_CX_CTRL_TCP_DISABLE |
652 COH901318_CX_CTRL_TC_IRQ_DISABLE |
653 COH901318_CX_CTRL_HSP_ENABLE |
654 COH901318_CX_CTRL_HSS_DISABLE |
655 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
656 COH901318_CX_CTRL_PRDD_DEST,
657 .param.ctrl_lli = 0 |
658 COH901318_CX_CTRL_TC_ENABLE |
659 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
660 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
661 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
662 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
663 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
664 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
665 COH901318_CX_CTRL_TCP_DISABLE |
666 COH901318_CX_CTRL_TC_IRQ_ENABLE |
667 COH901318_CX_CTRL_HSP_ENABLE |
668 COH901318_CX_CTRL_HSS_DISABLE |
669 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
670 COH901318_CX_CTRL_PRDD_DEST,
671 .param.ctrl_lli_last = 0 |
672 COH901318_CX_CTRL_TC_ENABLE |
673 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
674 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
675 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
676 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
677 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
678 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
679 COH901318_CX_CTRL_TCP_DISABLE |
680 COH901318_CX_CTRL_TC_IRQ_ENABLE |
681 COH901318_CX_CTRL_HSP_ENABLE |
682 COH901318_CX_CTRL_HSS_DISABLE |
683 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
684 COH901318_CX_CTRL_PRDD_DEST,
685 },
686 {
687 .number = U300_DMA_MSL_RX_5,
688 .name = "MSL RX 5",
689 .priority_high = 0,
690 .param.config = COH901318_CX_CFG_CH_DISABLE |
691 COH901318_CX_CFG_LCR_DISABLE |
692 COH901318_CX_CFG_TC_IRQ_ENABLE |
693 COH901318_CX_CFG_BE_IRQ_ENABLE,
694 .param.ctrl_lli_chained = 0 |
695 COH901318_CX_CTRL_TC_ENABLE |
696 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
697 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
698 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
699 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
700 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
701 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
702 COH901318_CX_CTRL_TCP_DISABLE |
703 COH901318_CX_CTRL_TC_IRQ_DISABLE |
704 COH901318_CX_CTRL_HSP_ENABLE |
705 COH901318_CX_CTRL_HSS_DISABLE |
706 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
707 COH901318_CX_CTRL_PRDD_DEST,
708 .param.ctrl_lli = 0 |
709 COH901318_CX_CTRL_TC_ENABLE |
710 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
711 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
712 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
713 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
714 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
715 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
716 COH901318_CX_CTRL_TCP_DISABLE |
717 COH901318_CX_CTRL_TC_IRQ_ENABLE |
718 COH901318_CX_CTRL_HSP_ENABLE |
719 COH901318_CX_CTRL_HSS_DISABLE |
720 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
721 COH901318_CX_CTRL_PRDD_DEST,
722 .param.ctrl_lli_last = 0 |
723 COH901318_CX_CTRL_TC_ENABLE |
724 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
725 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
726 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
727 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
728 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
729 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
730 COH901318_CX_CTRL_TCP_DISABLE |
731 COH901318_CX_CTRL_TC_IRQ_ENABLE |
732 COH901318_CX_CTRL_HSP_ENABLE |
733 COH901318_CX_CTRL_HSS_DISABLE |
734 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
735 COH901318_CX_CTRL_PRDD_DEST,
736 },
737 {
738 .number = U300_DMA_MSL_RX_6,
739 .name = "MSL RX 6",
740 .priority_high = 0,
741 },
742 /*
743 * Don't set up device address, burst count or size of src
744 * or dst bus for this peripheral - handled by PrimeCell
745 * DMA extension.
746 */
747 {
748 .number = U300_DMA_MMCSD_RX_TX,
749 .name = "MMCSD RX TX",
750 .priority_high = 0,
751 .param.config = COH901318_CX_CFG_CH_DISABLE |
752 COH901318_CX_CFG_LCR_DISABLE |
753 COH901318_CX_CFG_TC_IRQ_ENABLE |
754 COH901318_CX_CFG_BE_IRQ_ENABLE,
755 .param.ctrl_lli_chained = 0 |
756 COH901318_CX_CTRL_TC_ENABLE |
757 COH901318_CX_CTRL_MASTER_MODE_M1RW |
758 COH901318_CX_CTRL_TCP_ENABLE |
759 COH901318_CX_CTRL_TC_IRQ_DISABLE |
760 COH901318_CX_CTRL_HSP_ENABLE |
761 COH901318_CX_CTRL_HSS_DISABLE |
762 COH901318_CX_CTRL_DDMA_LEGACY,
763 .param.ctrl_lli = 0 |
764 COH901318_CX_CTRL_TC_ENABLE |
765 COH901318_CX_CTRL_MASTER_MODE_M1RW |
766 COH901318_CX_CTRL_TCP_ENABLE |
767 COH901318_CX_CTRL_TC_IRQ_DISABLE |
768 COH901318_CX_CTRL_HSP_ENABLE |
769 COH901318_CX_CTRL_HSS_DISABLE |
770 COH901318_CX_CTRL_DDMA_LEGACY,
771 .param.ctrl_lli_last = 0 |
772 COH901318_CX_CTRL_TC_ENABLE |
773 COH901318_CX_CTRL_MASTER_MODE_M1RW |
774 COH901318_CX_CTRL_TCP_DISABLE |
775 COH901318_CX_CTRL_TC_IRQ_ENABLE |
776 COH901318_CX_CTRL_HSP_ENABLE |
777 COH901318_CX_CTRL_HSS_DISABLE |
778 COH901318_CX_CTRL_DDMA_LEGACY,
779
780 },
781 {
782 .number = U300_DMA_MSPRO_TX,
783 .name = "MSPRO TX",
784 .priority_high = 0,
785 },
786 {
787 .number = U300_DMA_MSPRO_RX,
788 .name = "MSPRO RX",
789 .priority_high = 0,
790 },
791 /*
792 * Don't set up device address, burst count or size of src
793 * or dst bus for this peripheral - handled by PrimeCell
794 * DMA extension.
795 */
796 {
797 .number = U300_DMA_UART0_TX,
798 .name = "UART0 TX",
799 .priority_high = 0,
800 .param.config = COH901318_CX_CFG_CH_DISABLE |
801 COH901318_CX_CFG_LCR_DISABLE |
802 COH901318_CX_CFG_TC_IRQ_ENABLE |
803 COH901318_CX_CFG_BE_IRQ_ENABLE,
804 .param.ctrl_lli_chained = 0 |
805 COH901318_CX_CTRL_TC_ENABLE |
806 COH901318_CX_CTRL_MASTER_MODE_M1RW |
807 COH901318_CX_CTRL_TCP_ENABLE |
808 COH901318_CX_CTRL_TC_IRQ_DISABLE |
809 COH901318_CX_CTRL_HSP_ENABLE |
810 COH901318_CX_CTRL_HSS_DISABLE |
811 COH901318_CX_CTRL_DDMA_LEGACY,
812 .param.ctrl_lli = 0 |
813 COH901318_CX_CTRL_TC_ENABLE |
814 COH901318_CX_CTRL_MASTER_MODE_M1RW |
815 COH901318_CX_CTRL_TCP_ENABLE |
816 COH901318_CX_CTRL_TC_IRQ_ENABLE |
817 COH901318_CX_CTRL_HSP_ENABLE |
818 COH901318_CX_CTRL_HSS_DISABLE |
819 COH901318_CX_CTRL_DDMA_LEGACY,
820 .param.ctrl_lli_last = 0 |
821 COH901318_CX_CTRL_TC_ENABLE |
822 COH901318_CX_CTRL_MASTER_MODE_M1RW |
823 COH901318_CX_CTRL_TCP_ENABLE |
824 COH901318_CX_CTRL_TC_IRQ_ENABLE |
825 COH901318_CX_CTRL_HSP_ENABLE |
826 COH901318_CX_CTRL_HSS_DISABLE |
827 COH901318_CX_CTRL_DDMA_LEGACY,
828 },
829 {
830 .number = U300_DMA_UART0_RX,
831 .name = "UART0 RX",
832 .priority_high = 0,
833 .param.config = COH901318_CX_CFG_CH_DISABLE |
834 COH901318_CX_CFG_LCR_DISABLE |
835 COH901318_CX_CFG_TC_IRQ_ENABLE |
836 COH901318_CX_CFG_BE_IRQ_ENABLE,
837 .param.ctrl_lli_chained = 0 |
838 COH901318_CX_CTRL_TC_ENABLE |
839 COH901318_CX_CTRL_MASTER_MODE_M1RW |
840 COH901318_CX_CTRL_TCP_ENABLE |
841 COH901318_CX_CTRL_TC_IRQ_DISABLE |
842 COH901318_CX_CTRL_HSP_ENABLE |
843 COH901318_CX_CTRL_HSS_DISABLE |
844 COH901318_CX_CTRL_DDMA_LEGACY,
845 .param.ctrl_lli = 0 |
846 COH901318_CX_CTRL_TC_ENABLE |
847 COH901318_CX_CTRL_MASTER_MODE_M1RW |
848 COH901318_CX_CTRL_TCP_ENABLE |
849 COH901318_CX_CTRL_TC_IRQ_ENABLE |
850 COH901318_CX_CTRL_HSP_ENABLE |
851 COH901318_CX_CTRL_HSS_DISABLE |
852 COH901318_CX_CTRL_DDMA_LEGACY,
853 .param.ctrl_lli_last = 0 |
854 COH901318_CX_CTRL_TC_ENABLE |
855 COH901318_CX_CTRL_MASTER_MODE_M1RW |
856 COH901318_CX_CTRL_TCP_ENABLE |
857 COH901318_CX_CTRL_TC_IRQ_ENABLE |
858 COH901318_CX_CTRL_HSP_ENABLE |
859 COH901318_CX_CTRL_HSS_DISABLE |
860 COH901318_CX_CTRL_DDMA_LEGACY,
861 },
862 {
863 .number = U300_DMA_APEX_TX,
864 .name = "APEX TX",
865 .priority_high = 0,
866 },
867 {
868 .number = U300_DMA_APEX_RX,
869 .name = "APEX RX",
870 .priority_high = 0,
871 },
872 {
873 .number = U300_DMA_PCM_I2S0_TX,
874 .name = "PCM I2S0 TX",
875 .priority_high = 1,
876 .param.config = COH901318_CX_CFG_CH_DISABLE |
877 COH901318_CX_CFG_LCR_DISABLE |
878 COH901318_CX_CFG_TC_IRQ_ENABLE |
879 COH901318_CX_CFG_BE_IRQ_ENABLE,
880 .param.ctrl_lli_chained = 0 |
881 COH901318_CX_CTRL_TC_ENABLE |
882 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
883 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
884 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
885 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
886 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
887 COH901318_CX_CTRL_MASTER_MODE_M1RW |
888 COH901318_CX_CTRL_TCP_DISABLE |
889 COH901318_CX_CTRL_TC_IRQ_DISABLE |
890 COH901318_CX_CTRL_HSP_ENABLE |
891 COH901318_CX_CTRL_HSS_DISABLE |
892 COH901318_CX_CTRL_DDMA_LEGACY |
893 COH901318_CX_CTRL_PRDD_SOURCE,
894 .param.ctrl_lli = 0 |
895 COH901318_CX_CTRL_TC_ENABLE |
896 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
897 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
898 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
899 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
900 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
901 COH901318_CX_CTRL_MASTER_MODE_M1RW |
902 COH901318_CX_CTRL_TCP_ENABLE |
903 COH901318_CX_CTRL_TC_IRQ_DISABLE |
904 COH901318_CX_CTRL_HSP_ENABLE |
905 COH901318_CX_CTRL_HSS_DISABLE |
906 COH901318_CX_CTRL_DDMA_LEGACY |
907 COH901318_CX_CTRL_PRDD_SOURCE,
908 .param.ctrl_lli_last = 0 |
909 COH901318_CX_CTRL_TC_ENABLE |
910 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
911 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
912 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
913 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
914 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
915 COH901318_CX_CTRL_MASTER_MODE_M1RW |
916 COH901318_CX_CTRL_TCP_ENABLE |
917 COH901318_CX_CTRL_TC_IRQ_DISABLE |
918 COH901318_CX_CTRL_HSP_ENABLE |
919 COH901318_CX_CTRL_HSS_DISABLE |
920 COH901318_CX_CTRL_DDMA_LEGACY |
921 COH901318_CX_CTRL_PRDD_SOURCE,
922 },
923 {
924 .number = U300_DMA_PCM_I2S0_RX,
925 .name = "PCM I2S0 RX",
926 .priority_high = 1,
927 .param.config = COH901318_CX_CFG_CH_DISABLE |
928 COH901318_CX_CFG_LCR_DISABLE |
929 COH901318_CX_CFG_TC_IRQ_ENABLE |
930 COH901318_CX_CFG_BE_IRQ_ENABLE,
931 .param.ctrl_lli_chained = 0 |
932 COH901318_CX_CTRL_TC_ENABLE |
933 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
934 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
935 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
936 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
937 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
938 COH901318_CX_CTRL_MASTER_MODE_M1RW |
939 COH901318_CX_CTRL_TCP_DISABLE |
940 COH901318_CX_CTRL_TC_IRQ_DISABLE |
941 COH901318_CX_CTRL_HSP_ENABLE |
942 COH901318_CX_CTRL_HSS_DISABLE |
943 COH901318_CX_CTRL_DDMA_LEGACY |
944 COH901318_CX_CTRL_PRDD_DEST,
945 .param.ctrl_lli = 0 |
946 COH901318_CX_CTRL_TC_ENABLE |
947 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
948 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
949 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
950 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
951 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
952 COH901318_CX_CTRL_MASTER_MODE_M1RW |
953 COH901318_CX_CTRL_TCP_ENABLE |
954 COH901318_CX_CTRL_TC_IRQ_DISABLE |
955 COH901318_CX_CTRL_HSP_ENABLE |
956 COH901318_CX_CTRL_HSS_DISABLE |
957 COH901318_CX_CTRL_DDMA_LEGACY |
958 COH901318_CX_CTRL_PRDD_DEST,
959 .param.ctrl_lli_last = 0 |
960 COH901318_CX_CTRL_TC_ENABLE |
961 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
962 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
963 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
964 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
965 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
966 COH901318_CX_CTRL_MASTER_MODE_M1RW |
967 COH901318_CX_CTRL_TCP_ENABLE |
968 COH901318_CX_CTRL_TC_IRQ_ENABLE |
969 COH901318_CX_CTRL_HSP_ENABLE |
970 COH901318_CX_CTRL_HSS_DISABLE |
971 COH901318_CX_CTRL_DDMA_LEGACY |
972 COH901318_CX_CTRL_PRDD_DEST,
973 },
974 {
975 .number = U300_DMA_PCM_I2S1_TX,
976 .name = "PCM I2S1 TX",
977 .priority_high = 1,
978 .param.config = COH901318_CX_CFG_CH_DISABLE |
979 COH901318_CX_CFG_LCR_DISABLE |
980 COH901318_CX_CFG_TC_IRQ_ENABLE |
981 COH901318_CX_CFG_BE_IRQ_ENABLE,
982 .param.ctrl_lli_chained = 0 |
983 COH901318_CX_CTRL_TC_ENABLE |
984 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
985 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
986 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
987 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
988 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
989 COH901318_CX_CTRL_MASTER_MODE_M1RW |
990 COH901318_CX_CTRL_TCP_DISABLE |
991 COH901318_CX_CTRL_TC_IRQ_DISABLE |
992 COH901318_CX_CTRL_HSP_ENABLE |
993 COH901318_CX_CTRL_HSS_DISABLE |
994 COH901318_CX_CTRL_DDMA_LEGACY |
995 COH901318_CX_CTRL_PRDD_SOURCE,
996 .param.ctrl_lli = 0 |
997 COH901318_CX_CTRL_TC_ENABLE |
998 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
999 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1000 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1001 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1002 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1003 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1004 COH901318_CX_CTRL_TCP_ENABLE |
1005 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1006 COH901318_CX_CTRL_HSP_ENABLE |
1007 COH901318_CX_CTRL_HSS_DISABLE |
1008 COH901318_CX_CTRL_DDMA_LEGACY |
1009 COH901318_CX_CTRL_PRDD_SOURCE,
1010 .param.ctrl_lli_last = 0 |
1011 COH901318_CX_CTRL_TC_ENABLE |
1012 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1013 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1014 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1015 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1016 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1017 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1018 COH901318_CX_CTRL_TCP_ENABLE |
1019 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1020 COH901318_CX_CTRL_HSP_ENABLE |
1021 COH901318_CX_CTRL_HSS_DISABLE |
1022 COH901318_CX_CTRL_DDMA_LEGACY |
1023 COH901318_CX_CTRL_PRDD_SOURCE,
1024 },
1025 {
1026 .number = U300_DMA_PCM_I2S1_RX,
1027 .name = "PCM I2S1 RX",
1028 .priority_high = 1,
1029 .param.config = COH901318_CX_CFG_CH_DISABLE |
1030 COH901318_CX_CFG_LCR_DISABLE |
1031 COH901318_CX_CFG_TC_IRQ_ENABLE |
1032 COH901318_CX_CFG_BE_IRQ_ENABLE,
1033 .param.ctrl_lli_chained = 0 |
1034 COH901318_CX_CTRL_TC_ENABLE |
1035 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1036 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1037 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1038 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1039 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1040 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1041 COH901318_CX_CTRL_TCP_DISABLE |
1042 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1043 COH901318_CX_CTRL_HSP_ENABLE |
1044 COH901318_CX_CTRL_HSS_DISABLE |
1045 COH901318_CX_CTRL_DDMA_LEGACY |
1046 COH901318_CX_CTRL_PRDD_DEST,
1047 .param.ctrl_lli = 0 |
1048 COH901318_CX_CTRL_TC_ENABLE |
1049 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1050 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1051 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1052 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1053 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1054 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1055 COH901318_CX_CTRL_TCP_ENABLE |
1056 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1057 COH901318_CX_CTRL_HSP_ENABLE |
1058 COH901318_CX_CTRL_HSS_DISABLE |
1059 COH901318_CX_CTRL_DDMA_LEGACY |
1060 COH901318_CX_CTRL_PRDD_DEST,
1061 .param.ctrl_lli_last = 0 |
1062 COH901318_CX_CTRL_TC_ENABLE |
1063 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1064 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1065 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1066 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1067 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1068 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1069 COH901318_CX_CTRL_TCP_ENABLE |
1070 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1071 COH901318_CX_CTRL_HSP_ENABLE |
1072 COH901318_CX_CTRL_HSS_DISABLE |
1073 COH901318_CX_CTRL_DDMA_LEGACY |
1074 COH901318_CX_CTRL_PRDD_DEST,
1075 },
1076 {
1077 .number = U300_DMA_XGAM_CDI,
1078 .name = "XGAM CDI",
1079 .priority_high = 0,
1080 },
1081 {
1082 .number = U300_DMA_XGAM_PDI,
1083 .name = "XGAM PDI",
1084 .priority_high = 0,
1085 },
1086 /*
1087 * Don't set up device address, burst count or size of src
1088 * or dst bus for this peripheral - handled by PrimeCell
1089 * DMA extension.
1090 */
1091 {
1092 .number = U300_DMA_SPI_TX,
1093 .name = "SPI TX",
1094 .priority_high = 0,
1095 .param.config = COH901318_CX_CFG_CH_DISABLE |
1096 COH901318_CX_CFG_LCR_DISABLE |
1097 COH901318_CX_CFG_TC_IRQ_ENABLE |
1098 COH901318_CX_CFG_BE_IRQ_ENABLE,
1099 .param.ctrl_lli_chained = 0 |
1100 COH901318_CX_CTRL_TC_ENABLE |
1101 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1102 COH901318_CX_CTRL_TCP_DISABLE |
1103 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1104 COH901318_CX_CTRL_HSP_ENABLE |
1105 COH901318_CX_CTRL_HSS_DISABLE |
1106 COH901318_CX_CTRL_DDMA_LEGACY,
1107 .param.ctrl_lli = 0 |
1108 COH901318_CX_CTRL_TC_ENABLE |
1109 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1110 COH901318_CX_CTRL_TCP_DISABLE |
1111 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1112 COH901318_CX_CTRL_HSP_ENABLE |
1113 COH901318_CX_CTRL_HSS_DISABLE |
1114 COH901318_CX_CTRL_DDMA_LEGACY,
1115 .param.ctrl_lli_last = 0 |
1116 COH901318_CX_CTRL_TC_ENABLE |
1117 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1118 COH901318_CX_CTRL_TCP_DISABLE |
1119 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1120 COH901318_CX_CTRL_HSP_ENABLE |
1121 COH901318_CX_CTRL_HSS_DISABLE |
1122 COH901318_CX_CTRL_DDMA_LEGACY,
1123 },
1124 {
1125 .number = U300_DMA_SPI_RX,
1126 .name = "SPI RX",
1127 .priority_high = 0,
1128 .param.config = COH901318_CX_CFG_CH_DISABLE |
1129 COH901318_CX_CFG_LCR_DISABLE |
1130 COH901318_CX_CFG_TC_IRQ_ENABLE |
1131 COH901318_CX_CFG_BE_IRQ_ENABLE,
1132 .param.ctrl_lli_chained = 0 |
1133 COH901318_CX_CTRL_TC_ENABLE |
1134 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1135 COH901318_CX_CTRL_TCP_DISABLE |
1136 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1137 COH901318_CX_CTRL_HSP_ENABLE |
1138 COH901318_CX_CTRL_HSS_DISABLE |
1139 COH901318_CX_CTRL_DDMA_LEGACY,
1140 .param.ctrl_lli = 0 |
1141 COH901318_CX_CTRL_TC_ENABLE |
1142 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1143 COH901318_CX_CTRL_TCP_DISABLE |
1144 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1145 COH901318_CX_CTRL_HSP_ENABLE |
1146 COH901318_CX_CTRL_HSS_DISABLE |
1147 COH901318_CX_CTRL_DDMA_LEGACY,
1148 .param.ctrl_lli_last = 0 |
1149 COH901318_CX_CTRL_TC_ENABLE |
1150 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1151 COH901318_CX_CTRL_TCP_DISABLE |
1152 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1153 COH901318_CX_CTRL_HSP_ENABLE |
1154 COH901318_CX_CTRL_HSS_DISABLE |
1155 COH901318_CX_CTRL_DDMA_LEGACY,
1156
1157 },
1158 {
1159 .number = U300_DMA_GENERAL_PURPOSE_0,
1160 .name = "GENERAL 00",
1161 .priority_high = 0,
1162
1163 .param.config = flags_memcpy_config,
1164 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1165 .param.ctrl_lli = flags_memcpy_lli,
1166 .param.ctrl_lli_last = flags_memcpy_lli_last,
1167 },
1168 {
1169 .number = U300_DMA_GENERAL_PURPOSE_1,
1170 .name = "GENERAL 01",
1171 .priority_high = 0,
1172
1173 .param.config = flags_memcpy_config,
1174 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1175 .param.ctrl_lli = flags_memcpy_lli,
1176 .param.ctrl_lli_last = flags_memcpy_lli_last,
1177 },
1178 {
1179 .number = U300_DMA_GENERAL_PURPOSE_2,
1180 .name = "GENERAL 02",
1181 .priority_high = 0,
1182
1183 .param.config = flags_memcpy_config,
1184 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1185 .param.ctrl_lli = flags_memcpy_lli,
1186 .param.ctrl_lli_last = flags_memcpy_lli_last,
1187 },
1188 {
1189 .number = U300_DMA_GENERAL_PURPOSE_3,
1190 .name = "GENERAL 03",
1191 .priority_high = 0,
1192
1193 .param.config = flags_memcpy_config,
1194 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1195 .param.ctrl_lli = flags_memcpy_lli,
1196 .param.ctrl_lli_last = flags_memcpy_lli_last,
1197 },
1198 {
1199 .number = U300_DMA_GENERAL_PURPOSE_4,
1200 .name = "GENERAL 04",
1201 .priority_high = 0,
1202
1203 .param.config = flags_memcpy_config,
1204 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1205 .param.ctrl_lli = flags_memcpy_lli,
1206 .param.ctrl_lli_last = flags_memcpy_lli_last,
1207 },
1208 {
1209 .number = U300_DMA_GENERAL_PURPOSE_5,
1210 .name = "GENERAL 05",
1211 .priority_high = 0,
1212
1213 .param.config = flags_memcpy_config,
1214 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1215 .param.ctrl_lli = flags_memcpy_lli,
1216 .param.ctrl_lli_last = flags_memcpy_lli_last,
1217 },
1218 {
1219 .number = U300_DMA_GENERAL_PURPOSE_6,
1220 .name = "GENERAL 06",
1221 .priority_high = 0,
1222
1223 .param.config = flags_memcpy_config,
1224 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1225 .param.ctrl_lli = flags_memcpy_lli,
1226 .param.ctrl_lli_last = flags_memcpy_lli_last,
1227 },
1228 {
1229 .number = U300_DMA_GENERAL_PURPOSE_7,
1230 .name = "GENERAL 07",
1231 .priority_high = 0,
1232
1233 .param.config = flags_memcpy_config,
1234 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1235 .param.ctrl_lli = flags_memcpy_lli,
1236 .param.ctrl_lli_last = flags_memcpy_lli_last,
1237 },
1238 {
1239 .number = U300_DMA_GENERAL_PURPOSE_8,
1240 .name = "GENERAL 08",
1241 .priority_high = 0,
1242
1243 .param.config = flags_memcpy_config,
1244 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1245 .param.ctrl_lli = flags_memcpy_lli,
1246 .param.ctrl_lli_last = flags_memcpy_lli_last,
1247 },
1248 {
1249 .number = U300_DMA_UART1_TX,
1250 .name = "UART1 TX",
1251 .priority_high = 0,
1252 },
1253 {
1254 .number = U300_DMA_UART1_RX,
1255 .name = "UART1 RX",
1256 .priority_high = 0,
1257 }
1258 };
1259
1260 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
1261
1262 #ifdef VERBOSE_DEBUG
1263 #define COH_DBG(x) ({ if (1) x; 0; })
1264 #else
1265 #define COH_DBG(x) ({ if (0) x; 0; })
1266 #endif
1267
1268 struct coh901318_desc {
1269 struct dma_async_tx_descriptor desc;
1270 struct list_head node;
1271 struct scatterlist *sg;
1272 unsigned int sg_len;
1273 struct coh901318_lli *lli;
1274 enum dma_transfer_direction dir;
1275 unsigned long flags;
1276 u32 head_config;
1277 u32 head_ctrl;
1278 };
1279
1280 struct coh901318_base {
1281 struct device *dev;
1282 void __iomem *virtbase;
1283 struct coh901318_pool pool;
1284 struct powersave pm;
1285 struct dma_device dma_slave;
1286 struct dma_device dma_memcpy;
1287 struct coh901318_chan *chans;
1288 };
1289
1290 struct coh901318_chan {
1291 spinlock_t lock;
1292 int allocated;
1293 int id;
1294 int stopped;
1295
1296 struct work_struct free_work;
1297 struct dma_chan chan;
1298
1299 struct tasklet_struct tasklet;
1300
1301 struct list_head active;
1302 struct list_head queue;
1303 struct list_head free;
1304
1305 unsigned long nbr_active_done;
1306 unsigned long busy;
1307
1308 u32 addr;
1309 u32 ctrl;
1310
1311 struct coh901318_base *base;
1312 };
1313
coh901318_list_print(struct coh901318_chan * cohc,struct coh901318_lli * lli)1314 static void coh901318_list_print(struct coh901318_chan *cohc,
1315 struct coh901318_lli *lli)
1316 {
1317 struct coh901318_lli *l = lli;
1318 int i = 0;
1319
1320 while (l) {
1321 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
1322 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
1323 i, l, l->control, l->src_addr, l->dst_addr,
1324 l->link_addr, l->virt_link_addr);
1325 i++;
1326 l = l->virt_link_addr;
1327 }
1328 }
1329
1330 #ifdef CONFIG_DEBUG_FS
1331
1332 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
1333
1334 static struct coh901318_base *debugfs_dma_base;
1335 static struct dentry *dma_dentry;
1336
coh901318_debugfs_read(struct file * file,char __user * buf,size_t count,loff_t * f_pos)1337 static int coh901318_debugfs_read(struct file *file, char __user *buf,
1338 size_t count, loff_t *f_pos)
1339 {
1340 u64 started_channels = debugfs_dma_base->pm.started_channels;
1341 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
1342 char *dev_buf;
1343 char *tmp;
1344 int ret;
1345 int i;
1346
1347 dev_buf = kmalloc(4*1024, GFP_KERNEL);
1348 if (dev_buf == NULL)
1349 return -ENOMEM;
1350 tmp = dev_buf;
1351
1352 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
1353
1354 for (i = 0; i < U300_DMA_CHANNELS; i++)
1355 if (started_channels & (1 << i))
1356 tmp += sprintf(tmp, "channel %d\n", i);
1357
1358 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
1359
1360 ret = simple_read_from_buffer(buf, count, f_pos, dev_buf,
1361 tmp - dev_buf);
1362 kfree(dev_buf);
1363 return ret;
1364 }
1365
1366 static const struct file_operations coh901318_debugfs_status_operations = {
1367 .owner = THIS_MODULE,
1368 .open = simple_open,
1369 .read = coh901318_debugfs_read,
1370 .llseek = default_llseek,
1371 };
1372
1373
init_coh901318_debugfs(void)1374 static int __init init_coh901318_debugfs(void)
1375 {
1376
1377 dma_dentry = debugfs_create_dir("dma", NULL);
1378
1379 (void) debugfs_create_file("status",
1380 S_IFREG | S_IRUGO,
1381 dma_dentry, NULL,
1382 &coh901318_debugfs_status_operations);
1383 return 0;
1384 }
1385
exit_coh901318_debugfs(void)1386 static void __exit exit_coh901318_debugfs(void)
1387 {
1388 debugfs_remove_recursive(dma_dentry);
1389 }
1390
1391 module_init(init_coh901318_debugfs);
1392 module_exit(exit_coh901318_debugfs);
1393 #else
1394
1395 #define COH901318_DEBUGFS_ASSIGN(x, y)
1396
1397 #endif /* CONFIG_DEBUG_FS */
1398
to_coh901318_chan(struct dma_chan * chan)1399 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
1400 {
1401 return container_of(chan, struct coh901318_chan, chan);
1402 }
1403
1404 static inline const struct coh901318_params *
cohc_chan_param(struct coh901318_chan * cohc)1405 cohc_chan_param(struct coh901318_chan *cohc)
1406 {
1407 return &chan_config[cohc->id].param;
1408 }
1409
1410 static inline const struct coh_dma_channel *
cohc_chan_conf(struct coh901318_chan * cohc)1411 cohc_chan_conf(struct coh901318_chan *cohc)
1412 {
1413 return &chan_config[cohc->id];
1414 }
1415
enable_powersave(struct coh901318_chan * cohc)1416 static void enable_powersave(struct coh901318_chan *cohc)
1417 {
1418 unsigned long flags;
1419 struct powersave *pm = &cohc->base->pm;
1420
1421 spin_lock_irqsave(&pm->lock, flags);
1422
1423 pm->started_channels &= ~(1ULL << cohc->id);
1424
1425 spin_unlock_irqrestore(&pm->lock, flags);
1426 }
disable_powersave(struct coh901318_chan * cohc)1427 static void disable_powersave(struct coh901318_chan *cohc)
1428 {
1429 unsigned long flags;
1430 struct powersave *pm = &cohc->base->pm;
1431
1432 spin_lock_irqsave(&pm->lock, flags);
1433
1434 pm->started_channels |= (1ULL << cohc->id);
1435
1436 spin_unlock_irqrestore(&pm->lock, flags);
1437 }
1438
coh901318_set_ctrl(struct coh901318_chan * cohc,u32 control)1439 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
1440 {
1441 int channel = cohc->id;
1442 void __iomem *virtbase = cohc->base->virtbase;
1443
1444 writel(control,
1445 virtbase + COH901318_CX_CTRL +
1446 COH901318_CX_CTRL_SPACING * channel);
1447 return 0;
1448 }
1449
coh901318_set_conf(struct coh901318_chan * cohc,u32 conf)1450 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
1451 {
1452 int channel = cohc->id;
1453 void __iomem *virtbase = cohc->base->virtbase;
1454
1455 writel(conf,
1456 virtbase + COH901318_CX_CFG +
1457 COH901318_CX_CFG_SPACING*channel);
1458 return 0;
1459 }
1460
1461
coh901318_start(struct coh901318_chan * cohc)1462 static int coh901318_start(struct coh901318_chan *cohc)
1463 {
1464 u32 val;
1465 int channel = cohc->id;
1466 void __iomem *virtbase = cohc->base->virtbase;
1467
1468 disable_powersave(cohc);
1469
1470 val = readl(virtbase + COH901318_CX_CFG +
1471 COH901318_CX_CFG_SPACING * channel);
1472
1473 /* Enable channel */
1474 val |= COH901318_CX_CFG_CH_ENABLE;
1475 writel(val, virtbase + COH901318_CX_CFG +
1476 COH901318_CX_CFG_SPACING * channel);
1477
1478 return 0;
1479 }
1480
coh901318_prep_linked_list(struct coh901318_chan * cohc,struct coh901318_lli * lli)1481 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
1482 struct coh901318_lli *lli)
1483 {
1484 int channel = cohc->id;
1485 void __iomem *virtbase = cohc->base->virtbase;
1486
1487 BUG_ON(readl(virtbase + COH901318_CX_STAT +
1488 COH901318_CX_STAT_SPACING*channel) &
1489 COH901318_CX_STAT_ACTIVE);
1490
1491 writel(lli->src_addr,
1492 virtbase + COH901318_CX_SRC_ADDR +
1493 COH901318_CX_SRC_ADDR_SPACING * channel);
1494
1495 writel(lli->dst_addr, virtbase +
1496 COH901318_CX_DST_ADDR +
1497 COH901318_CX_DST_ADDR_SPACING * channel);
1498
1499 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
1500 COH901318_CX_LNK_ADDR_SPACING * channel);
1501
1502 writel(lli->control, virtbase + COH901318_CX_CTRL +
1503 COH901318_CX_CTRL_SPACING * channel);
1504
1505 return 0;
1506 }
1507
1508 static struct coh901318_desc *
coh901318_desc_get(struct coh901318_chan * cohc)1509 coh901318_desc_get(struct coh901318_chan *cohc)
1510 {
1511 struct coh901318_desc *desc;
1512
1513 if (list_empty(&cohc->free)) {
1514 /* alloc new desc because we're out of used ones
1515 * TODO: alloc a pile of descs instead of just one,
1516 * avoid many small allocations.
1517 */
1518 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
1519 if (desc == NULL)
1520 goto out;
1521 INIT_LIST_HEAD(&desc->node);
1522 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
1523 } else {
1524 /* Reuse an old desc. */
1525 desc = list_first_entry(&cohc->free,
1526 struct coh901318_desc,
1527 node);
1528 list_del(&desc->node);
1529 /* Initialize it a bit so it's not insane */
1530 desc->sg = NULL;
1531 desc->sg_len = 0;
1532 desc->desc.callback = NULL;
1533 desc->desc.callback_param = NULL;
1534 }
1535
1536 out:
1537 return desc;
1538 }
1539
1540 static void
coh901318_desc_free(struct coh901318_chan * cohc,struct coh901318_desc * cohd)1541 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
1542 {
1543 list_add_tail(&cohd->node, &cohc->free);
1544 }
1545
1546 /* call with irq lock held */
1547 static void
coh901318_desc_submit(struct coh901318_chan * cohc,struct coh901318_desc * desc)1548 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1549 {
1550 list_add_tail(&desc->node, &cohc->active);
1551 }
1552
1553 static struct coh901318_desc *
coh901318_first_active_get(struct coh901318_chan * cohc)1554 coh901318_first_active_get(struct coh901318_chan *cohc)
1555 {
1556 struct coh901318_desc *d;
1557
1558 if (list_empty(&cohc->active))
1559 return NULL;
1560
1561 d = list_first_entry(&cohc->active,
1562 struct coh901318_desc,
1563 node);
1564 return d;
1565 }
1566
1567 static void
coh901318_desc_remove(struct coh901318_desc * cohd)1568 coh901318_desc_remove(struct coh901318_desc *cohd)
1569 {
1570 list_del(&cohd->node);
1571 }
1572
1573 static void
coh901318_desc_queue(struct coh901318_chan * cohc,struct coh901318_desc * desc)1574 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1575 {
1576 list_add_tail(&desc->node, &cohc->queue);
1577 }
1578
1579 static struct coh901318_desc *
coh901318_first_queued(struct coh901318_chan * cohc)1580 coh901318_first_queued(struct coh901318_chan *cohc)
1581 {
1582 struct coh901318_desc *d;
1583
1584 if (list_empty(&cohc->queue))
1585 return NULL;
1586
1587 d = list_first_entry(&cohc->queue,
1588 struct coh901318_desc,
1589 node);
1590 return d;
1591 }
1592
coh901318_get_bytes_in_lli(struct coh901318_lli * in_lli)1593 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
1594 {
1595 struct coh901318_lli *lli = in_lli;
1596 u32 bytes = 0;
1597
1598 while (lli) {
1599 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
1600 lli = lli->virt_link_addr;
1601 }
1602 return bytes;
1603 }
1604
1605 /*
1606 * Get the number of bytes left to transfer on this channel,
1607 * it is unwise to call this before stopping the channel for
1608 * absolute measures, but for a rough guess you can still call
1609 * it.
1610 */
coh901318_get_bytes_left(struct dma_chan * chan)1611 static u32 coh901318_get_bytes_left(struct dma_chan *chan)
1612 {
1613 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1614 struct coh901318_desc *cohd;
1615 struct list_head *pos;
1616 unsigned long flags;
1617 u32 left = 0;
1618 int i = 0;
1619
1620 spin_lock_irqsave(&cohc->lock, flags);
1621
1622 /*
1623 * If there are many queued jobs, we iterate and add the
1624 * size of them all. We take a special look on the first
1625 * job though, since it is probably active.
1626 */
1627 list_for_each(pos, &cohc->active) {
1628 /*
1629 * The first job in the list will be working on the
1630 * hardware. The job can be stopped but still active,
1631 * so that the transfer counter is somewhere inside
1632 * the buffer.
1633 */
1634 cohd = list_entry(pos, struct coh901318_desc, node);
1635
1636 if (i == 0) {
1637 struct coh901318_lli *lli;
1638 dma_addr_t ladd;
1639
1640 /* Read current transfer count value */
1641 left = readl(cohc->base->virtbase +
1642 COH901318_CX_CTRL +
1643 COH901318_CX_CTRL_SPACING * cohc->id) &
1644 COH901318_CX_CTRL_TC_VALUE_MASK;
1645
1646 /* See if the transfer is linked... */
1647 ladd = readl(cohc->base->virtbase +
1648 COH901318_CX_LNK_ADDR +
1649 COH901318_CX_LNK_ADDR_SPACING *
1650 cohc->id) &
1651 ~COH901318_CX_LNK_LINK_IMMEDIATE;
1652 /* Single transaction */
1653 if (!ladd)
1654 continue;
1655
1656 /*
1657 * Linked transaction, follow the lli, find the
1658 * currently processing lli, and proceed to the next
1659 */
1660 lli = cohd->lli;
1661 while (lli && lli->link_addr != ladd)
1662 lli = lli->virt_link_addr;
1663
1664 if (lli)
1665 lli = lli->virt_link_addr;
1666
1667 /*
1668 * Follow remaining lli links around to count the total
1669 * number of bytes left
1670 */
1671 left += coh901318_get_bytes_in_lli(lli);
1672 } else {
1673 left += coh901318_get_bytes_in_lli(cohd->lli);
1674 }
1675 i++;
1676 }
1677
1678 /* Also count bytes in the queued jobs */
1679 list_for_each(pos, &cohc->queue) {
1680 cohd = list_entry(pos, struct coh901318_desc, node);
1681 left += coh901318_get_bytes_in_lli(cohd->lli);
1682 }
1683
1684 spin_unlock_irqrestore(&cohc->lock, flags);
1685
1686 return left;
1687 }
1688
1689 /*
1690 * Pauses a transfer without losing data. Enables power save.
1691 * Use this function in conjunction with coh901318_resume.
1692 */
coh901318_pause(struct dma_chan * chan)1693 static int coh901318_pause(struct dma_chan *chan)
1694 {
1695 u32 val;
1696 unsigned long flags;
1697 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1698 int channel = cohc->id;
1699 void __iomem *virtbase = cohc->base->virtbase;
1700
1701 spin_lock_irqsave(&cohc->lock, flags);
1702
1703 /* Disable channel in HW */
1704 val = readl(virtbase + COH901318_CX_CFG +
1705 COH901318_CX_CFG_SPACING * channel);
1706
1707 /* Stopping infinite transfer */
1708 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
1709 (val & COH901318_CX_CFG_CH_ENABLE))
1710 cohc->stopped = 1;
1711
1712
1713 val &= ~COH901318_CX_CFG_CH_ENABLE;
1714 /* Enable twice, HW bug work around */
1715 writel(val, virtbase + COH901318_CX_CFG +
1716 COH901318_CX_CFG_SPACING * channel);
1717 writel(val, virtbase + COH901318_CX_CFG +
1718 COH901318_CX_CFG_SPACING * channel);
1719
1720 /* Spin-wait for it to actually go inactive */
1721 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
1722 channel) & COH901318_CX_STAT_ACTIVE)
1723 cpu_relax();
1724
1725 /* Check if we stopped an active job */
1726 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
1727 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
1728 cohc->stopped = 1;
1729
1730 enable_powersave(cohc);
1731
1732 spin_unlock_irqrestore(&cohc->lock, flags);
1733 return 0;
1734 }
1735
1736 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
1737 Power save is handled.
1738 */
coh901318_resume(struct dma_chan * chan)1739 static int coh901318_resume(struct dma_chan *chan)
1740 {
1741 u32 val;
1742 unsigned long flags;
1743 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1744 int channel = cohc->id;
1745
1746 spin_lock_irqsave(&cohc->lock, flags);
1747
1748 disable_powersave(cohc);
1749
1750 if (cohc->stopped) {
1751 /* Enable channel in HW */
1752 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
1753 COH901318_CX_CFG_SPACING * channel);
1754
1755 val |= COH901318_CX_CFG_CH_ENABLE;
1756
1757 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
1758 COH901318_CX_CFG_SPACING*channel);
1759
1760 cohc->stopped = 0;
1761 }
1762
1763 spin_unlock_irqrestore(&cohc->lock, flags);
1764 return 0;
1765 }
1766
coh901318_filter_id(struct dma_chan * chan,void * chan_id)1767 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
1768 {
1769 unsigned int ch_nr = (unsigned int) chan_id;
1770
1771 if (ch_nr == to_coh901318_chan(chan)->id)
1772 return true;
1773
1774 return false;
1775 }
1776 EXPORT_SYMBOL(coh901318_filter_id);
1777
1778 struct coh901318_filter_args {
1779 struct coh901318_base *base;
1780 unsigned int ch_nr;
1781 };
1782
coh901318_filter_base_and_id(struct dma_chan * chan,void * data)1783 static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
1784 {
1785 struct coh901318_filter_args *args = data;
1786
1787 if (&args->base->dma_slave == chan->device &&
1788 args->ch_nr == to_coh901318_chan(chan)->id)
1789 return true;
1790
1791 return false;
1792 }
1793
coh901318_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1794 static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
1795 struct of_dma *ofdma)
1796 {
1797 struct coh901318_filter_args args = {
1798 .base = ofdma->of_dma_data,
1799 .ch_nr = dma_spec->args[0],
1800 };
1801 dma_cap_mask_t cap;
1802 dma_cap_zero(cap);
1803 dma_cap_set(DMA_SLAVE, cap);
1804
1805 return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
1806 }
1807 /*
1808 * DMA channel allocation
1809 */
coh901318_config(struct coh901318_chan * cohc,struct coh901318_params * param)1810 static int coh901318_config(struct coh901318_chan *cohc,
1811 struct coh901318_params *param)
1812 {
1813 const struct coh901318_params *p;
1814 int channel = cohc->id;
1815 void __iomem *virtbase = cohc->base->virtbase;
1816
1817 if (param)
1818 p = param;
1819 else
1820 p = cohc_chan_param(cohc);
1821
1822 /* Clear any pending BE or TC interrupt */
1823 if (channel < 32) {
1824 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
1825 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
1826 } else {
1827 writel(1 << (channel - 32), virtbase +
1828 COH901318_BE_INT_CLEAR2);
1829 writel(1 << (channel - 32), virtbase +
1830 COH901318_TC_INT_CLEAR2);
1831 }
1832
1833 coh901318_set_conf(cohc, p->config);
1834 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
1835
1836 return 0;
1837 }
1838
1839 /* must lock when calling this function
1840 * start queued jobs, if any
1841 * TODO: start all queued jobs in one go
1842 *
1843 * Returns descriptor if queued job is started otherwise NULL.
1844 * If the queue is empty NULL is returned.
1845 */
coh901318_queue_start(struct coh901318_chan * cohc)1846 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
1847 {
1848 struct coh901318_desc *cohd;
1849
1850 /*
1851 * start queued jobs, if any
1852 * TODO: transmit all queued jobs in one go
1853 */
1854 cohd = coh901318_first_queued(cohc);
1855
1856 if (cohd != NULL) {
1857 /* Remove from queue */
1858 coh901318_desc_remove(cohd);
1859 /* initiate DMA job */
1860 cohc->busy = 1;
1861
1862 coh901318_desc_submit(cohc, cohd);
1863
1864 /* Program the transaction head */
1865 coh901318_set_conf(cohc, cohd->head_config);
1866 coh901318_set_ctrl(cohc, cohd->head_ctrl);
1867 coh901318_prep_linked_list(cohc, cohd->lli);
1868
1869 /* start dma job on this channel */
1870 coh901318_start(cohc);
1871
1872 }
1873
1874 return cohd;
1875 }
1876
1877 /*
1878 * This tasklet is called from the interrupt handler to
1879 * handle each descriptor (DMA job) that is sent to a channel.
1880 */
dma_tasklet(unsigned long data)1881 static void dma_tasklet(unsigned long data)
1882 {
1883 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
1884 struct coh901318_desc *cohd_fin;
1885 unsigned long flags;
1886 dma_async_tx_callback callback;
1887 void *callback_param;
1888
1889 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
1890 " nbr_active_done %ld\n", __func__,
1891 cohc->id, cohc->nbr_active_done);
1892
1893 spin_lock_irqsave(&cohc->lock, flags);
1894
1895 /* get first active descriptor entry from list */
1896 cohd_fin = coh901318_first_active_get(cohc);
1897
1898 if (cohd_fin == NULL)
1899 goto err;
1900
1901 /* locate callback to client */
1902 callback = cohd_fin->desc.callback;
1903 callback_param = cohd_fin->desc.callback_param;
1904
1905 /* sign this job as completed on the channel */
1906 dma_cookie_complete(&cohd_fin->desc);
1907
1908 /* release the lli allocation and remove the descriptor */
1909 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
1910
1911 /* return desc to free-list */
1912 coh901318_desc_remove(cohd_fin);
1913 coh901318_desc_free(cohc, cohd_fin);
1914
1915 spin_unlock_irqrestore(&cohc->lock, flags);
1916
1917 /* Call the callback when we're done */
1918 if (callback)
1919 callback(callback_param);
1920
1921 spin_lock_irqsave(&cohc->lock, flags);
1922
1923 /*
1924 * If another interrupt fired while the tasklet was scheduling,
1925 * we don't get called twice, so we have this number of active
1926 * counter that keep track of the number of IRQs expected to
1927 * be handled for this channel. If there happen to be more than
1928 * one IRQ to be ack:ed, we simply schedule this tasklet again.
1929 */
1930 cohc->nbr_active_done--;
1931 if (cohc->nbr_active_done) {
1932 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
1933 "came in while we were scheduling this tasklet\n");
1934 if (cohc_chan_conf(cohc)->priority_high)
1935 tasklet_hi_schedule(&cohc->tasklet);
1936 else
1937 tasklet_schedule(&cohc->tasklet);
1938 }
1939
1940 spin_unlock_irqrestore(&cohc->lock, flags);
1941
1942 return;
1943
1944 err:
1945 spin_unlock_irqrestore(&cohc->lock, flags);
1946 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
1947 }
1948
1949
1950 /* called from interrupt context */
dma_tc_handle(struct coh901318_chan * cohc)1951 static void dma_tc_handle(struct coh901318_chan *cohc)
1952 {
1953 /*
1954 * If the channel is not allocated, then we shouldn't have
1955 * any TC interrupts on it.
1956 */
1957 if (!cohc->allocated) {
1958 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
1959 "unallocated channel\n");
1960 return;
1961 }
1962
1963 /*
1964 * When we reach this point, at least one queue item
1965 * should have been moved over from cohc->queue to
1966 * cohc->active and run to completion, that is why we're
1967 * getting a terminal count interrupt is it not?
1968 * If you get this BUG() the most probable cause is that
1969 * the individual nodes in the lli chain have IRQ enabled,
1970 * so check your platform config for lli chain ctrl.
1971 */
1972 BUG_ON(list_empty(&cohc->active));
1973
1974 cohc->nbr_active_done++;
1975
1976 /*
1977 * This attempt to take a job from cohc->queue, put it
1978 * into cohc->active and start it.
1979 */
1980 if (coh901318_queue_start(cohc) == NULL)
1981 cohc->busy = 0;
1982
1983 /*
1984 * This tasklet will remove items from cohc->active
1985 * and thus terminates them.
1986 */
1987 if (cohc_chan_conf(cohc)->priority_high)
1988 tasklet_hi_schedule(&cohc->tasklet);
1989 else
1990 tasklet_schedule(&cohc->tasklet);
1991 }
1992
1993
dma_irq_handler(int irq,void * dev_id)1994 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
1995 {
1996 u32 status1;
1997 u32 status2;
1998 int i;
1999 int ch;
2000 struct coh901318_base *base = dev_id;
2001 struct coh901318_chan *cohc;
2002 void __iomem *virtbase = base->virtbase;
2003
2004 status1 = readl(virtbase + COH901318_INT_STATUS1);
2005 status2 = readl(virtbase + COH901318_INT_STATUS2);
2006
2007 if (unlikely(status1 == 0 && status2 == 0)) {
2008 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
2009 return IRQ_HANDLED;
2010 }
2011
2012 /* TODO: consider handle IRQ in tasklet here to
2013 * minimize interrupt latency */
2014
2015 /* Check the first 32 DMA channels for IRQ */
2016 while (status1) {
2017 /* Find first bit set, return as a number. */
2018 i = ffs(status1) - 1;
2019 ch = i;
2020
2021 cohc = &base->chans[ch];
2022 spin_lock(&cohc->lock);
2023
2024 /* Mask off this bit */
2025 status1 &= ~(1 << i);
2026 /* Check the individual channel bits */
2027 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
2028 dev_crit(COHC_2_DEV(cohc),
2029 "DMA bus error on channel %d!\n", ch);
2030 BUG_ON(1);
2031 /* Clear BE interrupt */
2032 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
2033 } else {
2034 /* Caused by TC, really? */
2035 if (unlikely(!test_bit(i, virtbase +
2036 COH901318_TC_INT_STATUS1))) {
2037 dev_warn(COHC_2_DEV(cohc),
2038 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2039 /* Clear TC interrupt */
2040 BUG_ON(1);
2041 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2042 } else {
2043 /* Enable powersave if transfer has finished */
2044 if (!(readl(virtbase + COH901318_CX_STAT +
2045 COH901318_CX_STAT_SPACING*ch) &
2046 COH901318_CX_STAT_ENABLED)) {
2047 enable_powersave(cohc);
2048 }
2049
2050 /* Must clear TC interrupt before calling
2051 * dma_tc_handle
2052 * in case tc_handle initiate a new dma job
2053 */
2054 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2055
2056 dma_tc_handle(cohc);
2057 }
2058 }
2059 spin_unlock(&cohc->lock);
2060 }
2061
2062 /* Check the remaining 32 DMA channels for IRQ */
2063 while (status2) {
2064 /* Find first bit set, return as a number. */
2065 i = ffs(status2) - 1;
2066 ch = i + 32;
2067 cohc = &base->chans[ch];
2068 spin_lock(&cohc->lock);
2069
2070 /* Mask off this bit */
2071 status2 &= ~(1 << i);
2072 /* Check the individual channel bits */
2073 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
2074 dev_crit(COHC_2_DEV(cohc),
2075 "DMA bus error on channel %d!\n", ch);
2076 /* Clear BE interrupt */
2077 BUG_ON(1);
2078 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
2079 } else {
2080 /* Caused by TC, really? */
2081 if (unlikely(!test_bit(i, virtbase +
2082 COH901318_TC_INT_STATUS2))) {
2083 dev_warn(COHC_2_DEV(cohc),
2084 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2085 /* Clear TC interrupt */
2086 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2087 BUG_ON(1);
2088 } else {
2089 /* Enable powersave if transfer has finished */
2090 if (!(readl(virtbase + COH901318_CX_STAT +
2091 COH901318_CX_STAT_SPACING*ch) &
2092 COH901318_CX_STAT_ENABLED)) {
2093 enable_powersave(cohc);
2094 }
2095 /* Must clear TC interrupt before calling
2096 * dma_tc_handle
2097 * in case tc_handle initiate a new dma job
2098 */
2099 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2100
2101 dma_tc_handle(cohc);
2102 }
2103 }
2104 spin_unlock(&cohc->lock);
2105 }
2106
2107 return IRQ_HANDLED;
2108 }
2109
coh901318_terminate_all(struct dma_chan * chan)2110 static int coh901318_terminate_all(struct dma_chan *chan)
2111 {
2112 unsigned long flags;
2113 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2114 struct coh901318_desc *cohd;
2115 void __iomem *virtbase = cohc->base->virtbase;
2116
2117 /* The remainder of this function terminates the transfer */
2118 coh901318_pause(chan);
2119 spin_lock_irqsave(&cohc->lock, flags);
2120
2121 /* Clear any pending BE or TC interrupt */
2122 if (cohc->id < 32) {
2123 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
2124 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
2125 } else {
2126 writel(1 << (cohc->id - 32), virtbase +
2127 COH901318_BE_INT_CLEAR2);
2128 writel(1 << (cohc->id - 32), virtbase +
2129 COH901318_TC_INT_CLEAR2);
2130 }
2131
2132 enable_powersave(cohc);
2133
2134 while ((cohd = coh901318_first_active_get(cohc))) {
2135 /* release the lli allocation*/
2136 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
2137
2138 /* return desc to free-list */
2139 coh901318_desc_remove(cohd);
2140 coh901318_desc_free(cohc, cohd);
2141 }
2142
2143 while ((cohd = coh901318_first_queued(cohc))) {
2144 /* release the lli allocation*/
2145 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
2146
2147 /* return desc to free-list */
2148 coh901318_desc_remove(cohd);
2149 coh901318_desc_free(cohc, cohd);
2150 }
2151
2152
2153 cohc->nbr_active_done = 0;
2154 cohc->busy = 0;
2155
2156 spin_unlock_irqrestore(&cohc->lock, flags);
2157
2158 return 0;
2159 }
2160
coh901318_alloc_chan_resources(struct dma_chan * chan)2161 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
2162 {
2163 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2164 unsigned long flags;
2165
2166 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
2167 __func__, cohc->id);
2168
2169 if (chan->client_count > 1)
2170 return -EBUSY;
2171
2172 spin_lock_irqsave(&cohc->lock, flags);
2173
2174 coh901318_config(cohc, NULL);
2175
2176 cohc->allocated = 1;
2177 dma_cookie_init(chan);
2178
2179 spin_unlock_irqrestore(&cohc->lock, flags);
2180
2181 return 1;
2182 }
2183
2184 static void
coh901318_free_chan_resources(struct dma_chan * chan)2185 coh901318_free_chan_resources(struct dma_chan *chan)
2186 {
2187 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2188 int channel = cohc->id;
2189 unsigned long flags;
2190
2191 spin_lock_irqsave(&cohc->lock, flags);
2192
2193 /* Disable HW */
2194 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
2195 COH901318_CX_CFG_SPACING*channel);
2196 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
2197 COH901318_CX_CTRL_SPACING*channel);
2198
2199 cohc->allocated = 0;
2200
2201 spin_unlock_irqrestore(&cohc->lock, flags);
2202
2203 coh901318_terminate_all(chan);
2204 }
2205
2206
2207 static dma_cookie_t
coh901318_tx_submit(struct dma_async_tx_descriptor * tx)2208 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
2209 {
2210 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
2211 desc);
2212 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
2213 unsigned long flags;
2214 dma_cookie_t cookie;
2215
2216 spin_lock_irqsave(&cohc->lock, flags);
2217 cookie = dma_cookie_assign(tx);
2218
2219 coh901318_desc_queue(cohc, cohd);
2220
2221 spin_unlock_irqrestore(&cohc->lock, flags);
2222
2223 return cookie;
2224 }
2225
2226 static struct dma_async_tx_descriptor *
coh901318_prep_memcpy(struct dma_chan * chan,dma_addr_t dest,dma_addr_t src,size_t size,unsigned long flags)2227 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
2228 size_t size, unsigned long flags)
2229 {
2230 struct coh901318_lli *lli;
2231 struct coh901318_desc *cohd;
2232 unsigned long flg;
2233 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2234 int lli_len;
2235 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
2236 int ret;
2237
2238 spin_lock_irqsave(&cohc->lock, flg);
2239
2240 dev_vdbg(COHC_2_DEV(cohc),
2241 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
2242 __func__, cohc->id, src, dest, size);
2243
2244 if (flags & DMA_PREP_INTERRUPT)
2245 /* Trigger interrupt after last lli */
2246 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2247
2248 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2249 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2250 lli_len++;
2251
2252 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
2253
2254 if (lli == NULL)
2255 goto err;
2256
2257 ret = coh901318_lli_fill_memcpy(
2258 &cohc->base->pool, lli, src, size, dest,
2259 cohc_chan_param(cohc)->ctrl_lli_chained,
2260 ctrl_last);
2261 if (ret)
2262 goto err;
2263
2264 COH_DBG(coh901318_list_print(cohc, lli));
2265
2266 /* Pick a descriptor to handle this transfer */
2267 cohd = coh901318_desc_get(cohc);
2268 cohd->lli = lli;
2269 cohd->flags = flags;
2270 cohd->desc.tx_submit = coh901318_tx_submit;
2271
2272 spin_unlock_irqrestore(&cohc->lock, flg);
2273
2274 return &cohd->desc;
2275 err:
2276 spin_unlock_irqrestore(&cohc->lock, flg);
2277 return NULL;
2278 }
2279
2280 static struct dma_async_tx_descriptor *
coh901318_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)2281 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2282 unsigned int sg_len, enum dma_transfer_direction direction,
2283 unsigned long flags, void *context)
2284 {
2285 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2286 struct coh901318_lli *lli;
2287 struct coh901318_desc *cohd;
2288 const struct coh901318_params *params;
2289 struct scatterlist *sg;
2290 int len = 0;
2291 int size;
2292 int i;
2293 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
2294 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
2295 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
2296 u32 config;
2297 unsigned long flg;
2298 int ret;
2299
2300 if (!sgl)
2301 goto out;
2302 if (sg_dma_len(sgl) == 0)
2303 goto out;
2304
2305 spin_lock_irqsave(&cohc->lock, flg);
2306
2307 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
2308 __func__, sg_len, direction);
2309
2310 if (flags & DMA_PREP_INTERRUPT)
2311 /* Trigger interrupt after last lli */
2312 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2313
2314 params = cohc_chan_param(cohc);
2315 config = params->config;
2316 /*
2317 * Add runtime-specific control on top, make
2318 * sure the bits you set per peripheral channel are
2319 * cleared in the default config from the platform.
2320 */
2321 ctrl_chained |= cohc->ctrl;
2322 ctrl_last |= cohc->ctrl;
2323 ctrl |= cohc->ctrl;
2324
2325 if (direction == DMA_MEM_TO_DEV) {
2326 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
2327 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
2328
2329 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
2330 ctrl_chained |= tx_flags;
2331 ctrl_last |= tx_flags;
2332 ctrl |= tx_flags;
2333 } else if (direction == DMA_DEV_TO_MEM) {
2334 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
2335 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
2336
2337 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
2338 ctrl_chained |= rx_flags;
2339 ctrl_last |= rx_flags;
2340 ctrl |= rx_flags;
2341 } else
2342 goto err_direction;
2343
2344 /* The dma only supports transmitting packages up to
2345 * MAX_DMA_PACKET_SIZE. Calculate to total number of
2346 * dma elemts required to send the entire sg list
2347 */
2348 for_each_sg(sgl, sg, sg_len, i) {
2349 unsigned int factor;
2350 size = sg_dma_len(sg);
2351
2352 if (size <= MAX_DMA_PACKET_SIZE) {
2353 len++;
2354 continue;
2355 }
2356
2357 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2358 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2359 factor++;
2360
2361 len += factor;
2362 }
2363
2364 pr_debug("Allocate %d lli:s for this transfer\n", len);
2365 lli = coh901318_lli_alloc(&cohc->base->pool, len);
2366
2367 if (lli == NULL)
2368 goto err_dma_alloc;
2369
2370 /* initiate allocated lli list */
2371 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
2372 cohc->addr,
2373 ctrl_chained,
2374 ctrl,
2375 ctrl_last,
2376 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
2377 if (ret)
2378 goto err_lli_fill;
2379
2380
2381 COH_DBG(coh901318_list_print(cohc, lli));
2382
2383 /* Pick a descriptor to handle this transfer */
2384 cohd = coh901318_desc_get(cohc);
2385 cohd->head_config = config;
2386 /*
2387 * Set the default head ctrl for the channel to the one from the
2388 * lli, things may have changed due to odd buffer alignment
2389 * etc.
2390 */
2391 cohd->head_ctrl = lli->control;
2392 cohd->dir = direction;
2393 cohd->flags = flags;
2394 cohd->desc.tx_submit = coh901318_tx_submit;
2395 cohd->lli = lli;
2396
2397 spin_unlock_irqrestore(&cohc->lock, flg);
2398
2399 return &cohd->desc;
2400 err_lli_fill:
2401 err_dma_alloc:
2402 err_direction:
2403 spin_unlock_irqrestore(&cohc->lock, flg);
2404 out:
2405 return NULL;
2406 }
2407
2408 static enum dma_status
coh901318_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)2409 coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2410 struct dma_tx_state *txstate)
2411 {
2412 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2413 enum dma_status ret;
2414
2415 ret = dma_cookie_status(chan, cookie, txstate);
2416 if (ret == DMA_COMPLETE)
2417 return ret;
2418
2419 dma_set_residue(txstate, coh901318_get_bytes_left(chan));
2420
2421 if (ret == DMA_IN_PROGRESS && cohc->stopped)
2422 ret = DMA_PAUSED;
2423
2424 return ret;
2425 }
2426
2427 static void
coh901318_issue_pending(struct dma_chan * chan)2428 coh901318_issue_pending(struct dma_chan *chan)
2429 {
2430 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2431 unsigned long flags;
2432
2433 spin_lock_irqsave(&cohc->lock, flags);
2434
2435 /*
2436 * Busy means that pending jobs are already being processed,
2437 * and then there is no point in starting the queue: the
2438 * terminal count interrupt on the channel will take the next
2439 * job on the queue and execute it anyway.
2440 */
2441 if (!cohc->busy)
2442 coh901318_queue_start(cohc);
2443
2444 spin_unlock_irqrestore(&cohc->lock, flags);
2445 }
2446
2447 /*
2448 * Here we wrap in the runtime dma control interface
2449 */
2450 struct burst_table {
2451 int burst_8bit;
2452 int burst_16bit;
2453 int burst_32bit;
2454 u32 reg;
2455 };
2456
2457 static const struct burst_table burst_sizes[] = {
2458 {
2459 .burst_8bit = 64,
2460 .burst_16bit = 32,
2461 .burst_32bit = 16,
2462 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
2463 },
2464 {
2465 .burst_8bit = 48,
2466 .burst_16bit = 24,
2467 .burst_32bit = 12,
2468 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
2469 },
2470 {
2471 .burst_8bit = 32,
2472 .burst_16bit = 16,
2473 .burst_32bit = 8,
2474 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
2475 },
2476 {
2477 .burst_8bit = 16,
2478 .burst_16bit = 8,
2479 .burst_32bit = 4,
2480 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
2481 },
2482 {
2483 .burst_8bit = 8,
2484 .burst_16bit = 4,
2485 .burst_32bit = 2,
2486 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
2487 },
2488 {
2489 .burst_8bit = 4,
2490 .burst_16bit = 2,
2491 .burst_32bit = 1,
2492 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
2493 },
2494 {
2495 .burst_8bit = 2,
2496 .burst_16bit = 1,
2497 .burst_32bit = 0,
2498 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
2499 },
2500 {
2501 .burst_8bit = 1,
2502 .burst_16bit = 0,
2503 .burst_32bit = 0,
2504 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
2505 },
2506 };
2507
coh901318_dma_set_runtimeconfig(struct dma_chan * chan,struct dma_slave_config * config)2508 static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2509 struct dma_slave_config *config)
2510 {
2511 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2512 dma_addr_t addr;
2513 enum dma_slave_buswidth addr_width;
2514 u32 maxburst;
2515 u32 ctrl = 0;
2516 int i = 0;
2517
2518 /* We only support mem to per or per to mem transfers */
2519 if (config->direction == DMA_DEV_TO_MEM) {
2520 addr = config->src_addr;
2521 addr_width = config->src_addr_width;
2522 maxburst = config->src_maxburst;
2523 } else if (config->direction == DMA_MEM_TO_DEV) {
2524 addr = config->dst_addr;
2525 addr_width = config->dst_addr_width;
2526 maxburst = config->dst_maxburst;
2527 } else {
2528 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
2529 return -EINVAL;
2530 }
2531
2532 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
2533 addr_width);
2534 switch (addr_width) {
2535 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2536 ctrl |=
2537 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
2538 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
2539
2540 while (i < ARRAY_SIZE(burst_sizes)) {
2541 if (burst_sizes[i].burst_8bit <= maxburst)
2542 break;
2543 i++;
2544 }
2545
2546 break;
2547 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2548 ctrl |=
2549 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
2550 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
2551
2552 while (i < ARRAY_SIZE(burst_sizes)) {
2553 if (burst_sizes[i].burst_16bit <= maxburst)
2554 break;
2555 i++;
2556 }
2557
2558 break;
2559 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2560 /* Direction doesn't matter here, it's 32/32 bits */
2561 ctrl |=
2562 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
2563 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
2564
2565 while (i < ARRAY_SIZE(burst_sizes)) {
2566 if (burst_sizes[i].burst_32bit <= maxburst)
2567 break;
2568 i++;
2569 }
2570
2571 break;
2572 default:
2573 dev_err(COHC_2_DEV(cohc),
2574 "bad runtimeconfig: alien address width\n");
2575 return -EINVAL;
2576 }
2577
2578 ctrl |= burst_sizes[i].reg;
2579 dev_dbg(COHC_2_DEV(cohc),
2580 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
2581 burst_sizes[i].burst_8bit, addr_width, maxburst);
2582
2583 cohc->addr = addr;
2584 cohc->ctrl = ctrl;
2585
2586 return 0;
2587 }
2588
coh901318_base_init(struct dma_device * dma,const int * pick_chans,struct coh901318_base * base)2589 static void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
2590 struct coh901318_base *base)
2591 {
2592 int chans_i;
2593 int i = 0;
2594 struct coh901318_chan *cohc;
2595
2596 INIT_LIST_HEAD(&dma->channels);
2597
2598 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
2599 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
2600 cohc = &base->chans[i];
2601
2602 cohc->base = base;
2603 cohc->chan.device = dma;
2604 cohc->id = i;
2605
2606 /* TODO: do we really need this lock if only one
2607 * client is connected to each channel?
2608 */
2609
2610 spin_lock_init(&cohc->lock);
2611
2612 cohc->nbr_active_done = 0;
2613 cohc->busy = 0;
2614 INIT_LIST_HEAD(&cohc->free);
2615 INIT_LIST_HEAD(&cohc->active);
2616 INIT_LIST_HEAD(&cohc->queue);
2617
2618 tasklet_init(&cohc->tasklet, dma_tasklet,
2619 (unsigned long) cohc);
2620
2621 list_add_tail(&cohc->chan.device_node,
2622 &dma->channels);
2623 }
2624 }
2625 }
2626
coh901318_probe(struct platform_device * pdev)2627 static int __init coh901318_probe(struct platform_device *pdev)
2628 {
2629 int err = 0;
2630 struct coh901318_base *base;
2631 int irq;
2632 struct resource *io;
2633
2634 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2635 if (!io)
2636 return -ENODEV;
2637
2638 /* Map DMA controller registers to virtual memory */
2639 if (devm_request_mem_region(&pdev->dev,
2640 io->start,
2641 resource_size(io),
2642 pdev->dev.driver->name) == NULL)
2643 return -ENOMEM;
2644
2645 base = devm_kzalloc(&pdev->dev,
2646 ALIGN(sizeof(struct coh901318_base), 4) +
2647 U300_DMA_CHANNELS *
2648 sizeof(struct coh901318_chan),
2649 GFP_KERNEL);
2650 if (!base)
2651 return -ENOMEM;
2652
2653 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
2654
2655 base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
2656 if (!base->virtbase)
2657 return -ENOMEM;
2658
2659 base->dev = &pdev->dev;
2660 spin_lock_init(&base->pm.lock);
2661 base->pm.started_channels = 0;
2662
2663 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
2664
2665 irq = platform_get_irq(pdev, 0);
2666 if (irq < 0)
2667 return irq;
2668
2669 err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 0,
2670 "coh901318", base);
2671 if (err)
2672 return err;
2673
2674 err = coh901318_pool_create(&base->pool, &pdev->dev,
2675 sizeof(struct coh901318_lli),
2676 32);
2677 if (err)
2678 return err;
2679
2680 /* init channels for device transfers */
2681 coh901318_base_init(&base->dma_slave, dma_slave_channels,
2682 base);
2683
2684 dma_cap_zero(base->dma_slave.cap_mask);
2685 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2686
2687 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2688 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
2689 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
2690 base->dma_slave.device_tx_status = coh901318_tx_status;
2691 base->dma_slave.device_issue_pending = coh901318_issue_pending;
2692 base->dma_slave.device_config = coh901318_dma_set_runtimeconfig;
2693 base->dma_slave.device_pause = coh901318_pause;
2694 base->dma_slave.device_resume = coh901318_resume;
2695 base->dma_slave.device_terminate_all = coh901318_terminate_all;
2696 base->dma_slave.dev = &pdev->dev;
2697
2698 err = dma_async_device_register(&base->dma_slave);
2699
2700 if (err)
2701 goto err_register_slave;
2702
2703 /* init channels for memcpy */
2704 coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels,
2705 base);
2706
2707 dma_cap_zero(base->dma_memcpy.cap_mask);
2708 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2709
2710 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2711 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
2712 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
2713 base->dma_memcpy.device_tx_status = coh901318_tx_status;
2714 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
2715 base->dma_memcpy.device_config = coh901318_dma_set_runtimeconfig;
2716 base->dma_memcpy.device_pause = coh901318_pause;
2717 base->dma_memcpy.device_resume = coh901318_resume;
2718 base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
2719 base->dma_memcpy.dev = &pdev->dev;
2720 /*
2721 * This controller can only access address at even 32bit boundaries,
2722 * i.e. 2^2
2723 */
2724 base->dma_memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES;
2725 err = dma_async_device_register(&base->dma_memcpy);
2726
2727 if (err)
2728 goto err_register_memcpy;
2729
2730 err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
2731 base);
2732 if (err)
2733 goto err_register_of_dma;
2734
2735 platform_set_drvdata(pdev, base);
2736 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
2737 (u32) base->virtbase);
2738
2739 return err;
2740
2741 err_register_of_dma:
2742 dma_async_device_unregister(&base->dma_memcpy);
2743 err_register_memcpy:
2744 dma_async_device_unregister(&base->dma_slave);
2745 err_register_slave:
2746 coh901318_pool_destroy(&base->pool);
2747 return err;
2748 }
2749
coh901318_remove(struct platform_device * pdev)2750 static int coh901318_remove(struct platform_device *pdev)
2751 {
2752 struct coh901318_base *base = platform_get_drvdata(pdev);
2753
2754 of_dma_controller_free(pdev->dev.of_node);
2755 dma_async_device_unregister(&base->dma_memcpy);
2756 dma_async_device_unregister(&base->dma_slave);
2757 coh901318_pool_destroy(&base->pool);
2758 return 0;
2759 }
2760
2761 static const struct of_device_id coh901318_dt_match[] = {
2762 { .compatible = "stericsson,coh901318" },
2763 {},
2764 };
2765
2766 static struct platform_driver coh901318_driver = {
2767 .remove = coh901318_remove,
2768 .driver = {
2769 .name = "coh901318",
2770 .of_match_table = coh901318_dt_match,
2771 },
2772 };
2773
coh901318_init(void)2774 int __init coh901318_init(void)
2775 {
2776 return platform_driver_probe(&coh901318_driver, coh901318_probe);
2777 }
2778 subsys_initcall(coh901318_init);
2779
coh901318_exit(void)2780 void __exit coh901318_exit(void)
2781 {
2782 platform_driver_unregister(&coh901318_driver);
2783 }
2784 module_exit(coh901318_exit);
2785
2786 MODULE_LICENSE("GPL");
2787 MODULE_AUTHOR("Per Friden");
2788