1 /*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 * Copyright (C) 2013 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/freezer.h>
17 #include <linux/init.h>
18 #include <linux/kthread.h>
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/random.h>
22 #include <linux/slab.h>
23 #include <linux/wait.h>
24
25 static unsigned int test_buf_size = 16384;
26 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
27 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
28
29 static char test_channel[20];
30 module_param_string(channel, test_channel, sizeof(test_channel),
31 S_IRUGO | S_IWUSR);
32 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
33
34 static char test_device[32];
35 module_param_string(device, test_device, sizeof(test_device),
36 S_IRUGO | S_IWUSR);
37 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
38
39 static unsigned int threads_per_chan = 1;
40 module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
41 MODULE_PARM_DESC(threads_per_chan,
42 "Number of threads to start per channel (default: 1)");
43
44 static unsigned int max_channels;
45 module_param(max_channels, uint, S_IRUGO | S_IWUSR);
46 MODULE_PARM_DESC(max_channels,
47 "Maximum number of channels to use (default: all)");
48
49 static unsigned int iterations;
50 module_param(iterations, uint, S_IRUGO | S_IWUSR);
51 MODULE_PARM_DESC(iterations,
52 "Iterations before stopping test (default: infinite)");
53
54 static unsigned int xor_sources = 3;
55 module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
56 MODULE_PARM_DESC(xor_sources,
57 "Number of xor source buffers (default: 3)");
58
59 static unsigned int pq_sources = 3;
60 module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
61 MODULE_PARM_DESC(pq_sources,
62 "Number of p+q source buffers (default: 3)");
63
64 static int timeout = 3000;
65 module_param(timeout, uint, S_IRUGO | S_IWUSR);
66 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
67 "Pass -1 for infinite timeout");
68
69 static bool noverify;
70 module_param(noverify, bool, S_IRUGO | S_IWUSR);
71 MODULE_PARM_DESC(noverify, "Disable random data setup and verification");
72
73 static bool verbose;
74 module_param(verbose, bool, S_IRUGO | S_IWUSR);
75 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
76
77 /**
78 * struct dmatest_params - test parameters.
79 * @buf_size: size of the memcpy test buffer
80 * @channel: bus ID of the channel to test
81 * @device: bus ID of the DMA Engine to test
82 * @threads_per_chan: number of threads to start per channel
83 * @max_channels: maximum number of channels to use
84 * @iterations: iterations before stopping test
85 * @xor_sources: number of xor source buffers
86 * @pq_sources: number of p+q source buffers
87 * @timeout: transfer timeout in msec, -1 for infinite timeout
88 */
89 struct dmatest_params {
90 unsigned int buf_size;
91 char channel[20];
92 char device[32];
93 unsigned int threads_per_chan;
94 unsigned int max_channels;
95 unsigned int iterations;
96 unsigned int xor_sources;
97 unsigned int pq_sources;
98 int timeout;
99 bool noverify;
100 };
101
102 /**
103 * struct dmatest_info - test information.
104 * @params: test parameters
105 * @lock: access protection to the fields of this structure
106 */
107 static struct dmatest_info {
108 /* Test parameters */
109 struct dmatest_params params;
110
111 /* Internal state */
112 struct list_head channels;
113 unsigned int nr_channels;
114 struct mutex lock;
115 bool did_init;
116 } test_info = {
117 .channels = LIST_HEAD_INIT(test_info.channels),
118 .lock = __MUTEX_INITIALIZER(test_info.lock),
119 };
120
121 static int dmatest_run_set(const char *val, const struct kernel_param *kp);
122 static int dmatest_run_get(char *val, const struct kernel_param *kp);
123 static const struct kernel_param_ops run_ops = {
124 .set = dmatest_run_set,
125 .get = dmatest_run_get,
126 };
127 static bool dmatest_run;
128 module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
129 MODULE_PARM_DESC(run, "Run the test (default: false)");
130
131 /* Maximum amount of mismatched bytes in buffer to print */
132 #define MAX_ERROR_COUNT 32
133
134 /*
135 * Initialization patterns. All bytes in the source buffer has bit 7
136 * set, all bytes in the destination buffer has bit 7 cleared.
137 *
138 * Bit 6 is set for all bytes which are to be copied by the DMA
139 * engine. Bit 5 is set for all bytes which are to be overwritten by
140 * the DMA engine.
141 *
142 * The remaining bits are the inverse of a counter which increments by
143 * one for each byte address.
144 */
145 #define PATTERN_SRC 0x80
146 #define PATTERN_DST 0x00
147 #define PATTERN_COPY 0x40
148 #define PATTERN_OVERWRITE 0x20
149 #define PATTERN_COUNT_MASK 0x1f
150
151 /* poor man's completion - we want to use wait_event_freezable() on it */
152 struct dmatest_done {
153 bool done;
154 wait_queue_head_t *wait;
155 };
156
157 struct dmatest_thread {
158 struct list_head node;
159 struct dmatest_info *info;
160 struct task_struct *task;
161 struct dma_chan *chan;
162 u8 **srcs;
163 u8 **dsts;
164 enum dma_transaction_type type;
165 wait_queue_head_t done_wait;
166 struct dmatest_done test_done;
167 bool done;
168 };
169
170 struct dmatest_chan {
171 struct list_head node;
172 struct dma_chan *chan;
173 struct list_head threads;
174 };
175
176 static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
177 static bool wait;
178
is_threaded_test_run(struct dmatest_info * info)179 static bool is_threaded_test_run(struct dmatest_info *info)
180 {
181 struct dmatest_chan *dtc;
182
183 list_for_each_entry(dtc, &info->channels, node) {
184 struct dmatest_thread *thread;
185
186 list_for_each_entry(thread, &dtc->threads, node) {
187 if (!thread->done)
188 return true;
189 }
190 }
191
192 return false;
193 }
194
dmatest_wait_get(char * val,const struct kernel_param * kp)195 static int dmatest_wait_get(char *val, const struct kernel_param *kp)
196 {
197 struct dmatest_info *info = &test_info;
198 struct dmatest_params *params = &info->params;
199
200 if (params->iterations)
201 wait_event(thread_wait, !is_threaded_test_run(info));
202 wait = true;
203 return param_get_bool(val, kp);
204 }
205
206 static const struct kernel_param_ops wait_ops = {
207 .get = dmatest_wait_get,
208 .set = param_set_bool,
209 };
210 module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
211 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
212
dmatest_match_channel(struct dmatest_params * params,struct dma_chan * chan)213 static bool dmatest_match_channel(struct dmatest_params *params,
214 struct dma_chan *chan)
215 {
216 if (params->channel[0] == '\0')
217 return true;
218 return strcmp(dma_chan_name(chan), params->channel) == 0;
219 }
220
dmatest_match_device(struct dmatest_params * params,struct dma_device * device)221 static bool dmatest_match_device(struct dmatest_params *params,
222 struct dma_device *device)
223 {
224 if (params->device[0] == '\0')
225 return true;
226 return strcmp(dev_name(device->dev), params->device) == 0;
227 }
228
dmatest_random(void)229 static unsigned long dmatest_random(void)
230 {
231 unsigned long buf;
232
233 prandom_bytes(&buf, sizeof(buf));
234 return buf;
235 }
236
dmatest_init_srcs(u8 ** bufs,unsigned int start,unsigned int len,unsigned int buf_size)237 static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
238 unsigned int buf_size)
239 {
240 unsigned int i;
241 u8 *buf;
242
243 for (; (buf = *bufs); bufs++) {
244 for (i = 0; i < start; i++)
245 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
246 for ( ; i < start + len; i++)
247 buf[i] = PATTERN_SRC | PATTERN_COPY
248 | (~i & PATTERN_COUNT_MASK);
249 for ( ; i < buf_size; i++)
250 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
251 buf++;
252 }
253 }
254
dmatest_init_dsts(u8 ** bufs,unsigned int start,unsigned int len,unsigned int buf_size)255 static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
256 unsigned int buf_size)
257 {
258 unsigned int i;
259 u8 *buf;
260
261 for (; (buf = *bufs); bufs++) {
262 for (i = 0; i < start; i++)
263 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
264 for ( ; i < start + len; i++)
265 buf[i] = PATTERN_DST | PATTERN_OVERWRITE
266 | (~i & PATTERN_COUNT_MASK);
267 for ( ; i < buf_size; i++)
268 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
269 }
270 }
271
dmatest_mismatch(u8 actual,u8 pattern,unsigned int index,unsigned int counter,bool is_srcbuf)272 static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
273 unsigned int counter, bool is_srcbuf)
274 {
275 u8 diff = actual ^ pattern;
276 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
277 const char *thread_name = current->comm;
278
279 if (is_srcbuf)
280 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
281 thread_name, index, expected, actual);
282 else if ((pattern & PATTERN_COPY)
283 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
284 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
285 thread_name, index, expected, actual);
286 else if (diff & PATTERN_SRC)
287 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
288 thread_name, index, expected, actual);
289 else
290 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
291 thread_name, index, expected, actual);
292 }
293
dmatest_verify(u8 ** bufs,unsigned int start,unsigned int end,unsigned int counter,u8 pattern,bool is_srcbuf)294 static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
295 unsigned int end, unsigned int counter, u8 pattern,
296 bool is_srcbuf)
297 {
298 unsigned int i;
299 unsigned int error_count = 0;
300 u8 actual;
301 u8 expected;
302 u8 *buf;
303 unsigned int counter_orig = counter;
304
305 for (; (buf = *bufs); bufs++) {
306 counter = counter_orig;
307 for (i = start; i < end; i++) {
308 actual = buf[i];
309 expected = pattern | (~counter & PATTERN_COUNT_MASK);
310 if (actual != expected) {
311 if (error_count < MAX_ERROR_COUNT)
312 dmatest_mismatch(actual, pattern, i,
313 counter, is_srcbuf);
314 error_count++;
315 }
316 counter++;
317 }
318 }
319
320 if (error_count > MAX_ERROR_COUNT)
321 pr_warn("%s: %u errors suppressed\n",
322 current->comm, error_count - MAX_ERROR_COUNT);
323
324 return error_count;
325 }
326
327
dmatest_callback(void * arg)328 static void dmatest_callback(void *arg)
329 {
330 struct dmatest_done *done = arg;
331 struct dmatest_thread *thread =
332 container_of(done, struct dmatest_thread, test_done);
333 if (!thread->done) {
334 done->done = true;
335 wake_up_all(done->wait);
336 } else {
337 /*
338 * If thread->done, it means that this callback occurred
339 * after the parent thread has cleaned up. This can
340 * happen in the case that driver doesn't implement
341 * the terminate_all() functionality and a dma operation
342 * did not occur within the timeout period
343 */
344 WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
345 }
346 }
347
min_odd(unsigned int x,unsigned int y)348 static unsigned int min_odd(unsigned int x, unsigned int y)
349 {
350 unsigned int val = min(x, y);
351
352 return val % 2 ? val : val - 1;
353 }
354
result(const char * err,unsigned int n,unsigned int src_off,unsigned int dst_off,unsigned int len,unsigned long data)355 static void result(const char *err, unsigned int n, unsigned int src_off,
356 unsigned int dst_off, unsigned int len, unsigned long data)
357 {
358 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
359 current->comm, n, err, src_off, dst_off, len, data);
360 }
361
dbg_result(const char * err,unsigned int n,unsigned int src_off,unsigned int dst_off,unsigned int len,unsigned long data)362 static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
363 unsigned int dst_off, unsigned int len,
364 unsigned long data)
365 {
366 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
367 current->comm, n, err, src_off, dst_off, len, data);
368 }
369
370 #define verbose_result(err, n, src_off, dst_off, len, data) ({ \
371 if (verbose) \
372 result(err, n, src_off, dst_off, len, data); \
373 else \
374 dbg_result(err, n, src_off, dst_off, len, data);\
375 })
376
dmatest_persec(s64 runtime,unsigned int val)377 static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
378 {
379 unsigned long long per_sec = 1000000;
380
381 if (runtime <= 0)
382 return 0;
383
384 /* drop precision until runtime is 32-bits */
385 while (runtime > UINT_MAX) {
386 runtime >>= 1;
387 per_sec <<= 1;
388 }
389
390 per_sec *= val;
391 do_div(per_sec, runtime);
392 return per_sec;
393 }
394
dmatest_KBs(s64 runtime,unsigned long long len)395 static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
396 {
397 return dmatest_persec(runtime, len >> 10);
398 }
399
400 /*
401 * This function repeatedly tests DMA transfers of various lengths and
402 * offsets for a given operation type until it is told to exit by
403 * kthread_stop(). There may be multiple threads running this function
404 * in parallel for a single channel, and there may be multiple channels
405 * being tested in parallel.
406 *
407 * Before each test, the source and destination buffer is initialized
408 * with a known pattern. This pattern is different depending on
409 * whether it's in an area which is supposed to be copied or
410 * overwritten, and different in the source and destination buffers.
411 * So if the DMA engine doesn't copy exactly what we tell it to copy,
412 * we'll notice.
413 */
dmatest_func(void * data)414 static int dmatest_func(void *data)
415 {
416 struct dmatest_thread *thread = data;
417 struct dmatest_done *done = &thread->test_done;
418 struct dmatest_info *info;
419 struct dmatest_params *params;
420 struct dma_chan *chan;
421 struct dma_device *dev;
422 unsigned int error_count;
423 unsigned int failed_tests = 0;
424 unsigned int total_tests = 0;
425 dma_cookie_t cookie;
426 enum dma_status status;
427 enum dma_ctrl_flags flags;
428 u8 *pq_coefs = NULL;
429 int ret;
430 int src_cnt;
431 int dst_cnt;
432 int i;
433 ktime_t ktime;
434 s64 runtime = 0;
435 unsigned long long total_len = 0;
436
437 set_freezable();
438
439 ret = -ENOMEM;
440
441 smp_rmb();
442 info = thread->info;
443 params = &info->params;
444 chan = thread->chan;
445 dev = chan->device;
446 if (thread->type == DMA_MEMCPY)
447 src_cnt = dst_cnt = 1;
448 else if (thread->type == DMA_XOR) {
449 /* force odd to ensure dst = src */
450 src_cnt = min_odd(params->xor_sources | 1, dev->max_xor);
451 dst_cnt = 1;
452 } else if (thread->type == DMA_PQ) {
453 /* force odd to ensure dst = src */
454 src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
455 dst_cnt = 2;
456
457 pq_coefs = kmalloc(params->pq_sources+1, GFP_KERNEL);
458 if (!pq_coefs)
459 goto err_thread_type;
460
461 for (i = 0; i < src_cnt; i++)
462 pq_coefs[i] = 1;
463 } else
464 goto err_thread_type;
465
466 thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
467 if (!thread->srcs)
468 goto err_srcs;
469 for (i = 0; i < src_cnt; i++) {
470 thread->srcs[i] = kmalloc(params->buf_size, GFP_KERNEL);
471 if (!thread->srcs[i])
472 goto err_srcbuf;
473 }
474 thread->srcs[i] = NULL;
475
476 thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
477 if (!thread->dsts)
478 goto err_dsts;
479 for (i = 0; i < dst_cnt; i++) {
480 thread->dsts[i] = kmalloc(params->buf_size, GFP_KERNEL);
481 if (!thread->dsts[i])
482 goto err_dstbuf;
483 }
484 thread->dsts[i] = NULL;
485
486 set_user_nice(current, 10);
487
488 /*
489 * src and dst buffers are freed by ourselves below
490 */
491 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
492
493 ktime = ktime_get();
494 while (!(kthread_should_stop() ||
495 (params->iterations && total_tests >= params->iterations))) {
496 struct dma_async_tx_descriptor *tx = NULL;
497 struct dmaengine_unmap_data *um;
498 dma_addr_t srcs[src_cnt];
499 dma_addr_t *dsts;
500 unsigned int src_off, dst_off, len;
501 u8 align = 0;
502
503 total_tests++;
504
505 /* honor alignment restrictions */
506 if (thread->type == DMA_MEMCPY)
507 align = dev->copy_align;
508 else if (thread->type == DMA_XOR)
509 align = dev->xor_align;
510 else if (thread->type == DMA_PQ)
511 align = dev->pq_align;
512
513 if (1 << align > params->buf_size) {
514 pr_err("%u-byte buffer too small for %d-byte alignment\n",
515 params->buf_size, 1 << align);
516 break;
517 }
518
519 if (params->noverify)
520 len = params->buf_size;
521 else
522 len = dmatest_random() % params->buf_size + 1;
523
524 len = (len >> align) << align;
525 if (!len)
526 len = 1 << align;
527
528 total_len += len;
529
530 if (params->noverify) {
531 src_off = 0;
532 dst_off = 0;
533 } else {
534 src_off = dmatest_random() % (params->buf_size - len + 1);
535 dst_off = dmatest_random() % (params->buf_size - len + 1);
536
537 src_off = (src_off >> align) << align;
538 dst_off = (dst_off >> align) << align;
539
540 dmatest_init_srcs(thread->srcs, src_off, len,
541 params->buf_size);
542 dmatest_init_dsts(thread->dsts, dst_off, len,
543 params->buf_size);
544 }
545
546 um = dmaengine_get_unmap_data(dev->dev, src_cnt+dst_cnt,
547 GFP_KERNEL);
548 if (!um) {
549 failed_tests++;
550 result("unmap data NULL", total_tests,
551 src_off, dst_off, len, ret);
552 continue;
553 }
554
555 um->len = params->buf_size;
556 for (i = 0; i < src_cnt; i++) {
557 void *buf = thread->srcs[i];
558 struct page *pg = virt_to_page(buf);
559 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
560
561 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
562 um->len, DMA_TO_DEVICE);
563 srcs[i] = um->addr[i] + src_off;
564 ret = dma_mapping_error(dev->dev, um->addr[i]);
565 if (ret) {
566 result("src mapping error", total_tests,
567 src_off, dst_off, len, ret);
568 goto error_unmap_continue;
569 }
570 um->to_cnt++;
571 }
572 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
573 dsts = &um->addr[src_cnt];
574 for (i = 0; i < dst_cnt; i++) {
575 void *buf = thread->dsts[i];
576 struct page *pg = virt_to_page(buf);
577 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
578
579 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
580 DMA_BIDIRECTIONAL);
581 ret = dma_mapping_error(dev->dev, dsts[i]);
582 if (ret) {
583 result("dst mapping error", total_tests,
584 src_off, dst_off, len, ret);
585 goto error_unmap_continue;
586 }
587 um->bidi_cnt++;
588 }
589
590 if (thread->type == DMA_MEMCPY)
591 tx = dev->device_prep_dma_memcpy(chan,
592 dsts[0] + dst_off,
593 srcs[0], len, flags);
594 else if (thread->type == DMA_XOR)
595 tx = dev->device_prep_dma_xor(chan,
596 dsts[0] + dst_off,
597 srcs, src_cnt,
598 len, flags);
599 else if (thread->type == DMA_PQ) {
600 dma_addr_t dma_pq[dst_cnt];
601
602 for (i = 0; i < dst_cnt; i++)
603 dma_pq[i] = dsts[i] + dst_off;
604 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
605 src_cnt, pq_coefs,
606 len, flags);
607 }
608
609 if (!tx) {
610 result("prep error", total_tests, src_off,
611 dst_off, len, ret);
612 msleep(100);
613 goto error_unmap_continue;
614 }
615
616 done->done = false;
617 tx->callback = dmatest_callback;
618 tx->callback_param = done;
619 cookie = tx->tx_submit(tx);
620
621 if (dma_submit_error(cookie)) {
622 result("submit error", total_tests, src_off,
623 dst_off, len, ret);
624 msleep(100);
625 goto error_unmap_continue;
626 }
627 dma_async_issue_pending(chan);
628
629 wait_event_freezable_timeout(thread->done_wait, done->done,
630 msecs_to_jiffies(params->timeout));
631
632 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
633
634 if (!done->done) {
635 dmaengine_unmap_put(um);
636 result("test timed out", total_tests, src_off, dst_off,
637 len, 0);
638 goto error_unmap_continue;
639 } else if (status != DMA_COMPLETE) {
640 dmaengine_unmap_put(um);
641 result(status == DMA_ERROR ?
642 "completion error status" :
643 "completion busy status", total_tests, src_off,
644 dst_off, len, ret);
645 goto error_unmap_continue;
646 }
647
648 dmaengine_unmap_put(um);
649
650 if (params->noverify) {
651 verbose_result("test passed", total_tests, src_off,
652 dst_off, len, 0);
653 continue;
654 }
655
656 pr_debug("%s: verifying source buffer...\n", current->comm);
657 error_count = dmatest_verify(thread->srcs, 0, src_off,
658 0, PATTERN_SRC, true);
659 error_count += dmatest_verify(thread->srcs, src_off,
660 src_off + len, src_off,
661 PATTERN_SRC | PATTERN_COPY, true);
662 error_count += dmatest_verify(thread->srcs, src_off + len,
663 params->buf_size, src_off + len,
664 PATTERN_SRC, true);
665
666 pr_debug("%s: verifying dest buffer...\n", current->comm);
667 error_count += dmatest_verify(thread->dsts, 0, dst_off,
668 0, PATTERN_DST, false);
669 error_count += dmatest_verify(thread->dsts, dst_off,
670 dst_off + len, src_off,
671 PATTERN_SRC | PATTERN_COPY, false);
672 error_count += dmatest_verify(thread->dsts, dst_off + len,
673 params->buf_size, dst_off + len,
674 PATTERN_DST, false);
675
676 if (error_count) {
677 result("data error", total_tests, src_off, dst_off,
678 len, error_count);
679 failed_tests++;
680 } else {
681 verbose_result("test passed", total_tests, src_off,
682 dst_off, len, 0);
683 }
684
685 continue;
686
687 error_unmap_continue:
688 dmaengine_unmap_put(um);
689 failed_tests++;
690 }
691 runtime = ktime_us_delta(ktime_get(), ktime);
692
693 ret = 0;
694 err_dstbuf:
695 for (i = 0; thread->dsts[i]; i++)
696 kfree(thread->dsts[i]);
697 kfree(thread->dsts);
698 err_dsts:
699 err_srcbuf:
700 for (i = 0; thread->srcs[i]; i++)
701 kfree(thread->srcs[i]);
702 kfree(thread->srcs);
703 err_srcs:
704 kfree(pq_coefs);
705 err_thread_type:
706 pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n",
707 current->comm, total_tests, failed_tests,
708 dmatest_persec(runtime, total_tests),
709 dmatest_KBs(runtime, total_len), ret);
710
711 /* terminate all transfers on specified channels */
712 if (ret || failed_tests)
713 dmaengine_terminate_all(chan);
714
715 thread->done = true;
716 wake_up(&thread_wait);
717
718 return ret;
719 }
720
dmatest_cleanup_channel(struct dmatest_chan * dtc)721 static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
722 {
723 struct dmatest_thread *thread;
724 struct dmatest_thread *_thread;
725 int ret;
726
727 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
728 ret = kthread_stop(thread->task);
729 pr_debug("thread %s exited with status %d\n",
730 thread->task->comm, ret);
731 list_del(&thread->node);
732 put_task_struct(thread->task);
733 kfree(thread);
734 }
735
736 /* terminate all transfers on specified channels */
737 dmaengine_terminate_all(dtc->chan);
738
739 kfree(dtc);
740 }
741
dmatest_add_threads(struct dmatest_info * info,struct dmatest_chan * dtc,enum dma_transaction_type type)742 static int dmatest_add_threads(struct dmatest_info *info,
743 struct dmatest_chan *dtc, enum dma_transaction_type type)
744 {
745 struct dmatest_params *params = &info->params;
746 struct dmatest_thread *thread;
747 struct dma_chan *chan = dtc->chan;
748 char *op;
749 unsigned int i;
750
751 if (type == DMA_MEMCPY)
752 op = "copy";
753 else if (type == DMA_XOR)
754 op = "xor";
755 else if (type == DMA_PQ)
756 op = "pq";
757 else
758 return -EINVAL;
759
760 for (i = 0; i < params->threads_per_chan; i++) {
761 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
762 if (!thread) {
763 pr_warn("No memory for %s-%s%u\n",
764 dma_chan_name(chan), op, i);
765 break;
766 }
767 thread->info = info;
768 thread->chan = dtc->chan;
769 thread->type = type;
770 thread->test_done.wait = &thread->done_wait;
771 init_waitqueue_head(&thread->done_wait);
772 smp_wmb();
773 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
774 dma_chan_name(chan), op, i);
775 if (IS_ERR(thread->task)) {
776 pr_warn("Failed to create thread %s-%s%u\n",
777 dma_chan_name(chan), op, i);
778 kfree(thread);
779 break;
780 }
781
782 /* srcbuf and dstbuf are allocated by the thread itself */
783 get_task_struct(thread->task);
784 list_add_tail(&thread->node, &dtc->threads);
785 wake_up_process(thread->task);
786 }
787
788 return i;
789 }
790
dmatest_add_channel(struct dmatest_info * info,struct dma_chan * chan)791 static int dmatest_add_channel(struct dmatest_info *info,
792 struct dma_chan *chan)
793 {
794 struct dmatest_chan *dtc;
795 struct dma_device *dma_dev = chan->device;
796 unsigned int thread_count = 0;
797 int cnt;
798
799 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
800 if (!dtc) {
801 pr_warn("No memory for %s\n", dma_chan_name(chan));
802 return -ENOMEM;
803 }
804
805 dtc->chan = chan;
806 INIT_LIST_HEAD(&dtc->threads);
807
808 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
809 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
810 thread_count += cnt > 0 ? cnt : 0;
811 }
812 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
813 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
814 thread_count += cnt > 0 ? cnt : 0;
815 }
816 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
817 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
818 thread_count += cnt > 0 ? cnt : 0;
819 }
820
821 pr_info("Started %u threads using %s\n",
822 thread_count, dma_chan_name(chan));
823
824 list_add_tail(&dtc->node, &info->channels);
825 info->nr_channels++;
826
827 return 0;
828 }
829
filter(struct dma_chan * chan,void * param)830 static bool filter(struct dma_chan *chan, void *param)
831 {
832 struct dmatest_params *params = param;
833
834 if (!dmatest_match_channel(params, chan) ||
835 !dmatest_match_device(params, chan->device))
836 return false;
837 else
838 return true;
839 }
840
request_channels(struct dmatest_info * info,enum dma_transaction_type type)841 static void request_channels(struct dmatest_info *info,
842 enum dma_transaction_type type)
843 {
844 dma_cap_mask_t mask;
845
846 dma_cap_zero(mask);
847 dma_cap_set(type, mask);
848 for (;;) {
849 struct dmatest_params *params = &info->params;
850 struct dma_chan *chan;
851
852 chan = dma_request_channel(mask, filter, params);
853 if (chan) {
854 if (dmatest_add_channel(info, chan)) {
855 dma_release_channel(chan);
856 break; /* add_channel failed, punt */
857 }
858 } else
859 break; /* no more channels available */
860 if (params->max_channels &&
861 info->nr_channels >= params->max_channels)
862 break; /* we have all we need */
863 }
864 }
865
run_threaded_test(struct dmatest_info * info)866 static void run_threaded_test(struct dmatest_info *info)
867 {
868 struct dmatest_params *params = &info->params;
869
870 /* Copy test parameters */
871 params->buf_size = test_buf_size;
872 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
873 strlcpy(params->device, strim(test_device), sizeof(params->device));
874 params->threads_per_chan = threads_per_chan;
875 params->max_channels = max_channels;
876 params->iterations = iterations;
877 params->xor_sources = xor_sources;
878 params->pq_sources = pq_sources;
879 params->timeout = timeout;
880 params->noverify = noverify;
881
882 request_channels(info, DMA_MEMCPY);
883 request_channels(info, DMA_XOR);
884 request_channels(info, DMA_PQ);
885 }
886
stop_threaded_test(struct dmatest_info * info)887 static void stop_threaded_test(struct dmatest_info *info)
888 {
889 struct dmatest_chan *dtc, *_dtc;
890 struct dma_chan *chan;
891
892 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
893 list_del(&dtc->node);
894 chan = dtc->chan;
895 dmatest_cleanup_channel(dtc);
896 pr_debug("dropped channel %s\n", dma_chan_name(chan));
897 dma_release_channel(chan);
898 }
899
900 info->nr_channels = 0;
901 }
902
restart_threaded_test(struct dmatest_info * info,bool run)903 static void restart_threaded_test(struct dmatest_info *info, bool run)
904 {
905 /* we might be called early to set run=, defer running until all
906 * parameters have been evaluated
907 */
908 if (!info->did_init)
909 return;
910
911 /* Stop any running test first */
912 stop_threaded_test(info);
913
914 /* Run test with new parameters */
915 run_threaded_test(info);
916 }
917
dmatest_run_get(char * val,const struct kernel_param * kp)918 static int dmatest_run_get(char *val, const struct kernel_param *kp)
919 {
920 struct dmatest_info *info = &test_info;
921
922 mutex_lock(&info->lock);
923 if (is_threaded_test_run(info)) {
924 dmatest_run = true;
925 } else {
926 stop_threaded_test(info);
927 dmatest_run = false;
928 }
929 mutex_unlock(&info->lock);
930
931 return param_get_bool(val, kp);
932 }
933
dmatest_run_set(const char * val,const struct kernel_param * kp)934 static int dmatest_run_set(const char *val, const struct kernel_param *kp)
935 {
936 struct dmatest_info *info = &test_info;
937 int ret;
938
939 mutex_lock(&info->lock);
940 ret = param_set_bool(val, kp);
941 if (ret) {
942 mutex_unlock(&info->lock);
943 return ret;
944 }
945
946 if (is_threaded_test_run(info))
947 ret = -EBUSY;
948 else if (dmatest_run)
949 restart_threaded_test(info, dmatest_run);
950
951 mutex_unlock(&info->lock);
952
953 return ret;
954 }
955
dmatest_init(void)956 static int __init dmatest_init(void)
957 {
958 struct dmatest_info *info = &test_info;
959 struct dmatest_params *params = &info->params;
960
961 if (dmatest_run) {
962 mutex_lock(&info->lock);
963 run_threaded_test(info);
964 mutex_unlock(&info->lock);
965 }
966
967 if (params->iterations && wait)
968 wait_event(thread_wait, !is_threaded_test_run(info));
969
970 /* module parameters are stable, inittime tests are started,
971 * let userspace take over 'run' control
972 */
973 info->did_init = true;
974
975 return 0;
976 }
977 /* when compiled-in wait for drivers to load first */
978 late_initcall(dmatest_init);
979
dmatest_exit(void)980 static void __exit dmatest_exit(void)
981 {
982 struct dmatest_info *info = &test_info;
983
984 mutex_lock(&info->lock);
985 stop_threaded_test(info);
986 mutex_unlock(&info->lock);
987 }
988 module_exit(dmatest_exit);
989
990 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
991 MODULE_LICENSE("GPL v2");
992