1 /*
2 * Copyright (C) 2011-2012 Avionic Design GmbH
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/gpio/driver.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of_irq.h>
14 #include <linux/seq_file.h>
15 #include <linux/slab.h>
16
17 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
18 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
19 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
20 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
21 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
22
23 struct adnp {
24 struct i2c_client *client;
25 struct gpio_chip gpio;
26 unsigned int reg_shift;
27
28 struct mutex i2c_lock;
29 struct mutex irq_lock;
30
31 u8 *irq_enable;
32 u8 *irq_level;
33 u8 *irq_rise;
34 u8 *irq_fall;
35 u8 *irq_high;
36 u8 *irq_low;
37 };
38
to_adnp(struct gpio_chip * chip)39 static inline struct adnp *to_adnp(struct gpio_chip *chip)
40 {
41 return container_of(chip, struct adnp, gpio);
42 }
43
adnp_read(struct adnp * adnp,unsigned offset,uint8_t * value)44 static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
45 {
46 int err;
47
48 err = i2c_smbus_read_byte_data(adnp->client, offset);
49 if (err < 0) {
50 dev_err(adnp->gpio.dev, "%s failed: %d\n",
51 "i2c_smbus_read_byte_data()", err);
52 return err;
53 }
54
55 *value = err;
56 return 0;
57 }
58
adnp_write(struct adnp * adnp,unsigned offset,uint8_t value)59 static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
60 {
61 int err;
62
63 err = i2c_smbus_write_byte_data(adnp->client, offset, value);
64 if (err < 0) {
65 dev_err(adnp->gpio.dev, "%s failed: %d\n",
66 "i2c_smbus_write_byte_data()", err);
67 return err;
68 }
69
70 return 0;
71 }
72
adnp_gpio_get(struct gpio_chip * chip,unsigned offset)73 static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
74 {
75 struct adnp *adnp = to_adnp(chip);
76 unsigned int reg = offset >> adnp->reg_shift;
77 unsigned int pos = offset & 7;
78 u8 value;
79 int err;
80
81 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
82 if (err < 0)
83 return err;
84
85 return (value & BIT(pos)) ? 1 : 0;
86 }
87
__adnp_gpio_set(struct adnp * adnp,unsigned offset,int value)88 static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
89 {
90 unsigned int reg = offset >> adnp->reg_shift;
91 unsigned int pos = offset & 7;
92 int err;
93 u8 val;
94
95 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
96 if (err < 0)
97 return;
98
99 if (value)
100 val |= BIT(pos);
101 else
102 val &= ~BIT(pos);
103
104 adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
105 }
106
adnp_gpio_set(struct gpio_chip * chip,unsigned offset,int value)107 static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
108 {
109 struct adnp *adnp = to_adnp(chip);
110
111 mutex_lock(&adnp->i2c_lock);
112 __adnp_gpio_set(adnp, offset, value);
113 mutex_unlock(&adnp->i2c_lock);
114 }
115
adnp_gpio_direction_input(struct gpio_chip * chip,unsigned offset)116 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
117 {
118 struct adnp *adnp = to_adnp(chip);
119 unsigned int reg = offset >> adnp->reg_shift;
120 unsigned int pos = offset & 7;
121 u8 value;
122 int err;
123
124 mutex_lock(&adnp->i2c_lock);
125
126 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
127 if (err < 0)
128 goto out;
129
130 value &= ~BIT(pos);
131
132 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
133 if (err < 0)
134 goto out;
135
136 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
137 if (err < 0)
138 goto out;
139
140 if (value & BIT(pos)) {
141 err = -EPERM;
142 goto out;
143 }
144
145 err = 0;
146
147 out:
148 mutex_unlock(&adnp->i2c_lock);
149 return err;
150 }
151
adnp_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)152 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
153 int value)
154 {
155 struct adnp *adnp = to_adnp(chip);
156 unsigned int reg = offset >> adnp->reg_shift;
157 unsigned int pos = offset & 7;
158 int err;
159 u8 val;
160
161 mutex_lock(&adnp->i2c_lock);
162
163 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
164 if (err < 0)
165 goto out;
166
167 val |= BIT(pos);
168
169 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
170 if (err < 0)
171 goto out;
172
173 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
174 if (err < 0)
175 goto out;
176
177 if (!(val & BIT(pos))) {
178 err = -EPERM;
179 goto out;
180 }
181
182 __adnp_gpio_set(adnp, offset, value);
183 err = 0;
184
185 out:
186 mutex_unlock(&adnp->i2c_lock);
187 return err;
188 }
189
adnp_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)190 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
191 {
192 struct adnp *adnp = to_adnp(chip);
193 unsigned int num_regs = 1 << adnp->reg_shift, i, j;
194 int err;
195
196 for (i = 0; i < num_regs; i++) {
197 u8 ddr, plr, ier, isr;
198
199 mutex_lock(&adnp->i2c_lock);
200
201 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
202 if (err < 0) {
203 mutex_unlock(&adnp->i2c_lock);
204 return;
205 }
206
207 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
208 if (err < 0) {
209 mutex_unlock(&adnp->i2c_lock);
210 return;
211 }
212
213 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
214 if (err < 0) {
215 mutex_unlock(&adnp->i2c_lock);
216 return;
217 }
218
219 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
220 if (err < 0) {
221 mutex_unlock(&adnp->i2c_lock);
222 return;
223 }
224
225 mutex_unlock(&adnp->i2c_lock);
226
227 for (j = 0; j < 8; j++) {
228 unsigned int bit = (i << adnp->reg_shift) + j;
229 const char *direction = "input ";
230 const char *level = "low ";
231 const char *interrupt = "disabled";
232 const char *pending = "";
233
234 if (ddr & BIT(j))
235 direction = "output";
236
237 if (plr & BIT(j))
238 level = "high";
239
240 if (ier & BIT(j))
241 interrupt = "enabled ";
242
243 if (isr & BIT(j))
244 pending = "pending";
245
246 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
247 direction, level, interrupt, pending);
248 }
249 }
250 }
251
adnp_gpio_setup(struct adnp * adnp,unsigned int num_gpios)252 static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
253 {
254 struct gpio_chip *chip = &adnp->gpio;
255 int err;
256
257 adnp->reg_shift = get_count_order(num_gpios) - 3;
258
259 chip->direction_input = adnp_gpio_direction_input;
260 chip->direction_output = adnp_gpio_direction_output;
261 chip->get = adnp_gpio_get;
262 chip->set = adnp_gpio_set;
263 chip->can_sleep = true;
264
265 if (IS_ENABLED(CONFIG_DEBUG_FS))
266 chip->dbg_show = adnp_gpio_dbg_show;
267
268 chip->base = -1;
269 chip->ngpio = num_gpios;
270 chip->label = adnp->client->name;
271 chip->dev = &adnp->client->dev;
272 chip->of_node = chip->dev->of_node;
273 chip->owner = THIS_MODULE;
274
275 err = gpiochip_add(chip);
276 if (err)
277 return err;
278
279 return 0;
280 }
281
adnp_irq(int irq,void * data)282 static irqreturn_t adnp_irq(int irq, void *data)
283 {
284 struct adnp *adnp = data;
285 unsigned int num_regs, i;
286
287 num_regs = 1 << adnp->reg_shift;
288
289 for (i = 0; i < num_regs; i++) {
290 unsigned int base = i << adnp->reg_shift, bit;
291 u8 changed, level, isr, ier;
292 unsigned long pending;
293 int err;
294
295 mutex_lock(&adnp->i2c_lock);
296
297 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
298 if (err < 0) {
299 mutex_unlock(&adnp->i2c_lock);
300 continue;
301 }
302
303 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
304 if (err < 0) {
305 mutex_unlock(&adnp->i2c_lock);
306 continue;
307 }
308
309 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
310 if (err < 0) {
311 mutex_unlock(&adnp->i2c_lock);
312 continue;
313 }
314
315 mutex_unlock(&adnp->i2c_lock);
316
317 /* determine pins that changed levels */
318 changed = level ^ adnp->irq_level[i];
319
320 /* compute edge-triggered interrupts */
321 pending = changed & ((adnp->irq_fall[i] & ~level) |
322 (adnp->irq_rise[i] & level));
323
324 /* add in level-triggered interrupts */
325 pending |= (adnp->irq_high[i] & level) |
326 (adnp->irq_low[i] & ~level);
327
328 /* mask out non-pending and disabled interrupts */
329 pending &= isr & ier;
330
331 for_each_set_bit(bit, &pending, 8) {
332 unsigned int child_irq;
333 child_irq = irq_find_mapping(adnp->gpio.irqdomain,
334 base + bit);
335 handle_nested_irq(child_irq);
336 }
337 }
338
339 return IRQ_HANDLED;
340 }
341
adnp_irq_mask(struct irq_data * d)342 static void adnp_irq_mask(struct irq_data *d)
343 {
344 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
345 struct adnp *adnp = to_adnp(gc);
346 unsigned int reg = d->hwirq >> adnp->reg_shift;
347 unsigned int pos = d->hwirq & 7;
348
349 adnp->irq_enable[reg] &= ~BIT(pos);
350 }
351
adnp_irq_unmask(struct irq_data * d)352 static void adnp_irq_unmask(struct irq_data *d)
353 {
354 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
355 struct adnp *adnp = to_adnp(gc);
356 unsigned int reg = d->hwirq >> adnp->reg_shift;
357 unsigned int pos = d->hwirq & 7;
358
359 adnp->irq_enable[reg] |= BIT(pos);
360 }
361
adnp_irq_set_type(struct irq_data * d,unsigned int type)362 static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
363 {
364 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
365 struct adnp *adnp = to_adnp(gc);
366 unsigned int reg = d->hwirq >> adnp->reg_shift;
367 unsigned int pos = d->hwirq & 7;
368
369 if (type & IRQ_TYPE_EDGE_RISING)
370 adnp->irq_rise[reg] |= BIT(pos);
371 else
372 adnp->irq_rise[reg] &= ~BIT(pos);
373
374 if (type & IRQ_TYPE_EDGE_FALLING)
375 adnp->irq_fall[reg] |= BIT(pos);
376 else
377 adnp->irq_fall[reg] &= ~BIT(pos);
378
379 if (type & IRQ_TYPE_LEVEL_HIGH)
380 adnp->irq_high[reg] |= BIT(pos);
381 else
382 adnp->irq_high[reg] &= ~BIT(pos);
383
384 if (type & IRQ_TYPE_LEVEL_LOW)
385 adnp->irq_low[reg] |= BIT(pos);
386 else
387 adnp->irq_low[reg] &= ~BIT(pos);
388
389 return 0;
390 }
391
adnp_irq_bus_lock(struct irq_data * d)392 static void adnp_irq_bus_lock(struct irq_data *d)
393 {
394 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
395 struct adnp *adnp = to_adnp(gc);
396
397 mutex_lock(&adnp->irq_lock);
398 }
399
adnp_irq_bus_unlock(struct irq_data * d)400 static void adnp_irq_bus_unlock(struct irq_data *d)
401 {
402 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
403 struct adnp *adnp = to_adnp(gc);
404 unsigned int num_regs = 1 << adnp->reg_shift, i;
405
406 mutex_lock(&adnp->i2c_lock);
407
408 for (i = 0; i < num_regs; i++)
409 adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
410
411 mutex_unlock(&adnp->i2c_lock);
412 mutex_unlock(&adnp->irq_lock);
413 }
414
415 static struct irq_chip adnp_irq_chip = {
416 .name = "gpio-adnp",
417 .irq_mask = adnp_irq_mask,
418 .irq_unmask = adnp_irq_unmask,
419 .irq_set_type = adnp_irq_set_type,
420 .irq_bus_lock = adnp_irq_bus_lock,
421 .irq_bus_sync_unlock = adnp_irq_bus_unlock,
422 };
423
adnp_irq_setup(struct adnp * adnp)424 static int adnp_irq_setup(struct adnp *adnp)
425 {
426 unsigned int num_regs = 1 << adnp->reg_shift, i;
427 struct gpio_chip *chip = &adnp->gpio;
428 int err;
429
430 mutex_init(&adnp->irq_lock);
431
432 /*
433 * Allocate memory to keep track of the current level and trigger
434 * modes of the interrupts. To avoid multiple allocations, a single
435 * large buffer is allocated and pointers are setup to point at the
436 * corresponding offsets. For consistency, the layout of the buffer
437 * is chosen to match the register layout of the hardware in that
438 * each segment contains the corresponding bits for all interrupts.
439 */
440 adnp->irq_enable = devm_kzalloc(chip->dev, num_regs * 6, GFP_KERNEL);
441 if (!adnp->irq_enable)
442 return -ENOMEM;
443
444 adnp->irq_level = adnp->irq_enable + (num_regs * 1);
445 adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
446 adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
447 adnp->irq_high = adnp->irq_enable + (num_regs * 4);
448 adnp->irq_low = adnp->irq_enable + (num_regs * 5);
449
450 for (i = 0; i < num_regs; i++) {
451 /*
452 * Read the initial level of all pins to allow the emulation
453 * of edge triggered interrupts.
454 */
455 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
456 if (err < 0)
457 return err;
458
459 /* disable all interrupts */
460 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
461 if (err < 0)
462 return err;
463
464 adnp->irq_enable[i] = 0x00;
465 }
466
467 err = devm_request_threaded_irq(chip->dev, adnp->client->irq,
468 NULL, adnp_irq,
469 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
470 dev_name(chip->dev), adnp);
471 if (err != 0) {
472 dev_err(chip->dev, "can't request IRQ#%d: %d\n",
473 adnp->client->irq, err);
474 return err;
475 }
476
477 err = gpiochip_irqchip_add(chip,
478 &adnp_irq_chip,
479 0,
480 handle_simple_irq,
481 IRQ_TYPE_NONE);
482 if (err) {
483 dev_err(chip->dev,
484 "could not connect irqchip to gpiochip\n");
485 return err;
486 }
487
488 return 0;
489 }
490
adnp_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)491 static int adnp_i2c_probe(struct i2c_client *client,
492 const struct i2c_device_id *id)
493 {
494 struct device_node *np = client->dev.of_node;
495 struct adnp *adnp;
496 u32 num_gpios;
497 int err;
498
499 err = of_property_read_u32(np, "nr-gpios", &num_gpios);
500 if (err < 0)
501 return err;
502
503 client->irq = irq_of_parse_and_map(np, 0);
504 if (!client->irq)
505 return -EPROBE_DEFER;
506
507 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
508 if (!adnp)
509 return -ENOMEM;
510
511 mutex_init(&adnp->i2c_lock);
512 adnp->client = client;
513
514 err = adnp_gpio_setup(adnp, num_gpios);
515 if (err)
516 return err;
517
518 if (of_find_property(np, "interrupt-controller", NULL)) {
519 err = adnp_irq_setup(adnp);
520 if (err)
521 return err;
522 }
523
524 i2c_set_clientdata(client, adnp);
525
526 return 0;
527 }
528
adnp_i2c_remove(struct i2c_client * client)529 static int adnp_i2c_remove(struct i2c_client *client)
530 {
531 struct adnp *adnp = i2c_get_clientdata(client);
532
533 gpiochip_remove(&adnp->gpio);
534 return 0;
535 }
536
537 static const struct i2c_device_id adnp_i2c_id[] = {
538 { "gpio-adnp" },
539 { },
540 };
541 MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
542
543 static const struct of_device_id adnp_of_match[] = {
544 { .compatible = "ad,gpio-adnp", },
545 { },
546 };
547 MODULE_DEVICE_TABLE(of, adnp_of_match);
548
549 static struct i2c_driver adnp_i2c_driver = {
550 .driver = {
551 .name = "gpio-adnp",
552 .owner = THIS_MODULE,
553 .of_match_table = adnp_of_match,
554 },
555 .probe = adnp_i2c_probe,
556 .remove = adnp_i2c_remove,
557 .id_table = adnp_i2c_id,
558 };
559 module_i2c_driver(adnp_i2c_driver);
560
561 MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
562 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
563 MODULE_LICENSE("GPL");
564