1 /* 2 * Register definition file for Samsung DP driver 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef _EXYNOS_DP_REG_H 13 #define _EXYNOS_DP_REG_H 14 15 #define EXYNOS_DP_TX_SW_RESET 0x14 16 #define EXYNOS_DP_FUNC_EN_1 0x18 17 #define EXYNOS_DP_FUNC_EN_2 0x1C 18 #define EXYNOS_DP_VIDEO_CTL_1 0x20 19 #define EXYNOS_DP_VIDEO_CTL_2 0x24 20 #define EXYNOS_DP_VIDEO_CTL_3 0x28 21 22 #define EXYNOS_DP_VIDEO_CTL_8 0x3C 23 #define EXYNOS_DP_VIDEO_CTL_10 0x44 24 25 #define EXYNOS_DP_LANE_MAP 0x35C 26 27 #define EXYNOS_DP_ANALOG_CTL_1 0x370 28 #define EXYNOS_DP_ANALOG_CTL_2 0x374 29 #define EXYNOS_DP_ANALOG_CTL_3 0x378 30 #define EXYNOS_DP_PLL_FILTER_CTL_1 0x37C 31 #define EXYNOS_DP_TX_AMP_TUNING_CTL 0x380 32 33 #define EXYNOS_DP_AUX_HW_RETRY_CTL 0x390 34 35 #define EXYNOS_DP_COMMON_INT_STA_1 0x3C4 36 #define EXYNOS_DP_COMMON_INT_STA_2 0x3C8 37 #define EXYNOS_DP_COMMON_INT_STA_3 0x3CC 38 #define EXYNOS_DP_COMMON_INT_STA_4 0x3D0 39 #define EXYNOS_DP_INT_STA 0x3DC 40 #define EXYNOS_DP_COMMON_INT_MASK_1 0x3E0 41 #define EXYNOS_DP_COMMON_INT_MASK_2 0x3E4 42 #define EXYNOS_DP_COMMON_INT_MASK_3 0x3E8 43 #define EXYNOS_DP_COMMON_INT_MASK_4 0x3EC 44 #define EXYNOS_DP_INT_STA_MASK 0x3F8 45 #define EXYNOS_DP_INT_CTL 0x3FC 46 47 #define EXYNOS_DP_SYS_CTL_1 0x600 48 #define EXYNOS_DP_SYS_CTL_2 0x604 49 #define EXYNOS_DP_SYS_CTL_3 0x608 50 #define EXYNOS_DP_SYS_CTL_4 0x60C 51 52 #define EXYNOS_DP_PKT_SEND_CTL 0x640 53 #define EXYNOS_DP_HDCP_CTL 0x648 54 55 #define EXYNOS_DP_LINK_BW_SET 0x680 56 #define EXYNOS_DP_LANE_COUNT_SET 0x684 57 #define EXYNOS_DP_TRAINING_PTN_SET 0x688 58 #define EXYNOS_DP_LN0_LINK_TRAINING_CTL 0x68C 59 #define EXYNOS_DP_LN1_LINK_TRAINING_CTL 0x690 60 #define EXYNOS_DP_LN2_LINK_TRAINING_CTL 0x694 61 #define EXYNOS_DP_LN3_LINK_TRAINING_CTL 0x698 62 63 #define EXYNOS_DP_DEBUG_CTL 0x6C0 64 #define EXYNOS_DP_HPD_DEGLITCH_L 0x6C4 65 #define EXYNOS_DP_HPD_DEGLITCH_H 0x6C8 66 #define EXYNOS_DP_LINK_DEBUG_CTL 0x6E0 67 68 #define EXYNOS_DP_M_VID_0 0x700 69 #define EXYNOS_DP_M_VID_1 0x704 70 #define EXYNOS_DP_M_VID_2 0x708 71 #define EXYNOS_DP_N_VID_0 0x70C 72 #define EXYNOS_DP_N_VID_1 0x710 73 #define EXYNOS_DP_N_VID_2 0x714 74 75 #define EXYNOS_DP_PLL_CTL 0x71C 76 #define EXYNOS_DP_PHY_PD 0x720 77 #define EXYNOS_DP_PHY_TEST 0x724 78 79 #define EXYNOS_DP_VIDEO_FIFO_THRD 0x730 80 #define EXYNOS_DP_AUDIO_MARGIN 0x73C 81 82 #define EXYNOS_DP_M_VID_GEN_FILTER_TH 0x764 83 #define EXYNOS_DP_M_AUD_GEN_FILTER_TH 0x778 84 #define EXYNOS_DP_AUX_CH_STA 0x780 85 #define EXYNOS_DP_AUX_CH_DEFER_CTL 0x788 86 #define EXYNOS_DP_AUX_RX_COMM 0x78C 87 #define EXYNOS_DP_BUFFER_DATA_CTL 0x790 88 #define EXYNOS_DP_AUX_CH_CTL_1 0x794 89 #define EXYNOS_DP_AUX_ADDR_7_0 0x798 90 #define EXYNOS_DP_AUX_ADDR_15_8 0x79C 91 #define EXYNOS_DP_AUX_ADDR_19_16 0x7A0 92 #define EXYNOS_DP_AUX_CH_CTL_2 0x7A4 93 94 #define EXYNOS_DP_BUF_DATA_0 0x7C0 95 96 #define EXYNOS_DP_SOC_GENERAL_CTL 0x800 97 98 /* EXYNOS_DP_TX_SW_RESET */ 99 #define RESET_DP_TX (0x1 << 0) 100 101 /* EXYNOS_DP_FUNC_EN_1 */ 102 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 103 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 104 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 105 #define AUD_FUNC_EN_N (0x1 << 3) 106 #define HDCP_FUNC_EN_N (0x1 << 2) 107 #define CRC_FUNC_EN_N (0x1 << 1) 108 #define SW_FUNC_EN_N (0x1 << 0) 109 110 /* EXYNOS_DP_FUNC_EN_2 */ 111 #define SSC_FUNC_EN_N (0x1 << 7) 112 #define AUX_FUNC_EN_N (0x1 << 2) 113 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 114 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 115 116 /* EXYNOS_DP_VIDEO_CTL_1 */ 117 #define VIDEO_EN (0x1 << 7) 118 #define HDCP_VIDEO_MUTE (0x1 << 6) 119 120 /* EXYNOS_DP_VIDEO_CTL_1 */ 121 #define IN_D_RANGE_MASK (0x1 << 7) 122 #define IN_D_RANGE_SHIFT (7) 123 #define IN_D_RANGE_CEA (0x1 << 7) 124 #define IN_D_RANGE_VESA (0x0 << 7) 125 #define IN_BPC_MASK (0x7 << 4) 126 #define IN_BPC_SHIFT (4) 127 #define IN_BPC_12_BITS (0x3 << 4) 128 #define IN_BPC_10_BITS (0x2 << 4) 129 #define IN_BPC_8_BITS (0x1 << 4) 130 #define IN_BPC_6_BITS (0x0 << 4) 131 #define IN_COLOR_F_MASK (0x3 << 0) 132 #define IN_COLOR_F_SHIFT (0) 133 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 134 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 135 #define IN_COLOR_F_RGB (0x0 << 0) 136 137 /* EXYNOS_DP_VIDEO_CTL_3 */ 138 #define IN_YC_COEFFI_MASK (0x1 << 7) 139 #define IN_YC_COEFFI_SHIFT (7) 140 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 141 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 142 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 143 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 144 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 145 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 146 147 /* EXYNOS_DP_VIDEO_CTL_8 */ 148 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 149 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 150 151 /* EXYNOS_DP_VIDEO_CTL_10 */ 152 #define FORMAT_SEL (0x1 << 4) 153 #define INTERACE_SCAN_CFG (0x1 << 2) 154 #define VSYNC_POLARITY_CFG (0x1 << 1) 155 #define HSYNC_POLARITY_CFG (0x1 << 0) 156 157 /* EXYNOS_DP_LANE_MAP */ 158 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 159 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 160 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 161 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 162 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 163 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 164 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 165 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 166 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 167 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 168 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 169 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 170 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 171 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 172 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 173 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 174 175 /* EXYNOS_DP_ANALOG_CTL_1 */ 176 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 177 178 /* EXYNOS_DP_ANALOG_CTL_2 */ 179 #define SEL_24M (0x1 << 3) 180 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 181 182 /* EXYNOS_DP_ANALOG_CTL_3 */ 183 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 184 #define VCO_BIT_600_MICRO (0x5 << 0) 185 186 /* EXYNOS_DP_PLL_FILTER_CTL_1 */ 187 #define PD_RING_OSC (0x1 << 6) 188 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 189 #define TX_CUR1_2X (0x1 << 2) 190 #define TX_CUR_16_MA (0x3 << 0) 191 192 /* EXYNOS_DP_TX_AMP_TUNING_CTL */ 193 #define CH3_AMP_400_MV (0x0 << 24) 194 #define CH2_AMP_400_MV (0x0 << 16) 195 #define CH1_AMP_400_MV (0x0 << 8) 196 #define CH0_AMP_400_MV (0x0 << 0) 197 198 /* EXYNOS_DP_AUX_HW_RETRY_CTL */ 199 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 200 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 201 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 202 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 203 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 204 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 205 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 206 207 /* EXYNOS_DP_COMMON_INT_STA_1 */ 208 #define VSYNC_DET (0x1 << 7) 209 #define PLL_LOCK_CHG (0x1 << 6) 210 #define SPDIF_ERR (0x1 << 5) 211 #define SPDIF_UNSTBL (0x1 << 4) 212 #define VID_FORMAT_CHG (0x1 << 3) 213 #define AUD_CLK_CHG (0x1 << 2) 214 #define VID_CLK_CHG (0x1 << 1) 215 #define SW_INT (0x1 << 0) 216 217 /* EXYNOS_DP_COMMON_INT_STA_2 */ 218 #define ENC_EN_CHG (0x1 << 6) 219 #define HW_BKSV_RDY (0x1 << 3) 220 #define HW_SHA_DONE (0x1 << 2) 221 #define HW_AUTH_STATE_CHG (0x1 << 1) 222 #define HW_AUTH_DONE (0x1 << 0) 223 224 /* EXYNOS_DP_COMMON_INT_STA_3 */ 225 #define AFIFO_UNDER (0x1 << 7) 226 #define AFIFO_OVER (0x1 << 6) 227 #define R0_CHK_FLAG (0x1 << 5) 228 229 /* EXYNOS_DP_COMMON_INT_STA_4 */ 230 #define PSR_ACTIVE (0x1 << 7) 231 #define PSR_INACTIVE (0x1 << 6) 232 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 233 #define HOTPLUG_CHG (0x1 << 2) 234 #define HPD_LOST (0x1 << 1) 235 #define PLUG (0x1 << 0) 236 237 /* EXYNOS_DP_INT_STA */ 238 #define INT_HPD (0x1 << 6) 239 #define HW_TRAINING_FINISH (0x1 << 5) 240 #define RPLY_RECEIV (0x1 << 1) 241 #define AUX_ERR (0x1 << 0) 242 243 /* EXYNOS_DP_INT_CTL */ 244 #define SOFT_INT_CTRL (0x1 << 2) 245 #define INT_POL1 (0x1 << 1) 246 #define INT_POL0 (0x1 << 0) 247 248 /* EXYNOS_DP_SYS_CTL_1 */ 249 #define DET_STA (0x1 << 2) 250 #define FORCE_DET (0x1 << 1) 251 #define DET_CTRL (0x1 << 0) 252 253 /* EXYNOS_DP_SYS_CTL_2 */ 254 #define CHA_CRI(x) (((x) & 0xf) << 4) 255 #define CHA_STA (0x1 << 2) 256 #define FORCE_CHA (0x1 << 1) 257 #define CHA_CTRL (0x1 << 0) 258 259 /* EXYNOS_DP_SYS_CTL_3 */ 260 #define HPD_STATUS (0x1 << 6) 261 #define F_HPD (0x1 << 5) 262 #define HPD_CTRL (0x1 << 4) 263 #define HDCP_RDY (0x1 << 3) 264 #define STRM_VALID (0x1 << 2) 265 #define F_VALID (0x1 << 1) 266 #define VALID_CTRL (0x1 << 0) 267 268 /* EXYNOS_DP_SYS_CTL_4 */ 269 #define FIX_M_AUD (0x1 << 4) 270 #define ENHANCED (0x1 << 3) 271 #define FIX_M_VID (0x1 << 2) 272 #define M_VID_UPDATE_CTRL (0x3 << 0) 273 274 /* EXYNOS_DP_TRAINING_PTN_SET */ 275 #define SCRAMBLER_TYPE (0x1 << 9) 276 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 277 #define SCRAMBLING_DISABLE (0x1 << 5) 278 #define SCRAMBLING_ENABLE (0x0 << 5) 279 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 280 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 281 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 282 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 283 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 284 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 285 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 286 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 287 288 /* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ 289 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 290 #define PRE_EMPHASIS_SET_SHIFT (3) 291 292 /* EXYNOS_DP_DEBUG_CTL */ 293 #define PLL_LOCK (0x1 << 4) 294 #define F_PLL_LOCK (0x1 << 3) 295 #define PLL_LOCK_CTRL (0x1 << 2) 296 #define PN_INV (0x1 << 0) 297 298 /* EXYNOS_DP_PLL_CTL */ 299 #define DP_PLL_PD (0x1 << 7) 300 #define DP_PLL_RESET (0x1 << 6) 301 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 302 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 303 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 304 305 /* EXYNOS_DP_PHY_PD */ 306 #define DP_PHY_PD (0x1 << 5) 307 #define AUX_PD (0x1 << 4) 308 #define CH3_PD (0x1 << 3) 309 #define CH2_PD (0x1 << 2) 310 #define CH1_PD (0x1 << 1) 311 #define CH0_PD (0x1 << 0) 312 313 /* EXYNOS_DP_PHY_TEST */ 314 #define MACRO_RST (0x1 << 5) 315 #define CH1_TEST (0x1 << 1) 316 #define CH0_TEST (0x1 << 0) 317 318 /* EXYNOS_DP_AUX_CH_STA */ 319 #define AUX_BUSY (0x1 << 4) 320 #define AUX_STATUS_MASK (0xf << 0) 321 322 /* EXYNOS_DP_AUX_CH_DEFER_CTL */ 323 #define DEFER_CTRL_EN (0x1 << 7) 324 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 325 326 /* EXYNOS_DP_AUX_RX_COMM */ 327 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 328 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 329 330 /* EXYNOS_DP_BUFFER_DATA_CTL */ 331 #define BUF_CLR (0x1 << 7) 332 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 333 334 /* EXYNOS_DP_AUX_CH_CTL_1 */ 335 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 336 #define AUX_TX_COMM_MASK (0xf << 0) 337 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 338 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 339 #define AUX_TX_COMM_MOT (0x1 << 2) 340 #define AUX_TX_COMM_WRITE (0x0 << 0) 341 #define AUX_TX_COMM_READ (0x1 << 0) 342 343 /* EXYNOS_DP_AUX_ADDR_7_0 */ 344 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 345 346 /* EXYNOS_DP_AUX_ADDR_15_8 */ 347 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 348 349 /* EXYNOS_DP_AUX_ADDR_19_16 */ 350 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 351 352 /* EXYNOS_DP_AUX_CH_CTL_2 */ 353 #define ADDR_ONLY (0x1 << 1) 354 #define AUX_EN (0x1 << 0) 355 356 /* EXYNOS_DP_SOC_GENERAL_CTL */ 357 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 358 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 359 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 360 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 361 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 362 #define VIDEO_MODE_MASK (0x1 << 0) 363 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 364 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 365 366 #endif /* _EXYNOS_DP_REG_H */ 367