1 /*
2 * i.MX drm driver - LVDS display bridge
3 *
4 * Copyright (C) 2012 Sascha Hauer, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/module.h>
17 #include <linux/clk.h>
18 #include <linux/component.h>
19 #include <drm/drmP.h>
20 #include <drm/drm_fb_helper.h>
21 #include <drm/drm_crtc_helper.h>
22 #include <drm/drm_panel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
25 #include <linux/of_device.h>
26 #include <linux/of_graph.h>
27 #include <video/of_videomode.h>
28 #include <linux/regmap.h>
29 #include <linux/videodev2.h>
30
31 #include "imx-drm.h"
32
33 #define DRIVER_NAME "imx-ldb"
34
35 #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
36 #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
37 #define LDB_CH0_MODE_EN_MASK (3 << 0)
38 #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
39 #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
40 #define LDB_CH1_MODE_EN_MASK (3 << 2)
41 #define LDB_SPLIT_MODE_EN (1 << 4)
42 #define LDB_DATA_WIDTH_CH0_24 (1 << 5)
43 #define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
44 #define LDB_DATA_WIDTH_CH1_24 (1 << 7)
45 #define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
46 #define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
47 #define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
48 #define LDB_BGREF_RMODE_INT (1 << 15)
49
50 #define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
51 #define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)
52
53 struct imx_ldb;
54
55 struct imx_ldb_channel {
56 struct imx_ldb *ldb;
57 struct drm_connector connector;
58 struct drm_encoder encoder;
59 struct drm_panel *panel;
60 struct device_node *child;
61 int chno;
62 void *edid;
63 int edid_len;
64 struct drm_display_mode mode;
65 int mode_valid;
66 int bus_format;
67 };
68
69 struct bus_mux {
70 int reg;
71 int shift;
72 int mask;
73 };
74
75 struct imx_ldb {
76 struct regmap *regmap;
77 struct device *dev;
78 struct imx_ldb_channel channel[2];
79 struct clk *clk[2]; /* our own clock */
80 struct clk *clk_sel[4]; /* parent of display clock */
81 struct clk *clk_parent[4]; /* original parent of clk_sel */
82 struct clk *clk_pll[2]; /* upstream clock we can adjust */
83 u32 ldb_ctrl;
84 const struct bus_mux *lvds_mux;
85 };
86
imx_ldb_connector_detect(struct drm_connector * connector,bool force)87 static enum drm_connector_status imx_ldb_connector_detect(
88 struct drm_connector *connector, bool force)
89 {
90 return connector_status_connected;
91 }
92
imx_ldb_connector_get_modes(struct drm_connector * connector)93 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
94 {
95 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
96 int num_modes = 0;
97
98 if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs &&
99 imx_ldb_ch->panel->funcs->get_modes) {
100 struct drm_display_info *di = &connector->display_info;
101
102 num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel);
103 if (!imx_ldb_ch->bus_format && di->num_bus_formats)
104 imx_ldb_ch->bus_format = di->bus_formats[0];
105 if (num_modes > 0)
106 return num_modes;
107 }
108
109 if (imx_ldb_ch->edid) {
110 drm_mode_connector_update_edid_property(connector,
111 imx_ldb_ch->edid);
112 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
113 }
114
115 if (imx_ldb_ch->mode_valid) {
116 struct drm_display_mode *mode;
117
118 mode = drm_mode_create(connector->dev);
119 if (!mode)
120 return -EINVAL;
121 drm_mode_copy(mode, &imx_ldb_ch->mode);
122 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
123 drm_mode_probed_add(connector, mode);
124 num_modes++;
125 }
126
127 return num_modes;
128 }
129
imx_ldb_connector_best_encoder(struct drm_connector * connector)130 static struct drm_encoder *imx_ldb_connector_best_encoder(
131 struct drm_connector *connector)
132 {
133 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
134
135 return &imx_ldb_ch->encoder;
136 }
137
imx_ldb_encoder_dpms(struct drm_encoder * encoder,int mode)138 static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
139 {
140 }
141
imx_ldb_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)142 static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
143 const struct drm_display_mode *mode,
144 struct drm_display_mode *adjusted_mode)
145 {
146 return true;
147 }
148
imx_ldb_set_clock(struct imx_ldb * ldb,int mux,int chno,unsigned long serial_clk,unsigned long di_clk)149 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
150 unsigned long serial_clk, unsigned long di_clk)
151 {
152 int ret;
153
154 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
155 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
156 clk_set_rate(ldb->clk_pll[chno], serial_clk);
157
158 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
159 clk_get_rate(ldb->clk_pll[chno]));
160
161 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
162 clk_get_rate(ldb->clk[chno]),
163 (long int)di_clk);
164 clk_set_rate(ldb->clk[chno], di_clk);
165
166 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
167 clk_get_rate(ldb->clk[chno]));
168
169 /* set display clock mux to LDB input clock */
170 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
171 if (ret)
172 dev_err(ldb->dev,
173 "unable to set di%d parent clock to ldb_di%d\n", mux,
174 chno);
175 }
176
imx_ldb_encoder_prepare(struct drm_encoder * encoder)177 static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
178 {
179 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
180 struct imx_ldb *ldb = imx_ldb_ch->ldb;
181 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
182 u32 bus_format;
183
184 switch (imx_ldb_ch->bus_format) {
185 default:
186 dev_warn(ldb->dev,
187 "could not determine data mapping, default to 18-bit \"spwg\"\n");
188 /* fallthrough */
189 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
190 bus_format = MEDIA_BUS_FMT_RGB666_1X18;
191 break;
192 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
193 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
194 if (imx_ldb_ch->chno == 0 || dual)
195 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
196 if (imx_ldb_ch->chno == 1 || dual)
197 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
198 break;
199 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
200 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
201 if (imx_ldb_ch->chno == 0 || dual)
202 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
203 LDB_BIT_MAP_CH0_JEIDA;
204 if (imx_ldb_ch->chno == 1 || dual)
205 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
206 LDB_BIT_MAP_CH1_JEIDA;
207 break;
208 }
209
210 imx_drm_set_bus_format(encoder, bus_format);
211 }
212
imx_ldb_encoder_commit(struct drm_encoder * encoder)213 static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
214 {
215 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
216 struct imx_ldb *ldb = imx_ldb_ch->ldb;
217 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
218 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
219
220 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
221 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
222 return;
223 }
224
225 drm_panel_prepare(imx_ldb_ch->panel);
226
227 if (dual) {
228 clk_prepare_enable(ldb->clk[0]);
229 clk_prepare_enable(ldb->clk[1]);
230 }
231
232 if (imx_ldb_ch == &ldb->channel[0] || dual) {
233 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
234 if (mux == 0 || ldb->lvds_mux)
235 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
236 else if (mux == 1)
237 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
238 }
239 if (imx_ldb_ch == &ldb->channel[1] || dual) {
240 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
241 if (mux == 1 || ldb->lvds_mux)
242 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
243 else if (mux == 0)
244 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
245 }
246
247 if (ldb->lvds_mux) {
248 const struct bus_mux *lvds_mux = NULL;
249
250 if (imx_ldb_ch == &ldb->channel[0])
251 lvds_mux = &ldb->lvds_mux[0];
252 else if (imx_ldb_ch == &ldb->channel[1])
253 lvds_mux = &ldb->lvds_mux[1];
254
255 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
256 mux << lvds_mux->shift);
257 }
258
259 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
260
261 drm_panel_enable(imx_ldb_ch->panel);
262 }
263
imx_ldb_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * orig_mode,struct drm_display_mode * mode)264 static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
265 struct drm_display_mode *orig_mode,
266 struct drm_display_mode *mode)
267 {
268 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
269 struct imx_ldb *ldb = imx_ldb_ch->ldb;
270 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
271 unsigned long serial_clk;
272 unsigned long di_clk = mode->clock * 1000;
273 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
274
275 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
276 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
277 return;
278 }
279
280 if (mode->clock > 170000) {
281 dev_warn(ldb->dev,
282 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
283 }
284 if (mode->clock > 85000 && !dual) {
285 dev_warn(ldb->dev,
286 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
287 }
288
289 if (dual) {
290 serial_clk = 3500UL * mode->clock;
291 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
292 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
293 } else {
294 serial_clk = 7000UL * mode->clock;
295 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
296 di_clk);
297 }
298
299 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
300 if (imx_ldb_ch == &ldb->channel[0]) {
301 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
302 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
303 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
304 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
305 }
306 if (imx_ldb_ch == &ldb->channel[1]) {
307 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
308 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
309 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
310 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
311 }
312 }
313
imx_ldb_encoder_disable(struct drm_encoder * encoder)314 static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
315 {
316 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
317 struct imx_ldb *ldb = imx_ldb_ch->ldb;
318 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
319 int mux, ret;
320
321 /*
322 * imx_ldb_encoder_disable is called by
323 * drm_helper_disable_unused_functions without
324 * the encoder being enabled before.
325 */
326 if (imx_ldb_ch == &ldb->channel[0] &&
327 (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
328 return;
329 else if (imx_ldb_ch == &ldb->channel[1] &&
330 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
331 return;
332
333 drm_panel_disable(imx_ldb_ch->panel);
334
335 if (imx_ldb_ch == &ldb->channel[0] || dual)
336 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
337 if (imx_ldb_ch == &ldb->channel[1] || dual)
338 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
339
340 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
341
342 if (dual) {
343 clk_disable_unprepare(ldb->clk[0]);
344 clk_disable_unprepare(ldb->clk[1]);
345 }
346
347 if (ldb->lvds_mux) {
348 const struct bus_mux *lvds_mux = NULL;
349
350 if (imx_ldb_ch == &ldb->channel[0])
351 lvds_mux = &ldb->lvds_mux[0];
352 else if (imx_ldb_ch == &ldb->channel[1])
353 lvds_mux = &ldb->lvds_mux[1];
354
355 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
356 mux &= lvds_mux->mask;
357 mux >>= lvds_mux->shift;
358 } else {
359 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
360 }
361
362 /* set display clock mux back to original input clock */
363 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
364 if (ret)
365 dev_err(ldb->dev,
366 "unable to set di%d parent clock to original parent\n",
367 mux);
368
369 drm_panel_unprepare(imx_ldb_ch->panel);
370 }
371
372 static struct drm_connector_funcs imx_ldb_connector_funcs = {
373 .dpms = drm_helper_connector_dpms,
374 .fill_modes = drm_helper_probe_single_connector_modes,
375 .detect = imx_ldb_connector_detect,
376 .destroy = imx_drm_connector_destroy,
377 };
378
379 static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
380 .get_modes = imx_ldb_connector_get_modes,
381 .best_encoder = imx_ldb_connector_best_encoder,
382 };
383
384 static struct drm_encoder_funcs imx_ldb_encoder_funcs = {
385 .destroy = imx_drm_encoder_destroy,
386 };
387
388 static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
389 .dpms = imx_ldb_encoder_dpms,
390 .mode_fixup = imx_ldb_encoder_mode_fixup,
391 .prepare = imx_ldb_encoder_prepare,
392 .commit = imx_ldb_encoder_commit,
393 .mode_set = imx_ldb_encoder_mode_set,
394 .disable = imx_ldb_encoder_disable,
395 };
396
imx_ldb_get_clk(struct imx_ldb * ldb,int chno)397 static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
398 {
399 char clkname[16];
400
401 snprintf(clkname, sizeof(clkname), "di%d", chno);
402 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
403 if (IS_ERR(ldb->clk[chno]))
404 return PTR_ERR(ldb->clk[chno]);
405
406 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
407 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
408
409 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
410 }
411
imx_ldb_register(struct drm_device * drm,struct imx_ldb_channel * imx_ldb_ch)412 static int imx_ldb_register(struct drm_device *drm,
413 struct imx_ldb_channel *imx_ldb_ch)
414 {
415 struct imx_ldb *ldb = imx_ldb_ch->ldb;
416 int ret;
417
418 ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder,
419 imx_ldb_ch->child);
420 if (ret)
421 return ret;
422
423 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
424 if (ret)
425 return ret;
426
427 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
428 ret = imx_ldb_get_clk(ldb, 1);
429 if (ret)
430 return ret;
431 }
432
433 drm_encoder_helper_add(&imx_ldb_ch->encoder,
434 &imx_ldb_encoder_helper_funcs);
435 drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs,
436 DRM_MODE_ENCODER_LVDS);
437
438 drm_connector_helper_add(&imx_ldb_ch->connector,
439 &imx_ldb_connector_helper_funcs);
440 drm_connector_init(drm, &imx_ldb_ch->connector,
441 &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
442
443 if (imx_ldb_ch->panel)
444 drm_panel_attach(imx_ldb_ch->panel, &imx_ldb_ch->connector);
445
446 drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
447 &imx_ldb_ch->encoder);
448
449 return 0;
450 }
451
452 enum {
453 LVDS_BIT_MAP_SPWG,
454 LVDS_BIT_MAP_JEIDA
455 };
456
457 struct imx_ldb_bit_mapping {
458 u32 bus_format;
459 u32 datawidth;
460 const char * const mapping;
461 };
462
463 static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
464 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
465 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
466 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
467 };
468
of_get_bus_format(struct device * dev,struct device_node * np)469 static u32 of_get_bus_format(struct device *dev, struct device_node *np)
470 {
471 const char *bm;
472 u32 datawidth = 0;
473 int ret, i;
474
475 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
476 if (ret < 0)
477 return ret;
478
479 of_property_read_u32(np, "fsl,data-width", &datawidth);
480
481 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
482 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
483 datawidth == imx_ldb_bit_mappings[i].datawidth)
484 return imx_ldb_bit_mappings[i].bus_format;
485 }
486
487 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
488
489 return -ENOENT;
490 }
491
492 static struct bus_mux imx6q_lvds_mux[2] = {
493 {
494 .reg = IOMUXC_GPR3,
495 .shift = 6,
496 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
497 }, {
498 .reg = IOMUXC_GPR3,
499 .shift = 8,
500 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
501 }
502 };
503
504 /*
505 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
506 * of_match_device will walk through this list and take the first entry
507 * matching any of its compatible values. Therefore, the more generic
508 * entries (in this case fsl,imx53-ldb) need to be ordered last.
509 */
510 static const struct of_device_id imx_ldb_dt_ids[] = {
511 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
512 { .compatible = "fsl,imx53-ldb", .data = NULL, },
513 { }
514 };
515 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
516
imx_ldb_bind(struct device * dev,struct device * master,void * data)517 static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
518 {
519 struct drm_device *drm = data;
520 struct device_node *np = dev->of_node;
521 const struct of_device_id *of_id =
522 of_match_device(imx_ldb_dt_ids, dev);
523 struct device_node *child;
524 const u8 *edidp;
525 struct imx_ldb *imx_ldb;
526 int dual;
527 int ret;
528 int i;
529
530 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
531 if (!imx_ldb)
532 return -ENOMEM;
533
534 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
535 if (IS_ERR(imx_ldb->regmap)) {
536 dev_err(dev, "failed to get parent regmap\n");
537 return PTR_ERR(imx_ldb->regmap);
538 }
539
540 /* disable LDB by resetting the control register to POR default */
541 regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
542
543 imx_ldb->dev = dev;
544
545 if (of_id)
546 imx_ldb->lvds_mux = of_id->data;
547
548 dual = of_property_read_bool(np, "fsl,dual-channel");
549 if (dual)
550 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
551
552 /*
553 * There are three different possible clock mux configurations:
554 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
555 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
556 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
557 * Map them all to di0_sel...di3_sel.
558 */
559 for (i = 0; i < 4; i++) {
560 char clkname[16];
561
562 sprintf(clkname, "di%d_sel", i);
563 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
564 if (IS_ERR(imx_ldb->clk_sel[i])) {
565 ret = PTR_ERR(imx_ldb->clk_sel[i]);
566 imx_ldb->clk_sel[i] = NULL;
567 break;
568 }
569
570 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
571 }
572 if (i == 0)
573 return ret;
574
575 for_each_child_of_node(np, child) {
576 struct imx_ldb_channel *channel;
577 struct device_node *port;
578
579 ret = of_property_read_u32(child, "reg", &i);
580 if (ret || i < 0 || i > 1)
581 return -EINVAL;
582
583 if (!of_device_is_available(child))
584 continue;
585
586 if (dual && i > 0) {
587 dev_warn(dev, "dual-channel mode, ignoring second output\n");
588 continue;
589 }
590
591 channel = &imx_ldb->channel[i];
592 channel->ldb = imx_ldb;
593 channel->chno = i;
594 channel->child = child;
595
596 /*
597 * The output port is port@4 with an external 4-port mux or
598 * port@2 with the internal 2-port mux.
599 */
600 port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2);
601 if (port) {
602 struct device_node *endpoint, *remote;
603
604 endpoint = of_get_child_by_name(port, "endpoint");
605 if (endpoint) {
606 remote = of_graph_get_remote_port_parent(endpoint);
607 if (remote)
608 channel->panel = of_drm_find_panel(remote);
609 else
610 return -EPROBE_DEFER;
611 if (!channel->panel) {
612 dev_err(dev, "panel not found: %s\n",
613 remote->full_name);
614 return -EPROBE_DEFER;
615 }
616 }
617 }
618
619 edidp = of_get_property(child, "edid", &channel->edid_len);
620 if (edidp) {
621 channel->edid = kmemdup(edidp, channel->edid_len,
622 GFP_KERNEL);
623 } else if (!channel->panel) {
624 ret = of_get_drm_display_mode(child, &channel->mode, 0);
625 if (!ret)
626 channel->mode_valid = 1;
627 }
628
629 channel->bus_format = of_get_bus_format(dev, child);
630 if (channel->bus_format == -EINVAL) {
631 /*
632 * If no bus format was specified in the device tree,
633 * we can still get it from the connected panel later.
634 */
635 if (channel->panel && channel->panel->funcs &&
636 channel->panel->funcs->get_modes)
637 channel->bus_format = 0;
638 }
639 if (channel->bus_format < 0) {
640 dev_err(dev, "could not determine data mapping: %d\n",
641 channel->bus_format);
642 return channel->bus_format;
643 }
644
645 ret = imx_ldb_register(drm, channel);
646 if (ret)
647 return ret;
648 }
649
650 dev_set_drvdata(dev, imx_ldb);
651
652 return 0;
653 }
654
imx_ldb_unbind(struct device * dev,struct device * master,void * data)655 static void imx_ldb_unbind(struct device *dev, struct device *master,
656 void *data)
657 {
658 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
659 int i;
660
661 for (i = 0; i < 2; i++) {
662 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
663
664 if (!channel->connector.funcs)
665 continue;
666
667 channel->connector.funcs->destroy(&channel->connector);
668 channel->encoder.funcs->destroy(&channel->encoder);
669
670 kfree(channel->edid);
671 }
672 }
673
674 static const struct component_ops imx_ldb_ops = {
675 .bind = imx_ldb_bind,
676 .unbind = imx_ldb_unbind,
677 };
678
imx_ldb_probe(struct platform_device * pdev)679 static int imx_ldb_probe(struct platform_device *pdev)
680 {
681 return component_add(&pdev->dev, &imx_ldb_ops);
682 }
683
imx_ldb_remove(struct platform_device * pdev)684 static int imx_ldb_remove(struct platform_device *pdev)
685 {
686 component_del(&pdev->dev, &imx_ldb_ops);
687 return 0;
688 }
689
690 static struct platform_driver imx_ldb_driver = {
691 .probe = imx_ldb_probe,
692 .remove = imx_ldb_remove,
693 .driver = {
694 .of_match_table = imx_ldb_dt_ids,
695 .name = DRIVER_NAME,
696 },
697 };
698
699 module_platform_driver(imx_ldb_driver);
700
701 MODULE_DESCRIPTION("i.MX LVDS driver");
702 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
703 MODULE_LICENSE("GPL");
704 MODULE_ALIAS("platform:" DRIVER_NAME);
705