1 /*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef __MDP4_KMS_H__
19 #define __MDP4_KMS_H__
20
21 #include "msm_drv.h"
22 #include "msm_kms.h"
23 #include "mdp/mdp_kms.h"
24 #include "mdp4.xml.h"
25
26 #include "drm_panel.h"
27
28 struct mdp4_kms {
29 struct mdp_kms base;
30
31 struct drm_device *dev;
32
33 int rev;
34
35 /* mapper-id used to request GEM buffer mapped for scanout: */
36 int id;
37
38 void __iomem *mmio;
39
40 struct regulator *dsi_pll_vdda;
41 struct regulator *dsi_pll_vddio;
42 struct regulator *vdd;
43
44 struct clk *clk;
45 struct clk *pclk;
46 struct clk *lut_clk;
47 struct clk *axi_clk;
48
49 struct mdp_irq error_handler;
50
51 /* empty/blank cursor bo to use when cursor is "disabled" */
52 struct drm_gem_object *blank_cursor_bo;
53 uint32_t blank_cursor_iova;
54 };
55 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
56
57 /* platform config data (ie. from DT, or pdata) */
58 struct mdp4_platform_config {
59 struct iommu_domain *iommu;
60 uint32_t max_clk;
61 };
62
mdp4_write(struct mdp4_kms * mdp4_kms,u32 reg,u32 data)63 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
64 {
65 msm_writel(data, mdp4_kms->mmio + reg);
66 }
67
mdp4_read(struct mdp4_kms * mdp4_kms,u32 reg)68 static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
69 {
70 return msm_readl(mdp4_kms->mmio + reg);
71 }
72
pipe2flush(enum mdp4_pipe pipe)73 static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
74 {
75 switch (pipe) {
76 case VG1: return MDP4_OVERLAY_FLUSH_VG1;
77 case VG2: return MDP4_OVERLAY_FLUSH_VG2;
78 case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
79 case RGB2: return MDP4_OVERLAY_FLUSH_RGB2;
80 default: return 0;
81 }
82 }
83
ovlp2flush(int ovlp)84 static inline uint32_t ovlp2flush(int ovlp)
85 {
86 switch (ovlp) {
87 case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
88 case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
89 default: return 0;
90 }
91 }
92
dma2irq(enum mdp4_dma dma)93 static inline uint32_t dma2irq(enum mdp4_dma dma)
94 {
95 switch (dma) {
96 case DMA_P: return MDP4_IRQ_DMA_P_DONE;
97 case DMA_S: return MDP4_IRQ_DMA_S_DONE;
98 case DMA_E: return MDP4_IRQ_DMA_E_DONE;
99 default: return 0;
100 }
101 }
102
dma2err(enum mdp4_dma dma)103 static inline uint32_t dma2err(enum mdp4_dma dma)
104 {
105 switch (dma) {
106 case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
107 case DMA_S: return 0; // ???
108 case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
109 default: return 0;
110 }
111 }
112
mixercfg(uint32_t mixer_cfg,int mixer,enum mdp4_pipe pipe,enum mdp_mixer_stage_id stage)113 static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
114 enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
115 {
116 switch (pipe) {
117 case VG1:
118 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK |
119 MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
120 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
121 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
122 break;
123 case VG2:
124 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK |
125 MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
126 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
127 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
128 break;
129 case RGB1:
130 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK |
131 MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
132 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
133 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
134 break;
135 case RGB2:
136 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK |
137 MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
138 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
139 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
140 break;
141 case RGB3:
142 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK |
143 MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
144 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
145 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
146 break;
147 case VG3:
148 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK |
149 MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
150 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
151 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
152 break;
153 case VG4:
154 mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK |
155 MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
156 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
157 COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
158 break;
159 default:
160 WARN_ON("invalid pipe");
161 break;
162 }
163
164 return mixer_cfg;
165 }
166
167 int mdp4_disable(struct mdp4_kms *mdp4_kms);
168 int mdp4_enable(struct mdp4_kms *mdp4_kms);
169
170 void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
171 uint32_t old_irqmask);
172 void mdp4_irq_preinstall(struct msm_kms *kms);
173 int mdp4_irq_postinstall(struct msm_kms *kms);
174 void mdp4_irq_uninstall(struct msm_kms *kms);
175 irqreturn_t mdp4_irq(struct msm_kms *kms);
176 int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
177 void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
178
mdp4_pipe_caps(enum mdp4_pipe pipe)179 static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe)
180 {
181 switch (pipe) {
182 case VG1:
183 case VG2:
184 case VG3:
185 case VG4:
186 return MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
187 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
188 case RGB1:
189 case RGB2:
190 case RGB3:
191 return MDP_PIPE_CAP_SCALE;
192 default:
193 return 0;
194 }
195 }
196
197 enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
198 struct drm_plane *mdp4_plane_init(struct drm_device *dev,
199 enum mdp4_pipe pipe_id, bool private_plane);
200
201 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
202 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
203 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
204 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
205 void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
206 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
207 struct drm_plane *plane, int id, int ovlp_id,
208 enum mdp4_dma dma_id);
209
210 long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
211 struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
212
213 long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
214 struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
215 struct drm_panel *panel);
216
217 struct drm_connector *mdp4_lvds_connector_init(struct drm_device *dev,
218 struct drm_panel *panel, struct drm_encoder *encoder);
219
220 #ifdef CONFIG_COMMON_CLK
221 struct clk *mpd4_lvds_pll_init(struct drm_device *dev);
222 #else
mpd4_lvds_pll_init(struct drm_device * dev)223 static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
224 {
225 return ERR_PTR(-ENODEV);
226 }
227 #endif
228
229 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
match_dev_name(struct device * dev,void * data)230 static inline int match_dev_name(struct device *dev, void *data)
231 {
232 return !strcmp(dev_name(dev), data);
233 }
234 /* bus scaling data is associated with extra pointless platform devices,
235 * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
236 * to find their pdata to make the bus-scaling stuff work.
237 */
mdp4_find_pdata(const char * devname)238 static inline void *mdp4_find_pdata(const char *devname)
239 {
240 struct device *dev;
241 dev = bus_find_device(&platform_bus_type, NULL,
242 (void *)devname, match_dev_name);
243 return dev ? dev->platform_data : NULL;
244 }
245 #endif
246
247 #endif /* __MDP4_KMS_H__ */
248