1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include "nouveau_drm.h"
26 #include "nouveau_dma.h"
27 #include "nouveau_fence.h"
28
29 #include "nv50_display.h"
30
31 u64
nv84_fence_crtc(struct nouveau_channel * chan,int crtc)32 nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
33 {
34 struct nv84_fence_chan *fctx = chan->fence;
35 return fctx->dispc_vma[crtc].offset;
36 }
37
38 static int
nv84_fence_emit32(struct nouveau_channel * chan,u64 virtual,u32 sequence)39 nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
40 {
41 int ret = RING_SPACE(chan, 8);
42 if (ret == 0) {
43 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
44 OUT_RING (chan, chan->vram.handle);
45 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
46 OUT_RING (chan, upper_32_bits(virtual));
47 OUT_RING (chan, lower_32_bits(virtual));
48 OUT_RING (chan, sequence);
49 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
50 OUT_RING (chan, 0x00000000);
51 FIRE_RING (chan);
52 }
53 return ret;
54 }
55
56 static int
nv84_fence_sync32(struct nouveau_channel * chan,u64 virtual,u32 sequence)57 nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
58 {
59 int ret = RING_SPACE(chan, 7);
60 if (ret == 0) {
61 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
62 OUT_RING (chan, chan->vram.handle);
63 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
64 OUT_RING (chan, upper_32_bits(virtual));
65 OUT_RING (chan, lower_32_bits(virtual));
66 OUT_RING (chan, sequence);
67 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
68 FIRE_RING (chan);
69 }
70 return ret;
71 }
72
73 static int
nv84_fence_emit(struct nouveau_fence * fence)74 nv84_fence_emit(struct nouveau_fence *fence)
75 {
76 struct nouveau_channel *chan = fence->channel;
77 struct nv84_fence_chan *fctx = chan->fence;
78 u64 addr = chan->chid * 16;
79
80 if (fence->sysmem)
81 addr += fctx->vma_gart.offset;
82 else
83 addr += fctx->vma.offset;
84
85 return fctx->base.emit32(chan, addr, fence->base.seqno);
86 }
87
88 static int
nv84_fence_sync(struct nouveau_fence * fence,struct nouveau_channel * prev,struct nouveau_channel * chan)89 nv84_fence_sync(struct nouveau_fence *fence,
90 struct nouveau_channel *prev, struct nouveau_channel *chan)
91 {
92 struct nv84_fence_chan *fctx = chan->fence;
93 u64 addr = prev->chid * 16;
94
95 if (fence->sysmem)
96 addr += fctx->vma_gart.offset;
97 else
98 addr += fctx->vma.offset;
99
100 return fctx->base.sync32(chan, addr, fence->base.seqno);
101 }
102
103 static u32
nv84_fence_read(struct nouveau_channel * chan)104 nv84_fence_read(struct nouveau_channel *chan)
105 {
106 struct nv84_fence_priv *priv = chan->drm->fence;
107 return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
108 }
109
110 static void
nv84_fence_context_del(struct nouveau_channel * chan)111 nv84_fence_context_del(struct nouveau_channel *chan)
112 {
113 struct drm_device *dev = chan->drm->dev;
114 struct nv84_fence_priv *priv = chan->drm->fence;
115 struct nv84_fence_chan *fctx = chan->fence;
116 int i;
117
118 for (i = 0; i < dev->mode_config.num_crtc; i++) {
119 struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
120 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
121 }
122
123 nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
124 mutex_lock(&priv->mutex);
125 nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
126 nouveau_bo_vma_del(priv->bo, &fctx->vma);
127 mutex_unlock(&priv->mutex);
128 nouveau_fence_context_del(&fctx->base);
129 chan->fence = NULL;
130 nouveau_fence_context_free(&fctx->base);
131 }
132
133 int
nv84_fence_context_new(struct nouveau_channel * chan)134 nv84_fence_context_new(struct nouveau_channel *chan)
135 {
136 struct nouveau_cli *cli = (void *)chan->user.client;
137 struct nv84_fence_priv *priv = chan->drm->fence;
138 struct nv84_fence_chan *fctx;
139 int ret, i;
140
141 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
142 if (!fctx)
143 return -ENOMEM;
144
145 nouveau_fence_context_new(chan, &fctx->base);
146 fctx->base.emit = nv84_fence_emit;
147 fctx->base.sync = nv84_fence_sync;
148 fctx->base.read = nv84_fence_read;
149 fctx->base.emit32 = nv84_fence_emit32;
150 fctx->base.sync32 = nv84_fence_sync32;
151 fctx->base.sequence = nv84_fence_read(chan);
152
153 mutex_lock(&priv->mutex);
154 ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma);
155 if (ret == 0) {
156 ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm,
157 &fctx->vma_gart);
158 }
159 mutex_unlock(&priv->mutex);
160
161 /* map display semaphore buffers into channel's vm */
162 for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
163 struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i);
164 ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]);
165 }
166
167 if (ret)
168 nv84_fence_context_del(chan);
169 return ret;
170 }
171
172 static bool
nv84_fence_suspend(struct nouveau_drm * drm)173 nv84_fence_suspend(struct nouveau_drm *drm)
174 {
175 struct nv84_fence_priv *priv = drm->fence;
176 int i;
177
178 priv->suspend = vmalloc(priv->base.contexts * sizeof(u32));
179 if (priv->suspend) {
180 for (i = 0; i < priv->base.contexts; i++)
181 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
182 }
183
184 return priv->suspend != NULL;
185 }
186
187 static void
nv84_fence_resume(struct nouveau_drm * drm)188 nv84_fence_resume(struct nouveau_drm *drm)
189 {
190 struct nv84_fence_priv *priv = drm->fence;
191 int i;
192
193 if (priv->suspend) {
194 for (i = 0; i < priv->base.contexts; i++)
195 nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
196 vfree(priv->suspend);
197 priv->suspend = NULL;
198 }
199 }
200
201 static void
nv84_fence_destroy(struct nouveau_drm * drm)202 nv84_fence_destroy(struct nouveau_drm *drm)
203 {
204 struct nv84_fence_priv *priv = drm->fence;
205 nouveau_bo_unmap(priv->bo_gart);
206 if (priv->bo_gart)
207 nouveau_bo_unpin(priv->bo_gart);
208 nouveau_bo_ref(NULL, &priv->bo_gart);
209 nouveau_bo_unmap(priv->bo);
210 if (priv->bo)
211 nouveau_bo_unpin(priv->bo);
212 nouveau_bo_ref(NULL, &priv->bo);
213 drm->fence = NULL;
214 kfree(priv);
215 }
216
217 int
nv84_fence_create(struct nouveau_drm * drm)218 nv84_fence_create(struct nouveau_drm *drm)
219 {
220 struct nvkm_fifo *fifo = nvxx_fifo(&drm->device);
221 struct nv84_fence_priv *priv;
222 u32 domain;
223 int ret;
224
225 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
226 if (!priv)
227 return -ENOMEM;
228
229 priv->base.dtor = nv84_fence_destroy;
230 priv->base.suspend = nv84_fence_suspend;
231 priv->base.resume = nv84_fence_resume;
232 priv->base.context_new = nv84_fence_context_new;
233 priv->base.context_del = nv84_fence_context_del;
234
235 priv->base.contexts = fifo->nr;
236 priv->base.context_base = fence_context_alloc(priv->base.contexts);
237 priv->base.uevent = true;
238
239 mutex_init(&priv->mutex);
240
241 /* Use VRAM if there is any ; otherwise fallback to system memory */
242 domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
243 /*
244 * fences created in sysmem must be non-cached or we
245 * will lose CPU/GPU coherency!
246 */
247 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
248 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0,
249 0, NULL, NULL, &priv->bo);
250 if (ret == 0) {
251 ret = nouveau_bo_pin(priv->bo, domain, false);
252 if (ret == 0) {
253 ret = nouveau_bo_map(priv->bo);
254 if (ret)
255 nouveau_bo_unpin(priv->bo);
256 }
257 if (ret)
258 nouveau_bo_ref(NULL, &priv->bo);
259 }
260
261 if (ret == 0)
262 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0,
263 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED, 0,
264 0, NULL, NULL, &priv->bo_gart);
265 if (ret == 0) {
266 ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT, false);
267 if (ret == 0) {
268 ret = nouveau_bo_map(priv->bo_gart);
269 if (ret)
270 nouveau_bo_unpin(priv->bo_gart);
271 }
272 if (ret)
273 nouveau_bo_ref(NULL, &priv->bo_gart);
274 }
275
276 if (ret)
277 nv84_fence_destroy(drm);
278 return ret;
279 }
280