1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "dmacnv50.h"
25 #include "rootnv50.h"
26
27 #include <core/client.h>
28 #include <subdev/timer.h>
29
30 #include <nvif/class.h>
31 #include <nvif/unpack.h>
32
33 const struct nv50_disp_mthd_list
34 gf119_disp_core_mthd_base = {
35 .mthd = 0x0000,
36 .addr = 0x000000,
37 .data = {
38 { 0x0080, 0x660080 },
39 { 0x0084, 0x660084 },
40 { 0x0088, 0x660088 },
41 { 0x008c, 0x000000 },
42 {}
43 }
44 };
45
46 const struct nv50_disp_mthd_list
47 gf119_disp_core_mthd_dac = {
48 .mthd = 0x0020,
49 .addr = 0x000020,
50 .data = {
51 { 0x0180, 0x660180 },
52 { 0x0184, 0x660184 },
53 { 0x0188, 0x660188 },
54 { 0x0190, 0x660190 },
55 {}
56 }
57 };
58
59 const struct nv50_disp_mthd_list
60 gf119_disp_core_mthd_sor = {
61 .mthd = 0x0020,
62 .addr = 0x000020,
63 .data = {
64 { 0x0200, 0x660200 },
65 { 0x0204, 0x660204 },
66 { 0x0208, 0x660208 },
67 { 0x0210, 0x660210 },
68 {}
69 }
70 };
71
72 const struct nv50_disp_mthd_list
73 gf119_disp_core_mthd_pior = {
74 .mthd = 0x0020,
75 .addr = 0x000020,
76 .data = {
77 { 0x0300, 0x660300 },
78 { 0x0304, 0x660304 },
79 { 0x0308, 0x660308 },
80 { 0x0310, 0x660310 },
81 {}
82 }
83 };
84
85 static const struct nv50_disp_mthd_list
86 gf119_disp_core_mthd_head = {
87 .mthd = 0x0300,
88 .addr = 0x000300,
89 .data = {
90 { 0x0400, 0x660400 },
91 { 0x0404, 0x660404 },
92 { 0x0408, 0x660408 },
93 { 0x040c, 0x66040c },
94 { 0x0410, 0x660410 },
95 { 0x0414, 0x660414 },
96 { 0x0418, 0x660418 },
97 { 0x041c, 0x66041c },
98 { 0x0420, 0x660420 },
99 { 0x0424, 0x660424 },
100 { 0x0428, 0x660428 },
101 { 0x042c, 0x66042c },
102 { 0x0430, 0x660430 },
103 { 0x0434, 0x660434 },
104 { 0x0438, 0x660438 },
105 { 0x0440, 0x660440 },
106 { 0x0444, 0x660444 },
107 { 0x0448, 0x660448 },
108 { 0x044c, 0x66044c },
109 { 0x0450, 0x660450 },
110 { 0x0454, 0x660454 },
111 { 0x0458, 0x660458 },
112 { 0x045c, 0x66045c },
113 { 0x0460, 0x660460 },
114 { 0x0468, 0x660468 },
115 { 0x046c, 0x66046c },
116 { 0x0470, 0x660470 },
117 { 0x0474, 0x660474 },
118 { 0x0480, 0x660480 },
119 { 0x0484, 0x660484 },
120 { 0x048c, 0x66048c },
121 { 0x0490, 0x660490 },
122 { 0x0494, 0x660494 },
123 { 0x0498, 0x660498 },
124 { 0x04b0, 0x6604b0 },
125 { 0x04b8, 0x6604b8 },
126 { 0x04bc, 0x6604bc },
127 { 0x04c0, 0x6604c0 },
128 { 0x04c4, 0x6604c4 },
129 { 0x04c8, 0x6604c8 },
130 { 0x04d0, 0x6604d0 },
131 { 0x04d4, 0x6604d4 },
132 { 0x04e0, 0x6604e0 },
133 { 0x04e4, 0x6604e4 },
134 { 0x04e8, 0x6604e8 },
135 { 0x04ec, 0x6604ec },
136 { 0x04f0, 0x6604f0 },
137 { 0x04f4, 0x6604f4 },
138 { 0x04f8, 0x6604f8 },
139 { 0x04fc, 0x6604fc },
140 { 0x0500, 0x660500 },
141 { 0x0504, 0x660504 },
142 { 0x0508, 0x660508 },
143 { 0x050c, 0x66050c },
144 { 0x0510, 0x660510 },
145 { 0x0514, 0x660514 },
146 { 0x0518, 0x660518 },
147 { 0x051c, 0x66051c },
148 { 0x052c, 0x66052c },
149 { 0x0530, 0x660530 },
150 { 0x054c, 0x66054c },
151 { 0x0550, 0x660550 },
152 { 0x0554, 0x660554 },
153 { 0x0558, 0x660558 },
154 { 0x055c, 0x66055c },
155 {}
156 }
157 };
158
159 static const struct nv50_disp_chan_mthd
160 gf119_disp_core_chan_mthd = {
161 .name = "Core",
162 .addr = 0x000000,
163 .prev = -0x020000,
164 .data = {
165 { "Global", 1, &gf119_disp_core_mthd_base },
166 { "DAC", 3, &gf119_disp_core_mthd_dac },
167 { "SOR", 8, &gf119_disp_core_mthd_sor },
168 { "PIOR", 4, &gf119_disp_core_mthd_pior },
169 { "HEAD", 4, &gf119_disp_core_mthd_head },
170 {}
171 }
172 };
173
174 static void
gf119_disp_core_fini(struct nv50_disp_dmac * chan)175 gf119_disp_core_fini(struct nv50_disp_dmac *chan)
176 {
177 struct nv50_disp *disp = chan->base.root->disp;
178 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
179 struct nvkm_device *device = subdev->device;
180
181 /* deactivate channel */
182 nvkm_mask(device, 0x610490, 0x00000010, 0x00000000);
183 nvkm_mask(device, 0x610490, 0x00000003, 0x00000000);
184 if (nvkm_msec(device, 2000,
185 if (!(nvkm_rd32(device, 0x610490) & 0x001e0000))
186 break;
187 ) < 0) {
188 nvkm_error(subdev, "core fini: %08x\n",
189 nvkm_rd32(device, 0x610490));
190 }
191
192 /* disable error reporting and completion notification */
193 nvkm_mask(device, 0x610090, 0x00000001, 0x00000000);
194 nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000000);
195 }
196
197 static int
gf119_disp_core_init(struct nv50_disp_dmac * chan)198 gf119_disp_core_init(struct nv50_disp_dmac *chan)
199 {
200 struct nv50_disp *disp = chan->base.root->disp;
201 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
202 struct nvkm_device *device = subdev->device;
203
204 /* enable error reporting */
205 nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000001);
206
207 /* initialise channel for dma command submission */
208 nvkm_wr32(device, 0x610494, chan->push);
209 nvkm_wr32(device, 0x610498, 0x00010000);
210 nvkm_wr32(device, 0x61049c, 0x00000001);
211 nvkm_mask(device, 0x610490, 0x00000010, 0x00000010);
212 nvkm_wr32(device, 0x640000, 0x00000000);
213 nvkm_wr32(device, 0x610490, 0x01000013);
214
215 /* wait for it to go inactive */
216 if (nvkm_msec(device, 2000,
217 if (!(nvkm_rd32(device, 0x610490) & 0x80000000))
218 break;
219 ) < 0) {
220 nvkm_error(subdev, "core init: %08x\n",
221 nvkm_rd32(device, 0x610490));
222 return -EBUSY;
223 }
224
225 return 0;
226 }
227
228 const struct nv50_disp_dmac_func
229 gf119_disp_core_func = {
230 .init = gf119_disp_core_init,
231 .fini = gf119_disp_core_fini,
232 .bind = gf119_disp_dmac_bind,
233 };
234
235 const struct nv50_disp_dmac_oclass
236 gf119_disp_core_oclass = {
237 .base.oclass = GF110_DISP_CORE_CHANNEL_DMA,
238 .base.minver = 0,
239 .base.maxver = 0,
240 .ctor = nv50_disp_core_new,
241 .func = &gf119_disp_core_func,
242 .mthd = &gf119_disp_core_chan_mthd,
243 .chid = 0,
244 };
245