1 /*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7 #include <linux/clk.h>
8 #include <linux/io.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12
13 #include <drm/drmP.h>
14
15 /* registers offset */
16 #define VTAC_CONFIG 0x00
17 #define VTAC_RX_FIFO_CONFIG 0x04
18 #define VTAC_FIFO_CONFIG_VAL 0x04
19
20 #define VTAC_SYS_CFG8521 0x824
21 #define VTAC_SYS_CFG8522 0x828
22
23 /* Number of phyts per pixel */
24 #define VTAC_2_5_PPP 0x0005
25 #define VTAC_3_PPP 0x0006
26 #define VTAC_4_PPP 0x0008
27 #define VTAC_5_PPP 0x000A
28 #define VTAC_6_PPP 0x000C
29 #define VTAC_13_PPP 0x001A
30 #define VTAC_14_PPP 0x001C
31 #define VTAC_15_PPP 0x001E
32 #define VTAC_16_PPP 0x0020
33 #define VTAC_17_PPP 0x0022
34 #define VTAC_18_PPP 0x0024
35
36 /* enable bits */
37 #define VTAC_ENABLE 0x3003
38
39 #define VTAC_TX_PHY_ENABLE_CLK_PHY BIT(0)
40 #define VTAC_TX_PHY_ENABLE_CLK_DLL BIT(1)
41 #define VTAC_TX_PHY_PLL_NOT_OSC_MODE BIT(3)
42 #define VTAC_TX_PHY_RST_N_DLL_SWITCH BIT(4)
43 #define VTAC_TX_PHY_PROG_N3 BIT(9)
44
45
46 /**
47 * VTAC mode structure
48 *
49 * @vid_in_width: Video Data Resolution
50 * @phyts_width: Width of phyt buses(phyt low and phyt high).
51 * @phyts_per_pixel: Number of phyts sent per pixel
52 */
53 struct sti_vtac_mode {
54 u32 vid_in_width;
55 u32 phyts_width;
56 u32 phyts_per_pixel;
57 };
58
59 static const struct sti_vtac_mode vtac_mode_main = {
60 .vid_in_width = 0x2,
61 .phyts_width = 0x2,
62 .phyts_per_pixel = VTAC_5_PPP,
63 };
64 static const struct sti_vtac_mode vtac_mode_aux = {
65 .vid_in_width = 0x1,
66 .phyts_width = 0x0,
67 .phyts_per_pixel = VTAC_17_PPP,
68 };
69
70 /**
71 * VTAC structure
72 *
73 * @dev: pointer to device structure
74 * @regs: ioremapped registers for RX and TX devices
75 * @phy_regs: phy registers for TX device
76 * @clk: clock
77 * @mode: main or auxillary configuration mode
78 */
79 struct sti_vtac {
80 struct device *dev;
81 void __iomem *regs;
82 void __iomem *phy_regs;
83 struct clk *clk;
84 const struct sti_vtac_mode *mode;
85 };
86
sti_vtac_rx_set_config(struct sti_vtac * vtac)87 static void sti_vtac_rx_set_config(struct sti_vtac *vtac)
88 {
89 u32 config;
90
91 /* Enable VTAC clock */
92 if (clk_prepare_enable(vtac->clk))
93 DRM_ERROR("Failed to prepare/enable vtac_rx clock.\n");
94
95 writel(VTAC_FIFO_CONFIG_VAL, vtac->regs + VTAC_RX_FIFO_CONFIG);
96
97 config = VTAC_ENABLE;
98 config |= vtac->mode->vid_in_width << 4;
99 config |= vtac->mode->phyts_width << 16;
100 config |= vtac->mode->phyts_per_pixel << 23;
101 writel(config, vtac->regs + VTAC_CONFIG);
102 }
103
sti_vtac_tx_set_config(struct sti_vtac * vtac)104 static void sti_vtac_tx_set_config(struct sti_vtac *vtac)
105 {
106 u32 phy_config;
107 u32 config;
108
109 /* Enable VTAC clock */
110 if (clk_prepare_enable(vtac->clk))
111 DRM_ERROR("Failed to prepare/enable vtac_tx clock.\n");
112
113 /* Configure vtac phy */
114 phy_config = 0x00000000;
115 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8522);
116 phy_config = VTAC_TX_PHY_ENABLE_CLK_PHY;
117 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
118 phy_config = readl(vtac->phy_regs + VTAC_SYS_CFG8521);
119 phy_config |= VTAC_TX_PHY_PROG_N3;
120 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
121 phy_config = readl(vtac->phy_regs + VTAC_SYS_CFG8521);
122 phy_config |= VTAC_TX_PHY_ENABLE_CLK_DLL;
123 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
124 phy_config = readl(vtac->phy_regs + VTAC_SYS_CFG8521);
125 phy_config |= VTAC_TX_PHY_RST_N_DLL_SWITCH;
126 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
127 phy_config = readl(vtac->phy_regs + VTAC_SYS_CFG8521);
128 phy_config |= VTAC_TX_PHY_PLL_NOT_OSC_MODE;
129 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521);
130
131 /* Configure vtac tx */
132 config = VTAC_ENABLE;
133 config |= vtac->mode->vid_in_width << 4;
134 config |= vtac->mode->phyts_width << 16;
135 config |= vtac->mode->phyts_per_pixel << 23;
136 writel(config, vtac->regs + VTAC_CONFIG);
137 }
138
139 static const struct of_device_id vtac_of_match[] = {
140 {
141 .compatible = "st,vtac-main",
142 .data = &vtac_mode_main,
143 }, {
144 .compatible = "st,vtac-aux",
145 .data = &vtac_mode_aux,
146 }, {
147 /* end node */
148 }
149 };
150 MODULE_DEVICE_TABLE(of, vtac_of_match);
151
sti_vtac_probe(struct platform_device * pdev)152 static int sti_vtac_probe(struct platform_device *pdev)
153 {
154 struct device *dev = &pdev->dev;
155 struct device_node *np = dev->of_node;
156 const struct of_device_id *id;
157 struct sti_vtac *vtac;
158 struct resource *res;
159
160 vtac = devm_kzalloc(dev, sizeof(*vtac), GFP_KERNEL);
161 if (!vtac)
162 return -ENOMEM;
163
164 vtac->dev = dev;
165
166 id = of_match_node(vtac_of_match, np);
167 if (!id)
168 return -ENOMEM;
169
170 vtac->mode = id->data;
171
172 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
173 if (!res) {
174 DRM_ERROR("Invalid resource\n");
175 return -ENOMEM;
176 }
177 vtac->regs = devm_ioremap_resource(dev, res);
178 if (IS_ERR(vtac->regs))
179 return PTR_ERR(vtac->regs);
180
181
182 vtac->clk = devm_clk_get(dev, "vtac");
183 if (IS_ERR(vtac->clk)) {
184 DRM_ERROR("Cannot get vtac clock\n");
185 return PTR_ERR(vtac->clk);
186 }
187
188 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
189 if (res) {
190 vtac->phy_regs = devm_ioremap_nocache(dev, res->start,
191 resource_size(res));
192 sti_vtac_tx_set_config(vtac);
193 } else {
194
195 sti_vtac_rx_set_config(vtac);
196 }
197
198 platform_set_drvdata(pdev, vtac);
199 DRM_INFO("%s %s\n", __func__, dev_name(vtac->dev));
200
201 return 0;
202 }
203
sti_vtac_remove(struct platform_device * pdev)204 static int sti_vtac_remove(struct platform_device *pdev)
205 {
206 return 0;
207 }
208
209 struct platform_driver sti_vtac_driver = {
210 .driver = {
211 .name = "sti-vtac",
212 .owner = THIS_MODULE,
213 .of_match_table = vtac_of_match,
214 },
215 .probe = sti_vtac_probe,
216 .remove = sti_vtac_remove,
217 };
218
219 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
220 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
221 MODULE_LICENSE("GPL");
222