1 /*
2 * This driver implements I2C master functionality using the LSI API2C
3 * controller.
4 *
5 * NOTE: The controller has a limitation in that it can only do transfers of
6 * maximum 255 bytes at a time. If a larger transfer is attempted, error code
7 * (-EINVAL) is returned.
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 */
13 #include <linux/clk.h>
14 #include <linux/clkdev.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/platform_device.h>
23
24 #define SCL_WAIT_TIMEOUT_NS 25000000
25 #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
26 #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100))
27 #define FIFO_SIZE 8
28
29 #define GLOBAL_CONTROL 0x00
30 #define GLOBAL_MST_EN BIT(0)
31 #define GLOBAL_SLV_EN BIT(1)
32 #define GLOBAL_IBML_EN BIT(2)
33 #define INTERRUPT_STATUS 0x04
34 #define INTERRUPT_ENABLE 0x08
35 #define INT_SLV BIT(1)
36 #define INT_MST BIT(0)
37 #define WAIT_TIMER_CONTROL 0x0c
38 #define WT_EN BIT(15)
39 #define WT_VALUE(_x) ((_x) & 0x7fff)
40 #define IBML_TIMEOUT 0x10
41 #define IBML_LOW_MEXT 0x14
42 #define IBML_LOW_SEXT 0x18
43 #define TIMER_CLOCK_DIV 0x1c
44 #define I2C_BUS_MONITOR 0x20
45 #define BM_SDAC BIT(3)
46 #define BM_SCLC BIT(2)
47 #define BM_SDAS BIT(1)
48 #define BM_SCLS BIT(0)
49 #define SOFT_RESET 0x24
50 #define MST_COMMAND 0x28
51 #define CMD_BUSY (1<<3)
52 #define CMD_MANUAL (0x00 | CMD_BUSY)
53 #define CMD_AUTO (0x01 | CMD_BUSY)
54 #define MST_RX_XFER 0x2c
55 #define MST_TX_XFER 0x30
56 #define MST_ADDR_1 0x34
57 #define MST_ADDR_2 0x38
58 #define MST_DATA 0x3c
59 #define MST_TX_FIFO 0x40
60 #define MST_RX_FIFO 0x44
61 #define MST_INT_ENABLE 0x48
62 #define MST_INT_STATUS 0x4c
63 #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */
64 #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */
65 #define MST_STATUS_SNS (1 << 11) /* Manual mode done */
66 #define MST_STATUS_SS (1 << 10) /* Automatic mode done */
67 #define MST_STATUS_SCC (1 << 9) /* Stop complete */
68 #define MST_STATUS_IP (1 << 8) /* Invalid parameter */
69 #define MST_STATUS_TSS (1 << 7) /* Timeout */
70 #define MST_STATUS_AL (1 << 6) /* Arbitration lost */
71 #define MST_STATUS_ND (1 << 5) /* NAK on data phase */
72 #define MST_STATUS_NA (1 << 4) /* NAK on address phase */
73 #define MST_STATUS_NAK (MST_STATUS_NA | \
74 MST_STATUS_ND)
75 #define MST_STATUS_ERR (MST_STATUS_NAK | \
76 MST_STATUS_AL | \
77 MST_STATUS_IP)
78 #define MST_TX_BYTES_XFRD 0x50
79 #define MST_RX_BYTES_XFRD 0x54
80 #define SCL_HIGH_PERIOD 0x80
81 #define SCL_LOW_PERIOD 0x84
82 #define SPIKE_FLTR_LEN 0x88
83 #define SDA_SETUP_TIME 0x8c
84 #define SDA_HOLD_TIME 0x90
85
86 /**
87 * axxia_i2c_dev - I2C device context
88 * @base: pointer to register struct
89 * @msg: pointer to current message
90 * @msg_xfrd: number of bytes transferred in msg
91 * @msg_err: error code for completed message
92 * @msg_complete: xfer completion object
93 * @dev: device reference
94 * @adapter: core i2c abstraction
95 * @i2c_clk: clock reference for i2c input clock
96 * @bus_clk_rate: current i2c bus clock rate
97 */
98 struct axxia_i2c_dev {
99 void __iomem *base;
100 struct i2c_msg *msg;
101 size_t msg_xfrd;
102 int msg_err;
103 struct completion msg_complete;
104 struct device *dev;
105 struct i2c_adapter adapter;
106 struct clk *i2c_clk;
107 u32 bus_clk_rate;
108 };
109
i2c_int_disable(struct axxia_i2c_dev * idev,u32 mask)110 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
111 {
112 u32 int_en;
113
114 int_en = readl(idev->base + MST_INT_ENABLE);
115 writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
116 }
117
i2c_int_enable(struct axxia_i2c_dev * idev,u32 mask)118 static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask)
119 {
120 u32 int_en;
121
122 int_en = readl(idev->base + MST_INT_ENABLE);
123 writel(int_en | mask, idev->base + MST_INT_ENABLE);
124 }
125
126 /**
127 * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency.
128 */
ns_to_clk(u64 ns,u32 clk_mhz)129 static u32 ns_to_clk(u64 ns, u32 clk_mhz)
130 {
131 return div_u64(ns * clk_mhz, 1000);
132 }
133
axxia_i2c_init(struct axxia_i2c_dev * idev)134 static int axxia_i2c_init(struct axxia_i2c_dev *idev)
135 {
136 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
137 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
138 u32 t_setup;
139 u32 t_high, t_low;
140 u32 tmo_clk;
141 u32 prescale;
142 unsigned long timeout;
143
144 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
145 idev->bus_clk_rate, clk_mhz, divisor);
146
147 /* Reset controller */
148 writel(0x01, idev->base + SOFT_RESET);
149 timeout = jiffies + msecs_to_jiffies(100);
150 while (readl(idev->base + SOFT_RESET) & 1) {
151 if (time_after(jiffies, timeout)) {
152 dev_warn(idev->dev, "Soft reset failed\n");
153 break;
154 }
155 }
156
157 /* Enable Master Mode */
158 writel(0x1, idev->base + GLOBAL_CONTROL);
159
160 if (idev->bus_clk_rate <= 100000) {
161 /* Standard mode SCL 50/50, tSU:DAT = 250 ns */
162 t_high = divisor * 1 / 2;
163 t_low = divisor * 1 / 2;
164 t_setup = ns_to_clk(250, clk_mhz);
165 } else {
166 /* Fast mode SCL 33/66, tSU:DAT = 100 ns */
167 t_high = divisor * 1 / 3;
168 t_low = divisor * 2 / 3;
169 t_setup = ns_to_clk(100, clk_mhz);
170 }
171
172 /* SCL High Time */
173 writel(t_high, idev->base + SCL_HIGH_PERIOD);
174 /* SCL Low Time */
175 writel(t_low, idev->base + SCL_LOW_PERIOD);
176 /* SDA Setup Time */
177 writel(t_setup, idev->base + SDA_SETUP_TIME);
178 /* SDA Hold Time, 300ns */
179 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
180 /* Filter <50ns spikes */
181 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
182
183 /* Configure Time-Out Registers */
184 tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz);
185
186 /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */
187 for (prescale = 0; prescale < 15; ++prescale) {
188 if (tmo_clk <= 0x7fff)
189 break;
190 tmo_clk >>= 1;
191 }
192 if (tmo_clk > 0x7fff)
193 tmo_clk = 0x7fff;
194
195 /* Prescale divider (log2) */
196 writel(prescale, idev->base + TIMER_CLOCK_DIV);
197 /* Timeout in divided clocks */
198 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
199
200 /* Mask all master interrupt bits */
201 i2c_int_disable(idev, ~0);
202
203 /* Interrupt enable */
204 writel(0x01, idev->base + INTERRUPT_ENABLE);
205
206 return 0;
207 }
208
i2c_m_rd(const struct i2c_msg * msg)209 static int i2c_m_rd(const struct i2c_msg *msg)
210 {
211 return (msg->flags & I2C_M_RD) != 0;
212 }
213
i2c_m_ten(const struct i2c_msg * msg)214 static int i2c_m_ten(const struct i2c_msg *msg)
215 {
216 return (msg->flags & I2C_M_TEN) != 0;
217 }
218
i2c_m_recv_len(const struct i2c_msg * msg)219 static int i2c_m_recv_len(const struct i2c_msg *msg)
220 {
221 return (msg->flags & I2C_M_RECV_LEN) != 0;
222 }
223
224 /**
225 * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block
226 * transfer length if this is the first byte of such a transfer.
227 */
axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev * idev)228 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
229 {
230 struct i2c_msg *msg = idev->msg;
231 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
232 int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd);
233
234 while (bytes_to_transfer-- > 0) {
235 int c = readl(idev->base + MST_DATA);
236
237 if (idev->msg_xfrd == 0 && i2c_m_recv_len(msg)) {
238 /*
239 * Check length byte for SMBus block read
240 */
241 if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) {
242 idev->msg_err = -EPROTO;
243 i2c_int_disable(idev, ~MST_STATUS_TSS);
244 complete(&idev->msg_complete);
245 break;
246 }
247 msg->len = 1 + c;
248 writel(msg->len, idev->base + MST_RX_XFER);
249 }
250 msg->buf[idev->msg_xfrd++] = c;
251 }
252
253 return 0;
254 }
255
256 /**
257 * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
258 * @return: Number of bytes left to transfer.
259 */
axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev * idev)260 static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev)
261 {
262 struct i2c_msg *msg = idev->msg;
263 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
264 int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd);
265 int ret = msg->len - idev->msg_xfrd - bytes_to_transfer;
266
267 while (bytes_to_transfer-- > 0)
268 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
269
270 return ret;
271 }
272
axxia_i2c_isr(int irq,void * _dev)273 static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
274 {
275 struct axxia_i2c_dev *idev = _dev;
276 u32 status;
277
278 if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST))
279 return IRQ_NONE;
280
281 /* Read interrupt status bits */
282 status = readl(idev->base + MST_INT_STATUS);
283
284 if (!idev->msg) {
285 dev_warn(idev->dev, "unexpected interrupt\n");
286 goto out;
287 }
288
289 /* RX FIFO needs service? */
290 if (i2c_m_rd(idev->msg) && (status & MST_STATUS_RFL))
291 axxia_i2c_empty_rx_fifo(idev);
292
293 /* TX FIFO needs service? */
294 if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) {
295 if (axxia_i2c_fill_tx_fifo(idev) == 0)
296 i2c_int_disable(idev, MST_STATUS_TFL);
297 }
298
299 if (unlikely(status & MST_STATUS_ERR)) {
300 /* Transfer error */
301 i2c_int_disable(idev, ~0);
302 if (status & MST_STATUS_AL)
303 idev->msg_err = -EAGAIN;
304 else if (status & MST_STATUS_NAK)
305 idev->msg_err = -ENXIO;
306 else
307 idev->msg_err = -EIO;
308 dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n",
309 status,
310 idev->msg->addr,
311 readl(idev->base + MST_RX_BYTES_XFRD),
312 readl(idev->base + MST_RX_XFER),
313 readl(idev->base + MST_TX_BYTES_XFRD),
314 readl(idev->base + MST_TX_XFER));
315 complete(&idev->msg_complete);
316 } else if (status & MST_STATUS_SCC) {
317 /* Stop completed */
318 i2c_int_disable(idev, ~MST_STATUS_TSS);
319 complete(&idev->msg_complete);
320 } else if (status & MST_STATUS_SNS) {
321 /* Transfer done */
322 i2c_int_disable(idev, ~MST_STATUS_TSS);
323 if (i2c_m_rd(idev->msg) && idev->msg_xfrd < idev->msg->len)
324 axxia_i2c_empty_rx_fifo(idev);
325 complete(&idev->msg_complete);
326 } else if (status & MST_STATUS_TSS) {
327 /* Transfer timeout */
328 idev->msg_err = -ETIMEDOUT;
329 i2c_int_disable(idev, ~MST_STATUS_TSS);
330 complete(&idev->msg_complete);
331 }
332
333 out:
334 /* Clear interrupt */
335 writel(INT_MST, idev->base + INTERRUPT_STATUS);
336
337 return IRQ_HANDLED;
338 }
339
axxia_i2c_xfer_msg(struct axxia_i2c_dev * idev,struct i2c_msg * msg)340 static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
341 {
342 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS;
343 u32 rx_xfer, tx_xfer;
344 u32 addr_1, addr_2;
345 unsigned long time_left;
346 unsigned int wt_value;
347
348 idev->msg = msg;
349 idev->msg_xfrd = 0;
350 reinit_completion(&idev->msg_complete);
351
352 if (i2c_m_ten(msg)) {
353 /* 10-bit address
354 * addr_1: 5'b11110 | addr[9:8] | (R/nW)
355 * addr_2: addr[7:0]
356 */
357 addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06);
358 addr_2 = msg->addr & 0xFF;
359 } else {
360 /* 7-bit address
361 * addr_1: addr[6:0] | (R/nW)
362 * addr_2: dont care
363 */
364 addr_1 = (msg->addr << 1) & 0xFF;
365 addr_2 = 0;
366 }
367
368 if (i2c_m_rd(msg)) {
369 /* I2C read transfer */
370 rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
371 tx_xfer = 0;
372 addr_1 |= 1; /* Set the R/nW bit of the address */
373 } else {
374 /* I2C write transfer */
375 rx_xfer = 0;
376 tx_xfer = msg->len;
377 }
378
379 writel(rx_xfer, idev->base + MST_RX_XFER);
380 writel(tx_xfer, idev->base + MST_TX_XFER);
381 writel(addr_1, idev->base + MST_ADDR_1);
382 writel(addr_2, idev->base + MST_ADDR_2);
383
384 if (i2c_m_rd(msg))
385 int_mask |= MST_STATUS_RFL;
386 else if (axxia_i2c_fill_tx_fifo(idev) != 0)
387 int_mask |= MST_STATUS_TFL;
388
389 wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL));
390 /* Disable wait timer temporarly */
391 writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
392 /* Check if timeout error happened */
393 if (idev->msg_err)
394 goto out;
395
396 /* Start manual mode */
397 writel(CMD_MANUAL, idev->base + MST_COMMAND);
398
399 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
400
401 i2c_int_enable(idev, int_mask);
402
403 time_left = wait_for_completion_timeout(&idev->msg_complete,
404 I2C_XFER_TIMEOUT);
405
406 i2c_int_disable(idev, int_mask);
407
408 if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
409 dev_warn(idev->dev, "busy after xfer\n");
410
411 if (time_left == 0) {
412 idev->msg_err = -ETIMEDOUT;
413 i2c_recover_bus(&idev->adapter);
414 axxia_i2c_init(idev);
415 }
416
417 out:
418 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO &&
419 idev->msg_err != -ETIMEDOUT)
420 axxia_i2c_init(idev);
421
422 return idev->msg_err;
423 }
424
axxia_i2c_stop(struct axxia_i2c_dev * idev)425 static int axxia_i2c_stop(struct axxia_i2c_dev *idev)
426 {
427 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC | MST_STATUS_TSS;
428 unsigned long time_left;
429
430 reinit_completion(&idev->msg_complete);
431
432 /* Issue stop */
433 writel(0xb, idev->base + MST_COMMAND);
434 i2c_int_enable(idev, int_mask);
435 time_left = wait_for_completion_timeout(&idev->msg_complete,
436 I2C_STOP_TIMEOUT);
437 i2c_int_disable(idev, int_mask);
438 if (time_left == 0)
439 return -ETIMEDOUT;
440
441 if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
442 dev_warn(idev->dev, "busy after stop\n");
443
444 return 0;
445 }
446
447 static int
axxia_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)448 axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
449 {
450 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
451 int i;
452 int ret = 0;
453
454 idev->msg_err = 0;
455 i2c_int_enable(idev, MST_STATUS_TSS);
456
457 for (i = 0; ret == 0 && i < num; ++i)
458 ret = axxia_i2c_xfer_msg(idev, &msgs[i]);
459
460 axxia_i2c_stop(idev);
461
462 return ret ? : i;
463 }
464
axxia_i2c_get_scl(struct i2c_adapter * adap)465 static int axxia_i2c_get_scl(struct i2c_adapter *adap)
466 {
467 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
468
469 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
470 }
471
axxia_i2c_set_scl(struct i2c_adapter * adap,int val)472 static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
473 {
474 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
475 u32 tmp;
476
477 /* Preserve SDA Control */
478 tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
479 if (!val)
480 tmp |= BM_SCLC;
481 writel(tmp, idev->base + I2C_BUS_MONITOR);
482 }
483
axxia_i2c_get_sda(struct i2c_adapter * adap)484 static int axxia_i2c_get_sda(struct i2c_adapter *adap)
485 {
486 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
487
488 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
489 }
490
491 static struct i2c_bus_recovery_info axxia_i2c_recovery_info = {
492 .recover_bus = i2c_generic_scl_recovery,
493 .get_scl = axxia_i2c_get_scl,
494 .set_scl = axxia_i2c_set_scl,
495 .get_sda = axxia_i2c_get_sda,
496 };
497
axxia_i2c_func(struct i2c_adapter * adap)498 static u32 axxia_i2c_func(struct i2c_adapter *adap)
499 {
500 u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
501 I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA);
502 return caps;
503 }
504
505 static const struct i2c_algorithm axxia_i2c_algo = {
506 .master_xfer = axxia_i2c_xfer,
507 .functionality = axxia_i2c_func,
508 };
509
510 static struct i2c_adapter_quirks axxia_i2c_quirks = {
511 .max_read_len = 255,
512 .max_write_len = 255,
513 };
514
axxia_i2c_probe(struct platform_device * pdev)515 static int axxia_i2c_probe(struct platform_device *pdev)
516 {
517 struct device_node *np = pdev->dev.of_node;
518 struct axxia_i2c_dev *idev = NULL;
519 struct resource *res;
520 void __iomem *base;
521 int irq;
522 int ret = 0;
523
524 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
525 if (!idev)
526 return -ENOMEM;
527
528 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
529 base = devm_ioremap_resource(&pdev->dev, res);
530 if (IS_ERR(base))
531 return PTR_ERR(base);
532
533 irq = platform_get_irq(pdev, 0);
534 if (irq < 0) {
535 dev_err(&pdev->dev, "missing interrupt resource\n");
536 return irq;
537 }
538
539 idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
540 if (IS_ERR(idev->i2c_clk)) {
541 dev_err(&pdev->dev, "missing clock\n");
542 return PTR_ERR(idev->i2c_clk);
543 }
544
545 idev->base = base;
546 idev->dev = &pdev->dev;
547 init_completion(&idev->msg_complete);
548
549 of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
550 if (idev->bus_clk_rate == 0)
551 idev->bus_clk_rate = 100000; /* default clock rate */
552
553 ret = axxia_i2c_init(idev);
554 if (ret) {
555 dev_err(&pdev->dev, "failed to initialize\n");
556 return ret;
557 }
558
559 ret = devm_request_irq(&pdev->dev, irq, axxia_i2c_isr, 0,
560 pdev->name, idev);
561 if (ret) {
562 dev_err(&pdev->dev, "failed to claim IRQ%d\n", irq);
563 return ret;
564 }
565
566 clk_prepare_enable(idev->i2c_clk);
567
568 i2c_set_adapdata(&idev->adapter, idev);
569 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
570 idev->adapter.owner = THIS_MODULE;
571 idev->adapter.algo = &axxia_i2c_algo;
572 idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
573 idev->adapter.quirks = &axxia_i2c_quirks;
574 idev->adapter.dev.parent = &pdev->dev;
575 idev->adapter.dev.of_node = pdev->dev.of_node;
576
577 platform_set_drvdata(pdev, idev);
578
579 ret = i2c_add_adapter(&idev->adapter);
580 if (ret) {
581 dev_err(&pdev->dev, "failed to add adapter\n");
582 return ret;
583 }
584
585 return 0;
586 }
587
axxia_i2c_remove(struct platform_device * pdev)588 static int axxia_i2c_remove(struct platform_device *pdev)
589 {
590 struct axxia_i2c_dev *idev = platform_get_drvdata(pdev);
591
592 clk_disable_unprepare(idev->i2c_clk);
593 i2c_del_adapter(&idev->adapter);
594
595 return 0;
596 }
597
598 /* Match table for of_platform binding */
599 static const struct of_device_id axxia_i2c_of_match[] = {
600 { .compatible = "lsi,api2c", },
601 {},
602 };
603
604 MODULE_DEVICE_TABLE(of, axxia_i2c_of_match);
605
606 static struct platform_driver axxia_i2c_driver = {
607 .probe = axxia_i2c_probe,
608 .remove = axxia_i2c_remove,
609 .driver = {
610 .name = "axxia-i2c",
611 .of_match_table = axxia_i2c_of_match,
612 },
613 };
614
615 module_platform_driver(axxia_i2c_driver);
616
617 MODULE_DESCRIPTION("Axxia I2C Bus driver");
618 MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>");
619 MODULE_LICENSE("GPL v2");
620