1 /*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 * ----------------------------------------------------------------------------
22 *
23 */
24 #include <linux/export.h>
25 #include <linux/errno.h>
26 #include <linux/err.h>
27 #include <linux/i2c.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/delay.h>
32 #include <linux/module.h>
33 #include "i2c-designware-core.h"
34
35 /*
36 * Registers offset
37 */
38 #define DW_IC_CON 0x0
39 #define DW_IC_TAR 0x4
40 #define DW_IC_DATA_CMD 0x10
41 #define DW_IC_SS_SCL_HCNT 0x14
42 #define DW_IC_SS_SCL_LCNT 0x18
43 #define DW_IC_FS_SCL_HCNT 0x1c
44 #define DW_IC_FS_SCL_LCNT 0x20
45 #define DW_IC_INTR_STAT 0x2c
46 #define DW_IC_INTR_MASK 0x30
47 #define DW_IC_RAW_INTR_STAT 0x34
48 #define DW_IC_RX_TL 0x38
49 #define DW_IC_TX_TL 0x3c
50 #define DW_IC_CLR_INTR 0x40
51 #define DW_IC_CLR_RX_UNDER 0x44
52 #define DW_IC_CLR_RX_OVER 0x48
53 #define DW_IC_CLR_TX_OVER 0x4c
54 #define DW_IC_CLR_RD_REQ 0x50
55 #define DW_IC_CLR_TX_ABRT 0x54
56 #define DW_IC_CLR_RX_DONE 0x58
57 #define DW_IC_CLR_ACTIVITY 0x5c
58 #define DW_IC_CLR_STOP_DET 0x60
59 #define DW_IC_CLR_START_DET 0x64
60 #define DW_IC_CLR_GEN_CALL 0x68
61 #define DW_IC_ENABLE 0x6c
62 #define DW_IC_STATUS 0x70
63 #define DW_IC_TXFLR 0x74
64 #define DW_IC_RXFLR 0x78
65 #define DW_IC_SDA_HOLD 0x7c
66 #define DW_IC_TX_ABRT_SOURCE 0x80
67 #define DW_IC_ENABLE_STATUS 0x9c
68 #define DW_IC_COMP_PARAM_1 0xf4
69 #define DW_IC_COMP_VERSION 0xf8
70 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
71 #define DW_IC_COMP_TYPE 0xfc
72 #define DW_IC_COMP_TYPE_VALUE 0x44570140
73
74 #define DW_IC_INTR_RX_UNDER 0x001
75 #define DW_IC_INTR_RX_OVER 0x002
76 #define DW_IC_INTR_RX_FULL 0x004
77 #define DW_IC_INTR_TX_OVER 0x008
78 #define DW_IC_INTR_TX_EMPTY 0x010
79 #define DW_IC_INTR_RD_REQ 0x020
80 #define DW_IC_INTR_TX_ABRT 0x040
81 #define DW_IC_INTR_RX_DONE 0x080
82 #define DW_IC_INTR_ACTIVITY 0x100
83 #define DW_IC_INTR_STOP_DET 0x200
84 #define DW_IC_INTR_START_DET 0x400
85 #define DW_IC_INTR_GEN_CALL 0x800
86
87 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
88 DW_IC_INTR_TX_EMPTY | \
89 DW_IC_INTR_TX_ABRT | \
90 DW_IC_INTR_STOP_DET)
91
92 #define DW_IC_STATUS_ACTIVITY 0x1
93
94 #define DW_IC_ERR_TX_ABRT 0x1
95
96 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
97
98 /*
99 * status codes
100 */
101 #define STATUS_IDLE 0x0
102 #define STATUS_WRITE_IN_PROGRESS 0x1
103 #define STATUS_READ_IN_PROGRESS 0x2
104
105 #define TIMEOUT 20 /* ms */
106
107 /*
108 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
109 *
110 * only expected abort codes are listed here
111 * refer to the datasheet for the full list
112 */
113 #define ABRT_7B_ADDR_NOACK 0
114 #define ABRT_10ADDR1_NOACK 1
115 #define ABRT_10ADDR2_NOACK 2
116 #define ABRT_TXDATA_NOACK 3
117 #define ABRT_GCALL_NOACK 4
118 #define ABRT_GCALL_READ 5
119 #define ABRT_SBYTE_ACKDET 7
120 #define ABRT_SBYTE_NORSTRT 9
121 #define ABRT_10B_RD_NORSTRT 10
122 #define ABRT_MASTER_DIS 11
123 #define ARB_LOST 12
124
125 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
126 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
127 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
128 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
129 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
130 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
131 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
132 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
133 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
134 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
135 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
136
137 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
138 DW_IC_TX_ABRT_10ADDR1_NOACK | \
139 DW_IC_TX_ABRT_10ADDR2_NOACK | \
140 DW_IC_TX_ABRT_TXDATA_NOACK | \
141 DW_IC_TX_ABRT_GCALL_NOACK)
142
143 static char *abort_sources[] = {
144 [ABRT_7B_ADDR_NOACK] =
145 "slave address not acknowledged (7bit mode)",
146 [ABRT_10ADDR1_NOACK] =
147 "first address byte not acknowledged (10bit mode)",
148 [ABRT_10ADDR2_NOACK] =
149 "second address byte not acknowledged (10bit mode)",
150 [ABRT_TXDATA_NOACK] =
151 "data not acknowledged",
152 [ABRT_GCALL_NOACK] =
153 "no acknowledgement for a general call",
154 [ABRT_GCALL_READ] =
155 "read after general call",
156 [ABRT_SBYTE_ACKDET] =
157 "start byte acknowledged",
158 [ABRT_SBYTE_NORSTRT] =
159 "trying to send start byte when restart is disabled",
160 [ABRT_10B_RD_NORSTRT] =
161 "trying to read when restart is disabled (10bit mode)",
162 [ABRT_MASTER_DIS] =
163 "trying to use disabled adapter",
164 [ARB_LOST] =
165 "lost arbitration",
166 };
167
dw_readl(struct dw_i2c_dev * dev,int offset)168 static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
169 {
170 u32 value;
171
172 if (dev->accessor_flags & ACCESS_16BIT)
173 value = readw_relaxed(dev->base + offset) |
174 (readw_relaxed(dev->base + offset + 2) << 16);
175 else
176 value = readl_relaxed(dev->base + offset);
177
178 if (dev->accessor_flags & ACCESS_SWAP)
179 return swab32(value);
180 else
181 return value;
182 }
183
dw_writel(struct dw_i2c_dev * dev,u32 b,int offset)184 static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
185 {
186 if (dev->accessor_flags & ACCESS_SWAP)
187 b = swab32(b);
188
189 if (dev->accessor_flags & ACCESS_16BIT) {
190 writew_relaxed((u16)b, dev->base + offset);
191 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
192 } else {
193 writel_relaxed(b, dev->base + offset);
194 }
195 }
196
197 static u32
i2c_dw_scl_hcnt(u32 ic_clk,u32 tSYMBOL,u32 tf,int cond,int offset)198 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
199 {
200 /*
201 * DesignWare I2C core doesn't seem to have solid strategy to meet
202 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
203 * will result in violation of the tHD;STA spec.
204 */
205 if (cond)
206 /*
207 * Conditional expression:
208 *
209 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
210 *
211 * This is based on the DW manuals, and represents an ideal
212 * configuration. The resulting I2C bus speed will be
213 * faster than any of the others.
214 *
215 * If your hardware is free from tHD;STA issue, try this one.
216 */
217 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
218 else
219 /*
220 * Conditional expression:
221 *
222 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
223 *
224 * This is just experimental rule; the tHD;STA period turned
225 * out to be proportinal to (_HCNT + 3). With this setting,
226 * we could meet both tHIGH and tHD;STA timing specs.
227 *
228 * If unsure, you'd better to take this alternative.
229 *
230 * The reason why we need to take into account "tf" here,
231 * is the same as described in i2c_dw_scl_lcnt().
232 */
233 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
234 - 3 + offset;
235 }
236
i2c_dw_scl_lcnt(u32 ic_clk,u32 tLOW,u32 tf,int offset)237 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
238 {
239 /*
240 * Conditional expression:
241 *
242 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
243 *
244 * DW I2C core starts counting the SCL CNTs for the LOW period
245 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
246 * In order to meet the tLOW timing spec, we need to take into
247 * account the fall time of SCL signal (tf). Default tf value
248 * should be 0.3 us, for safety.
249 */
250 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
251 }
252
__i2c_dw_enable(struct dw_i2c_dev * dev,bool enable)253 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
254 {
255 int timeout = 100;
256
257 do {
258 dw_writel(dev, enable, DW_IC_ENABLE);
259 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
260 return;
261
262 /*
263 * Wait 10 times the signaling period of the highest I2C
264 * transfer supported by the driver (for 400KHz this is
265 * 25us) as described in the DesignWare I2C databook.
266 */
267 usleep_range(25, 250);
268 } while (timeout--);
269
270 dev_warn(dev->dev, "timeout in %sabling adapter\n",
271 enable ? "en" : "dis");
272 }
273
274 /**
275 * i2c_dw_init() - initialize the designware i2c master hardware
276 * @dev: device private data
277 *
278 * This functions configures and enables the I2C master.
279 * This function is called during I2C init function, and in case of timeout at
280 * run time.
281 */
i2c_dw_init(struct dw_i2c_dev * dev)282 int i2c_dw_init(struct dw_i2c_dev *dev)
283 {
284 u32 input_clock_khz;
285 u32 hcnt, lcnt;
286 u32 reg;
287 u32 sda_falling_time, scl_falling_time;
288 int ret;
289
290 if (dev->acquire_lock) {
291 ret = dev->acquire_lock(dev);
292 if (ret) {
293 dev_err(dev->dev, "couldn't acquire bus ownership\n");
294 return ret;
295 }
296 }
297
298 input_clock_khz = dev->get_clk_rate_khz(dev);
299
300 reg = dw_readl(dev, DW_IC_COMP_TYPE);
301 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
302 /* Configure register endianess access */
303 dev->accessor_flags |= ACCESS_SWAP;
304 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
305 /* Configure register access mode 16bit */
306 dev->accessor_flags |= ACCESS_16BIT;
307 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
308 dev_err(dev->dev, "Unknown Synopsys component type: "
309 "0x%08x\n", reg);
310 if (dev->release_lock)
311 dev->release_lock(dev);
312 return -ENODEV;
313 }
314
315 /* Disable the adapter */
316 __i2c_dw_enable(dev, false);
317
318 /* set standard and fast speed deviders for high/low periods */
319
320 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
321 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
322
323 /* Set SCL timing parameters for standard-mode */
324 if (dev->ss_hcnt && dev->ss_lcnt) {
325 hcnt = dev->ss_hcnt;
326 lcnt = dev->ss_lcnt;
327 } else {
328 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
329 4000, /* tHD;STA = tHIGH = 4.0 us */
330 sda_falling_time,
331 0, /* 0: DW default, 1: Ideal */
332 0); /* No offset */
333 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
334 4700, /* tLOW = 4.7 us */
335 scl_falling_time,
336 0); /* No offset */
337 }
338 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
339 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
340 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
341
342 /* Set SCL timing parameters for fast-mode */
343 if (dev->fs_hcnt && dev->fs_lcnt) {
344 hcnt = dev->fs_hcnt;
345 lcnt = dev->fs_lcnt;
346 } else {
347 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
348 600, /* tHD;STA = tHIGH = 0.6 us */
349 sda_falling_time,
350 0, /* 0: DW default, 1: Ideal */
351 0); /* No offset */
352 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
353 1300, /* tLOW = 1.3 us */
354 scl_falling_time,
355 0); /* No offset */
356 }
357 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
358 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
359 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
360
361 /* Configure SDA Hold Time if required */
362 if (dev->sda_hold_time) {
363 reg = dw_readl(dev, DW_IC_COMP_VERSION);
364 if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
365 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
366 else
367 dev_warn(dev->dev,
368 "Hardware too old to adjust SDA hold time.");
369 }
370
371 /* Configure Tx/Rx FIFO threshold levels */
372 dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
373 dw_writel(dev, 0, DW_IC_RX_TL);
374
375 /* configure the i2c master */
376 dw_writel(dev, dev->master_cfg , DW_IC_CON);
377
378 if (dev->release_lock)
379 dev->release_lock(dev);
380 return 0;
381 }
382 EXPORT_SYMBOL_GPL(i2c_dw_init);
383
384 /*
385 * Waiting for bus not busy
386 */
i2c_dw_wait_bus_not_busy(struct dw_i2c_dev * dev)387 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
388 {
389 int timeout = TIMEOUT;
390
391 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
392 if (timeout <= 0) {
393 dev_warn(dev->dev, "timeout waiting for bus ready\n");
394 return -ETIMEDOUT;
395 }
396 timeout--;
397 usleep_range(1000, 1100);
398 }
399
400 return 0;
401 }
402
i2c_dw_xfer_init(struct dw_i2c_dev * dev)403 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
404 {
405 struct i2c_msg *msgs = dev->msgs;
406 u32 ic_con, ic_tar = 0;
407
408 /* Disable the adapter */
409 __i2c_dw_enable(dev, false);
410
411 /* if the slave address is ten bit address, enable 10BITADDR */
412 ic_con = dw_readl(dev, DW_IC_CON);
413 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
414 ic_con |= DW_IC_CON_10BITADDR_MASTER;
415 /*
416 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
417 * mode has to be enabled via bit 12 of IC_TAR register.
418 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
419 * detected from registers.
420 */
421 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
422 } else {
423 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
424 }
425
426 dw_writel(dev, ic_con, DW_IC_CON);
427
428 /*
429 * Set the slave (target) address and enable 10-bit addressing mode
430 * if applicable.
431 */
432 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
433
434 /* enforce disabled interrupts (due to HW issues) */
435 i2c_dw_disable_int(dev);
436
437 /* Enable the adapter */
438 __i2c_dw_enable(dev, true);
439
440 /* Clear and enable interrupts */
441 dw_readl(dev, DW_IC_CLR_INTR);
442 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
443 }
444
445 /*
446 * Initiate (and continue) low level master read/write transaction.
447 * This function is only called from i2c_dw_isr, and pumping i2c_msg
448 * messages into the tx buffer. Even if the size of i2c_msg data is
449 * longer than the size of the tx buffer, it handles everything.
450 */
451 static void
i2c_dw_xfer_msg(struct dw_i2c_dev * dev)452 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
453 {
454 struct i2c_msg *msgs = dev->msgs;
455 u32 intr_mask;
456 int tx_limit, rx_limit;
457 u32 addr = msgs[dev->msg_write_idx].addr;
458 u32 buf_len = dev->tx_buf_len;
459 u8 *buf = dev->tx_buf;
460 bool need_restart = false;
461
462 intr_mask = DW_IC_INTR_DEFAULT_MASK;
463
464 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
465 /*
466 * if target address has changed, we need to
467 * reprogram the target address in the i2c
468 * adapter when we are done with this transfer
469 */
470 if (msgs[dev->msg_write_idx].addr != addr) {
471 dev_err(dev->dev,
472 "%s: invalid target address\n", __func__);
473 dev->msg_err = -EINVAL;
474 break;
475 }
476
477 if (msgs[dev->msg_write_idx].len == 0) {
478 dev_err(dev->dev,
479 "%s: invalid message length\n", __func__);
480 dev->msg_err = -EINVAL;
481 break;
482 }
483
484 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
485 /* new i2c_msg */
486 buf = msgs[dev->msg_write_idx].buf;
487 buf_len = msgs[dev->msg_write_idx].len;
488
489 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
490 * IC_RESTART_EN are set, we must manually
491 * set restart bit between messages.
492 */
493 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
494 (dev->msg_write_idx > 0))
495 need_restart = true;
496 }
497
498 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
499 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
500
501 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
502 u32 cmd = 0;
503
504 /*
505 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
506 * manually set the stop bit. However, it cannot be
507 * detected from the registers so we set it always
508 * when writing/reading the last byte.
509 */
510 if (dev->msg_write_idx == dev->msgs_num - 1 &&
511 buf_len == 1)
512 cmd |= BIT(9);
513
514 if (need_restart) {
515 cmd |= BIT(10);
516 need_restart = false;
517 }
518
519 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
520
521 /* avoid rx buffer overrun */
522 if (rx_limit - dev->rx_outstanding <= 0)
523 break;
524
525 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
526 rx_limit--;
527 dev->rx_outstanding++;
528 } else
529 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
530 tx_limit--; buf_len--;
531 }
532
533 dev->tx_buf = buf;
534 dev->tx_buf_len = buf_len;
535
536 if (buf_len > 0) {
537 /* more bytes to be written */
538 dev->status |= STATUS_WRITE_IN_PROGRESS;
539 break;
540 } else
541 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
542 }
543
544 /*
545 * If i2c_msg index search is completed, we don't need TX_EMPTY
546 * interrupt any more.
547 */
548 if (dev->msg_write_idx == dev->msgs_num)
549 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
550
551 if (dev->msg_err)
552 intr_mask = 0;
553
554 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
555 }
556
557 static void
i2c_dw_read(struct dw_i2c_dev * dev)558 i2c_dw_read(struct dw_i2c_dev *dev)
559 {
560 struct i2c_msg *msgs = dev->msgs;
561 int rx_valid;
562
563 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
564 u32 len;
565 u8 *buf;
566
567 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
568 continue;
569
570 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
571 len = msgs[dev->msg_read_idx].len;
572 buf = msgs[dev->msg_read_idx].buf;
573 } else {
574 len = dev->rx_buf_len;
575 buf = dev->rx_buf;
576 }
577
578 rx_valid = dw_readl(dev, DW_IC_RXFLR);
579
580 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
581 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
582 dev->rx_outstanding--;
583 }
584
585 if (len > 0) {
586 dev->status |= STATUS_READ_IN_PROGRESS;
587 dev->rx_buf_len = len;
588 dev->rx_buf = buf;
589 return;
590 } else
591 dev->status &= ~STATUS_READ_IN_PROGRESS;
592 }
593 }
594
i2c_dw_handle_tx_abort(struct dw_i2c_dev * dev)595 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
596 {
597 unsigned long abort_source = dev->abort_source;
598 int i;
599
600 if (abort_source & DW_IC_TX_ABRT_NOACK) {
601 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
602 dev_dbg(dev->dev,
603 "%s: %s\n", __func__, abort_sources[i]);
604 return -EREMOTEIO;
605 }
606
607 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
608 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
609
610 if (abort_source & DW_IC_TX_ARB_LOST)
611 return -EAGAIN;
612 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
613 return -EINVAL; /* wrong msgs[] data */
614 else
615 return -EIO;
616 }
617
618 /*
619 * Prepare controller for a transaction and call i2c_dw_xfer_msg
620 */
621 static int
i2c_dw_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)622 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
623 {
624 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
625 int ret;
626
627 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
628
629 mutex_lock(&dev->lock);
630 pm_runtime_get_sync(dev->dev);
631
632 reinit_completion(&dev->cmd_complete);
633 dev->msgs = msgs;
634 dev->msgs_num = num;
635 dev->cmd_err = 0;
636 dev->msg_write_idx = 0;
637 dev->msg_read_idx = 0;
638 dev->msg_err = 0;
639 dev->status = STATUS_IDLE;
640 dev->abort_source = 0;
641 dev->rx_outstanding = 0;
642
643 if (dev->acquire_lock) {
644 ret = dev->acquire_lock(dev);
645 if (ret) {
646 dev_err(dev->dev, "couldn't acquire bus ownership\n");
647 goto done_nolock;
648 }
649 }
650
651 ret = i2c_dw_wait_bus_not_busy(dev);
652 if (ret < 0)
653 goto done;
654
655 /* start the transfers */
656 i2c_dw_xfer_init(dev);
657
658 /* wait for tx to complete */
659 if (!wait_for_completion_timeout(&dev->cmd_complete, HZ)) {
660 dev_err(dev->dev, "controller timed out\n");
661 /* i2c_dw_init implicitly disables the adapter */
662 i2c_dw_init(dev);
663 ret = -ETIMEDOUT;
664 goto done;
665 }
666
667 /*
668 * We must disable the adapter before unlocking the &dev->lock mutex
669 * below. Otherwise the hardware might continue generating interrupts
670 * which in turn causes a race condition with the following transfer.
671 * Needs some more investigation if the additional interrupts are
672 * a hardware bug or this driver doesn't handle them correctly yet.
673 */
674 __i2c_dw_enable(dev, false);
675
676 if (dev->msg_err) {
677 ret = dev->msg_err;
678 goto done;
679 }
680
681 /* no error */
682 if (likely(!dev->cmd_err)) {
683 ret = num;
684 goto done;
685 }
686
687 /* We have an error */
688 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
689 ret = i2c_dw_handle_tx_abort(dev);
690 goto done;
691 }
692 ret = -EIO;
693
694 done:
695 if (dev->release_lock)
696 dev->release_lock(dev);
697
698 done_nolock:
699 pm_runtime_mark_last_busy(dev->dev);
700 pm_runtime_put_autosuspend(dev->dev);
701 mutex_unlock(&dev->lock);
702
703 return ret;
704 }
705
i2c_dw_func(struct i2c_adapter * adap)706 static u32 i2c_dw_func(struct i2c_adapter *adap)
707 {
708 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
709 return dev->functionality;
710 }
711
712 static struct i2c_algorithm i2c_dw_algo = {
713 .master_xfer = i2c_dw_xfer,
714 .functionality = i2c_dw_func,
715 };
716
i2c_dw_read_clear_intrbits(struct dw_i2c_dev * dev)717 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
718 {
719 u32 stat;
720
721 /*
722 * The IC_INTR_STAT register just indicates "enabled" interrupts.
723 * Ths unmasked raw version of interrupt status bits are available
724 * in the IC_RAW_INTR_STAT register.
725 *
726 * That is,
727 * stat = dw_readl(IC_INTR_STAT);
728 * equals to,
729 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
730 *
731 * The raw version might be useful for debugging purposes.
732 */
733 stat = dw_readl(dev, DW_IC_INTR_STAT);
734
735 /*
736 * Do not use the IC_CLR_INTR register to clear interrupts, or
737 * you'll miss some interrupts, triggered during the period from
738 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
739 *
740 * Instead, use the separately-prepared IC_CLR_* registers.
741 */
742 if (stat & DW_IC_INTR_RX_UNDER)
743 dw_readl(dev, DW_IC_CLR_RX_UNDER);
744 if (stat & DW_IC_INTR_RX_OVER)
745 dw_readl(dev, DW_IC_CLR_RX_OVER);
746 if (stat & DW_IC_INTR_TX_OVER)
747 dw_readl(dev, DW_IC_CLR_TX_OVER);
748 if (stat & DW_IC_INTR_RD_REQ)
749 dw_readl(dev, DW_IC_CLR_RD_REQ);
750 if (stat & DW_IC_INTR_TX_ABRT) {
751 /*
752 * The IC_TX_ABRT_SOURCE register is cleared whenever
753 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
754 */
755 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
756 dw_readl(dev, DW_IC_CLR_TX_ABRT);
757 }
758 if (stat & DW_IC_INTR_RX_DONE)
759 dw_readl(dev, DW_IC_CLR_RX_DONE);
760 if (stat & DW_IC_INTR_ACTIVITY)
761 dw_readl(dev, DW_IC_CLR_ACTIVITY);
762 if (stat & DW_IC_INTR_STOP_DET)
763 dw_readl(dev, DW_IC_CLR_STOP_DET);
764 if (stat & DW_IC_INTR_START_DET)
765 dw_readl(dev, DW_IC_CLR_START_DET);
766 if (stat & DW_IC_INTR_GEN_CALL)
767 dw_readl(dev, DW_IC_CLR_GEN_CALL);
768
769 return stat;
770 }
771
772 /*
773 * Interrupt service routine. This gets called whenever an I2C interrupt
774 * occurs.
775 */
i2c_dw_isr(int this_irq,void * dev_id)776 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
777 {
778 struct dw_i2c_dev *dev = dev_id;
779 u32 stat, enabled;
780
781 enabled = dw_readl(dev, DW_IC_ENABLE);
782 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
783 dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
784 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
785 return IRQ_NONE;
786
787 stat = i2c_dw_read_clear_intrbits(dev);
788
789 if (stat & DW_IC_INTR_TX_ABRT) {
790 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
791 dev->status = STATUS_IDLE;
792
793 /*
794 * Anytime TX_ABRT is set, the contents of the tx/rx
795 * buffers are flushed. Make sure to skip them.
796 */
797 dw_writel(dev, 0, DW_IC_INTR_MASK);
798 goto tx_aborted;
799 }
800
801 if (stat & DW_IC_INTR_RX_FULL)
802 i2c_dw_read(dev);
803
804 if (stat & DW_IC_INTR_TX_EMPTY)
805 i2c_dw_xfer_msg(dev);
806
807 /*
808 * No need to modify or disable the interrupt mask here.
809 * i2c_dw_xfer_msg() will take care of it according to
810 * the current transmit status.
811 */
812
813 tx_aborted:
814 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
815 complete(&dev->cmd_complete);
816 else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
817 /* workaround to trigger pending interrupt */
818 stat = dw_readl(dev, DW_IC_INTR_MASK);
819 i2c_dw_disable_int(dev);
820 dw_writel(dev, stat, DW_IC_INTR_MASK);
821 }
822
823 return IRQ_HANDLED;
824 }
825
i2c_dw_disable(struct dw_i2c_dev * dev)826 void i2c_dw_disable(struct dw_i2c_dev *dev)
827 {
828 /* Disable controller */
829 __i2c_dw_enable(dev, false);
830
831 /* Disable all interupts */
832 dw_writel(dev, 0, DW_IC_INTR_MASK);
833 dw_readl(dev, DW_IC_CLR_INTR);
834 }
835 EXPORT_SYMBOL_GPL(i2c_dw_disable);
836
i2c_dw_disable_int(struct dw_i2c_dev * dev)837 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
838 {
839 dw_writel(dev, 0, DW_IC_INTR_MASK);
840 }
841 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
842
i2c_dw_read_comp_param(struct dw_i2c_dev * dev)843 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
844 {
845 return dw_readl(dev, DW_IC_COMP_PARAM_1);
846 }
847 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
848
i2c_dw_probe(struct dw_i2c_dev * dev)849 int i2c_dw_probe(struct dw_i2c_dev *dev)
850 {
851 struct i2c_adapter *adap = &dev->adapter;
852 int r;
853
854 init_completion(&dev->cmd_complete);
855 mutex_init(&dev->lock);
856
857 r = i2c_dw_init(dev);
858 if (r)
859 return r;
860
861 snprintf(adap->name, sizeof(adap->name),
862 "Synopsys DesignWare I2C adapter");
863 adap->algo = &i2c_dw_algo;
864 adap->dev.parent = dev->dev;
865 i2c_set_adapdata(adap, dev);
866
867 i2c_dw_disable_int(dev);
868 r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
869 IRQF_SHARED | IRQF_COND_SUSPEND,
870 dev_name(dev->dev), dev);
871 if (r) {
872 dev_err(dev->dev, "failure requesting irq %i: %d\n",
873 dev->irq, r);
874 return r;
875 }
876
877 r = i2c_add_numbered_adapter(adap);
878 if (r)
879 dev_err(dev->dev, "failure adding adapter: %d\n", r);
880
881 return r;
882 }
883 EXPORT_SYMBOL_GPL(i2c_dw_probe);
884
885 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
886 MODULE_LICENSE("GPL");
887