1 /*
2 * intel_idle.c - native hardware idle loop for modern Intel processors
3 *
4 * Copyright (c) 2013, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21 /*
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
26 */
27
28 /*
29 * Design Assumptions
30 *
31 * All CPUs have same idle states as boot CPU
32 *
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
35 */
36
37 /*
38 * Known limitations
39 *
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
44 *
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
48 *
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
51 */
52
53 /* un-comment DEBUG to enable pr_debug() statements */
54 #define DEBUG
55
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/tick.h>
59 #include <trace/events/power.h>
60 #include <linux/sched.h>
61 #include <linux/notifier.h>
62 #include <linux/cpu.h>
63 #include <linux/module.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/mwait.h>
66 #include <asm/msr.h>
67
68 #define INTEL_IDLE_VERSION "0.4.1"
69 #define PREFIX "intel_idle: "
70
71 static struct cpuidle_driver intel_idle_driver = {
72 .name = "intel_idle",
73 .owner = THIS_MODULE,
74 };
75 /* intel_idle.max_cstate=0 disables driver */
76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
77
78 static unsigned int mwait_substates;
79
80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
81 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
82 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
83
84 struct idle_cpu {
85 struct cpuidle_state *state_table;
86
87 /*
88 * Hardware C-state auto-demotion may not always be optimal.
89 * Indicate which enable bits to clear here.
90 */
91 unsigned long auto_demotion_disable_flags;
92 bool byt_auto_demotion_disable_flag;
93 bool disable_promotion_to_c1e;
94 };
95
96 static const struct idle_cpu *icpu;
97 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
98 static int intel_idle(struct cpuidle_device *dev,
99 struct cpuidle_driver *drv, int index);
100 static void intel_idle_freeze(struct cpuidle_device *dev,
101 struct cpuidle_driver *drv, int index);
102 static int intel_idle_cpu_init(int cpu);
103
104 static struct cpuidle_state *cpuidle_state_table;
105
106 /*
107 * Set this flag for states where the HW flushes the TLB for us
108 * and so we don't need cross-calls to keep it consistent.
109 * If this flag is set, SW flushes the TLB, so even if the
110 * HW doesn't do the flushing, this flag is safe to use.
111 */
112 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
113
114 /*
115 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
116 * the C-state (top nibble) and sub-state (bottom nibble)
117 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
118 *
119 * We store the hint at the top of our "flags" for each state.
120 */
121 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
122 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
123
124 /*
125 * States are indexed by the cstate number,
126 * which is also the index into the MWAIT hint array.
127 * Thus C0 is a dummy.
128 */
129 static struct cpuidle_state nehalem_cstates[] = {
130 {
131 .name = "C1-NHM",
132 .desc = "MWAIT 0x00",
133 .flags = MWAIT2flg(0x00),
134 .exit_latency = 3,
135 .target_residency = 6,
136 .enter = &intel_idle,
137 .enter_freeze = intel_idle_freeze, },
138 {
139 .name = "C1E-NHM",
140 .desc = "MWAIT 0x01",
141 .flags = MWAIT2flg(0x01),
142 .exit_latency = 10,
143 .target_residency = 20,
144 .enter = &intel_idle,
145 .enter_freeze = intel_idle_freeze, },
146 {
147 .name = "C3-NHM",
148 .desc = "MWAIT 0x10",
149 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
150 .exit_latency = 20,
151 .target_residency = 80,
152 .enter = &intel_idle,
153 .enter_freeze = intel_idle_freeze, },
154 {
155 .name = "C6-NHM",
156 .desc = "MWAIT 0x20",
157 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
158 .exit_latency = 200,
159 .target_residency = 800,
160 .enter = &intel_idle,
161 .enter_freeze = intel_idle_freeze, },
162 {
163 .enter = NULL }
164 };
165
166 static struct cpuidle_state snb_cstates[] = {
167 {
168 .name = "C1-SNB",
169 .desc = "MWAIT 0x00",
170 .flags = MWAIT2flg(0x00),
171 .exit_latency = 2,
172 .target_residency = 2,
173 .enter = &intel_idle,
174 .enter_freeze = intel_idle_freeze, },
175 {
176 .name = "C1E-SNB",
177 .desc = "MWAIT 0x01",
178 .flags = MWAIT2flg(0x01),
179 .exit_latency = 10,
180 .target_residency = 20,
181 .enter = &intel_idle,
182 .enter_freeze = intel_idle_freeze, },
183 {
184 .name = "C3-SNB",
185 .desc = "MWAIT 0x10",
186 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
187 .exit_latency = 80,
188 .target_residency = 211,
189 .enter = &intel_idle,
190 .enter_freeze = intel_idle_freeze, },
191 {
192 .name = "C6-SNB",
193 .desc = "MWAIT 0x20",
194 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
195 .exit_latency = 104,
196 .target_residency = 345,
197 .enter = &intel_idle,
198 .enter_freeze = intel_idle_freeze, },
199 {
200 .name = "C7-SNB",
201 .desc = "MWAIT 0x30",
202 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
203 .exit_latency = 109,
204 .target_residency = 345,
205 .enter = &intel_idle,
206 .enter_freeze = intel_idle_freeze, },
207 {
208 .enter = NULL }
209 };
210
211 static struct cpuidle_state byt_cstates[] = {
212 {
213 .name = "C1-BYT",
214 .desc = "MWAIT 0x00",
215 .flags = MWAIT2flg(0x00),
216 .exit_latency = 1,
217 .target_residency = 1,
218 .enter = &intel_idle,
219 .enter_freeze = intel_idle_freeze, },
220 {
221 .name = "C6N-BYT",
222 .desc = "MWAIT 0x58",
223 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
224 .exit_latency = 300,
225 .target_residency = 275,
226 .enter = &intel_idle,
227 .enter_freeze = intel_idle_freeze, },
228 {
229 .name = "C6S-BYT",
230 .desc = "MWAIT 0x52",
231 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
232 .exit_latency = 500,
233 .target_residency = 560,
234 .enter = &intel_idle,
235 .enter_freeze = intel_idle_freeze, },
236 {
237 .name = "C7-BYT",
238 .desc = "MWAIT 0x60",
239 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
240 .exit_latency = 1200,
241 .target_residency = 4000,
242 .enter = &intel_idle,
243 .enter_freeze = intel_idle_freeze, },
244 {
245 .name = "C7S-BYT",
246 .desc = "MWAIT 0x64",
247 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
248 .exit_latency = 10000,
249 .target_residency = 20000,
250 .enter = &intel_idle,
251 .enter_freeze = intel_idle_freeze, },
252 {
253 .enter = NULL }
254 };
255
256 static struct cpuidle_state cht_cstates[] = {
257 {
258 .name = "C1-CHT",
259 .desc = "MWAIT 0x00",
260 .flags = MWAIT2flg(0x00),
261 .exit_latency = 1,
262 .target_residency = 1,
263 .enter = &intel_idle,
264 .enter_freeze = intel_idle_freeze, },
265 {
266 .name = "C6N-CHT",
267 .desc = "MWAIT 0x58",
268 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
269 .exit_latency = 80,
270 .target_residency = 275,
271 .enter = &intel_idle,
272 .enter_freeze = intel_idle_freeze, },
273 {
274 .name = "C6S-CHT",
275 .desc = "MWAIT 0x52",
276 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
277 .exit_latency = 200,
278 .target_residency = 560,
279 .enter = &intel_idle,
280 .enter_freeze = intel_idle_freeze, },
281 {
282 .name = "C7-CHT",
283 .desc = "MWAIT 0x60",
284 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
285 .exit_latency = 1200,
286 .target_residency = 4000,
287 .enter = &intel_idle,
288 .enter_freeze = intel_idle_freeze, },
289 {
290 .name = "C7S-CHT",
291 .desc = "MWAIT 0x64",
292 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
293 .exit_latency = 10000,
294 .target_residency = 20000,
295 .enter = &intel_idle,
296 .enter_freeze = intel_idle_freeze, },
297 {
298 .enter = NULL }
299 };
300
301 static struct cpuidle_state ivb_cstates[] = {
302 {
303 .name = "C1-IVB",
304 .desc = "MWAIT 0x00",
305 .flags = MWAIT2flg(0x00),
306 .exit_latency = 1,
307 .target_residency = 1,
308 .enter = &intel_idle,
309 .enter_freeze = intel_idle_freeze, },
310 {
311 .name = "C1E-IVB",
312 .desc = "MWAIT 0x01",
313 .flags = MWAIT2flg(0x01),
314 .exit_latency = 10,
315 .target_residency = 20,
316 .enter = &intel_idle,
317 .enter_freeze = intel_idle_freeze, },
318 {
319 .name = "C3-IVB",
320 .desc = "MWAIT 0x10",
321 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
322 .exit_latency = 59,
323 .target_residency = 156,
324 .enter = &intel_idle,
325 .enter_freeze = intel_idle_freeze, },
326 {
327 .name = "C6-IVB",
328 .desc = "MWAIT 0x20",
329 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
330 .exit_latency = 80,
331 .target_residency = 300,
332 .enter = &intel_idle,
333 .enter_freeze = intel_idle_freeze, },
334 {
335 .name = "C7-IVB",
336 .desc = "MWAIT 0x30",
337 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
338 .exit_latency = 87,
339 .target_residency = 300,
340 .enter = &intel_idle,
341 .enter_freeze = intel_idle_freeze, },
342 {
343 .enter = NULL }
344 };
345
346 static struct cpuidle_state ivt_cstates[] = {
347 {
348 .name = "C1-IVT",
349 .desc = "MWAIT 0x00",
350 .flags = MWAIT2flg(0x00),
351 .exit_latency = 1,
352 .target_residency = 1,
353 .enter = &intel_idle,
354 .enter_freeze = intel_idle_freeze, },
355 {
356 .name = "C1E-IVT",
357 .desc = "MWAIT 0x01",
358 .flags = MWAIT2flg(0x01),
359 .exit_latency = 10,
360 .target_residency = 80,
361 .enter = &intel_idle,
362 .enter_freeze = intel_idle_freeze, },
363 {
364 .name = "C3-IVT",
365 .desc = "MWAIT 0x10",
366 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
367 .exit_latency = 59,
368 .target_residency = 156,
369 .enter = &intel_idle,
370 .enter_freeze = intel_idle_freeze, },
371 {
372 .name = "C6-IVT",
373 .desc = "MWAIT 0x20",
374 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
375 .exit_latency = 82,
376 .target_residency = 300,
377 .enter = &intel_idle,
378 .enter_freeze = intel_idle_freeze, },
379 {
380 .enter = NULL }
381 };
382
383 static struct cpuidle_state ivt_cstates_4s[] = {
384 {
385 .name = "C1-IVT-4S",
386 .desc = "MWAIT 0x00",
387 .flags = MWAIT2flg(0x00),
388 .exit_latency = 1,
389 .target_residency = 1,
390 .enter = &intel_idle,
391 .enter_freeze = intel_idle_freeze, },
392 {
393 .name = "C1E-IVT-4S",
394 .desc = "MWAIT 0x01",
395 .flags = MWAIT2flg(0x01),
396 .exit_latency = 10,
397 .target_residency = 250,
398 .enter = &intel_idle,
399 .enter_freeze = intel_idle_freeze, },
400 {
401 .name = "C3-IVT-4S",
402 .desc = "MWAIT 0x10",
403 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
404 .exit_latency = 59,
405 .target_residency = 300,
406 .enter = &intel_idle,
407 .enter_freeze = intel_idle_freeze, },
408 {
409 .name = "C6-IVT-4S",
410 .desc = "MWAIT 0x20",
411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
412 .exit_latency = 84,
413 .target_residency = 400,
414 .enter = &intel_idle,
415 .enter_freeze = intel_idle_freeze, },
416 {
417 .enter = NULL }
418 };
419
420 static struct cpuidle_state ivt_cstates_8s[] = {
421 {
422 .name = "C1-IVT-8S",
423 .desc = "MWAIT 0x00",
424 .flags = MWAIT2flg(0x00),
425 .exit_latency = 1,
426 .target_residency = 1,
427 .enter = &intel_idle,
428 .enter_freeze = intel_idle_freeze, },
429 {
430 .name = "C1E-IVT-8S",
431 .desc = "MWAIT 0x01",
432 .flags = MWAIT2flg(0x01),
433 .exit_latency = 10,
434 .target_residency = 500,
435 .enter = &intel_idle,
436 .enter_freeze = intel_idle_freeze, },
437 {
438 .name = "C3-IVT-8S",
439 .desc = "MWAIT 0x10",
440 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
441 .exit_latency = 59,
442 .target_residency = 600,
443 .enter = &intel_idle,
444 .enter_freeze = intel_idle_freeze, },
445 {
446 .name = "C6-IVT-8S",
447 .desc = "MWAIT 0x20",
448 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
449 .exit_latency = 88,
450 .target_residency = 700,
451 .enter = &intel_idle,
452 .enter_freeze = intel_idle_freeze, },
453 {
454 .enter = NULL }
455 };
456
457 static struct cpuidle_state hsw_cstates[] = {
458 {
459 .name = "C1-HSW",
460 .desc = "MWAIT 0x00",
461 .flags = MWAIT2flg(0x00),
462 .exit_latency = 2,
463 .target_residency = 2,
464 .enter = &intel_idle,
465 .enter_freeze = intel_idle_freeze, },
466 {
467 .name = "C1E-HSW",
468 .desc = "MWAIT 0x01",
469 .flags = MWAIT2flg(0x01),
470 .exit_latency = 10,
471 .target_residency = 20,
472 .enter = &intel_idle,
473 .enter_freeze = intel_idle_freeze, },
474 {
475 .name = "C3-HSW",
476 .desc = "MWAIT 0x10",
477 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
478 .exit_latency = 33,
479 .target_residency = 100,
480 .enter = &intel_idle,
481 .enter_freeze = intel_idle_freeze, },
482 {
483 .name = "C6-HSW",
484 .desc = "MWAIT 0x20",
485 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
486 .exit_latency = 133,
487 .target_residency = 400,
488 .enter = &intel_idle,
489 .enter_freeze = intel_idle_freeze, },
490 {
491 .name = "C7s-HSW",
492 .desc = "MWAIT 0x32",
493 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
494 .exit_latency = 166,
495 .target_residency = 500,
496 .enter = &intel_idle,
497 .enter_freeze = intel_idle_freeze, },
498 {
499 .name = "C8-HSW",
500 .desc = "MWAIT 0x40",
501 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
502 .exit_latency = 300,
503 .target_residency = 900,
504 .enter = &intel_idle,
505 .enter_freeze = intel_idle_freeze, },
506 {
507 .name = "C9-HSW",
508 .desc = "MWAIT 0x50",
509 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
510 .exit_latency = 600,
511 .target_residency = 1800,
512 .enter = &intel_idle,
513 .enter_freeze = intel_idle_freeze, },
514 {
515 .name = "C10-HSW",
516 .desc = "MWAIT 0x60",
517 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
518 .exit_latency = 2600,
519 .target_residency = 7700,
520 .enter = &intel_idle,
521 .enter_freeze = intel_idle_freeze, },
522 {
523 .enter = NULL }
524 };
525 static struct cpuidle_state bdw_cstates[] = {
526 {
527 .name = "C1-BDW",
528 .desc = "MWAIT 0x00",
529 .flags = MWAIT2flg(0x00),
530 .exit_latency = 2,
531 .target_residency = 2,
532 .enter = &intel_idle,
533 .enter_freeze = intel_idle_freeze, },
534 {
535 .name = "C1E-BDW",
536 .desc = "MWAIT 0x01",
537 .flags = MWAIT2flg(0x01),
538 .exit_latency = 10,
539 .target_residency = 20,
540 .enter = &intel_idle,
541 .enter_freeze = intel_idle_freeze, },
542 {
543 .name = "C3-BDW",
544 .desc = "MWAIT 0x10",
545 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
546 .exit_latency = 40,
547 .target_residency = 100,
548 .enter = &intel_idle,
549 .enter_freeze = intel_idle_freeze, },
550 {
551 .name = "C6-BDW",
552 .desc = "MWAIT 0x20",
553 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
554 .exit_latency = 133,
555 .target_residency = 400,
556 .enter = &intel_idle,
557 .enter_freeze = intel_idle_freeze, },
558 {
559 .name = "C7s-BDW",
560 .desc = "MWAIT 0x32",
561 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
562 .exit_latency = 166,
563 .target_residency = 500,
564 .enter = &intel_idle,
565 .enter_freeze = intel_idle_freeze, },
566 {
567 .name = "C8-BDW",
568 .desc = "MWAIT 0x40",
569 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
570 .exit_latency = 300,
571 .target_residency = 900,
572 .enter = &intel_idle,
573 .enter_freeze = intel_idle_freeze, },
574 {
575 .name = "C9-BDW",
576 .desc = "MWAIT 0x50",
577 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
578 .exit_latency = 600,
579 .target_residency = 1800,
580 .enter = &intel_idle,
581 .enter_freeze = intel_idle_freeze, },
582 {
583 .name = "C10-BDW",
584 .desc = "MWAIT 0x60",
585 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
586 .exit_latency = 2600,
587 .target_residency = 7700,
588 .enter = &intel_idle,
589 .enter_freeze = intel_idle_freeze, },
590 {
591 .enter = NULL }
592 };
593
594 static struct cpuidle_state skl_cstates[] = {
595 {
596 .name = "C1-SKL",
597 .desc = "MWAIT 0x00",
598 .flags = MWAIT2flg(0x00),
599 .exit_latency = 2,
600 .target_residency = 2,
601 .enter = &intel_idle,
602 .enter_freeze = intel_idle_freeze, },
603 {
604 .name = "C1E-SKL",
605 .desc = "MWAIT 0x01",
606 .flags = MWAIT2flg(0x01),
607 .exit_latency = 10,
608 .target_residency = 20,
609 .enter = &intel_idle,
610 .enter_freeze = intel_idle_freeze, },
611 {
612 .name = "C3-SKL",
613 .desc = "MWAIT 0x10",
614 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
615 .exit_latency = 70,
616 .target_residency = 100,
617 .enter = &intel_idle,
618 .enter_freeze = intel_idle_freeze, },
619 {
620 .name = "C6-SKL",
621 .desc = "MWAIT 0x20",
622 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
623 .exit_latency = 85,
624 .target_residency = 200,
625 .enter = &intel_idle,
626 .enter_freeze = intel_idle_freeze, },
627 {
628 .name = "C7s-SKL",
629 .desc = "MWAIT 0x33",
630 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
631 .exit_latency = 124,
632 .target_residency = 800,
633 .enter = &intel_idle,
634 .enter_freeze = intel_idle_freeze, },
635 {
636 .name = "C8-SKL",
637 .desc = "MWAIT 0x40",
638 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
639 .exit_latency = 200,
640 .target_residency = 800,
641 .enter = &intel_idle,
642 .enter_freeze = intel_idle_freeze, },
643 {
644 .name = "C9-SKL",
645 .desc = "MWAIT 0x50",
646 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
647 .exit_latency = 480,
648 .target_residency = 5000,
649 .enter = &intel_idle,
650 .enter_freeze = intel_idle_freeze, },
651 {
652 .name = "C10-SKL",
653 .desc = "MWAIT 0x60",
654 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
655 .exit_latency = 890,
656 .target_residency = 5000,
657 .enter = &intel_idle,
658 .enter_freeze = intel_idle_freeze, },
659 {
660 .enter = NULL }
661 };
662
663 static struct cpuidle_state atom_cstates[] = {
664 {
665 .name = "C1E-ATM",
666 .desc = "MWAIT 0x00",
667 .flags = MWAIT2flg(0x00),
668 .exit_latency = 10,
669 .target_residency = 20,
670 .enter = &intel_idle,
671 .enter_freeze = intel_idle_freeze, },
672 {
673 .name = "C2-ATM",
674 .desc = "MWAIT 0x10",
675 .flags = MWAIT2flg(0x10),
676 .exit_latency = 20,
677 .target_residency = 80,
678 .enter = &intel_idle,
679 .enter_freeze = intel_idle_freeze, },
680 {
681 .name = "C4-ATM",
682 .desc = "MWAIT 0x30",
683 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
684 .exit_latency = 100,
685 .target_residency = 400,
686 .enter = &intel_idle,
687 .enter_freeze = intel_idle_freeze, },
688 {
689 .name = "C6-ATM",
690 .desc = "MWAIT 0x52",
691 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
692 .exit_latency = 140,
693 .target_residency = 560,
694 .enter = &intel_idle,
695 .enter_freeze = intel_idle_freeze, },
696 {
697 .enter = NULL }
698 };
699 static struct cpuidle_state avn_cstates[] = {
700 {
701 .name = "C1-AVN",
702 .desc = "MWAIT 0x00",
703 .flags = MWAIT2flg(0x00),
704 .exit_latency = 2,
705 .target_residency = 2,
706 .enter = &intel_idle,
707 .enter_freeze = intel_idle_freeze, },
708 {
709 .name = "C6-AVN",
710 .desc = "MWAIT 0x51",
711 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
712 .exit_latency = 15,
713 .target_residency = 45,
714 .enter = &intel_idle,
715 .enter_freeze = intel_idle_freeze, },
716 {
717 .enter = NULL }
718 };
719 static struct cpuidle_state knl_cstates[] = {
720 {
721 .name = "C1-KNL",
722 .desc = "MWAIT 0x00",
723 .flags = MWAIT2flg(0x00),
724 .exit_latency = 1,
725 .target_residency = 2,
726 .enter = &intel_idle,
727 .enter_freeze = intel_idle_freeze },
728 {
729 .name = "C6-KNL",
730 .desc = "MWAIT 0x10",
731 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
732 .exit_latency = 120,
733 .target_residency = 500,
734 .enter = &intel_idle,
735 .enter_freeze = intel_idle_freeze },
736 {
737 .enter = NULL }
738 };
739
740 /**
741 * intel_idle
742 * @dev: cpuidle_device
743 * @drv: cpuidle driver
744 * @index: index of cpuidle state
745 *
746 * Must be called under local_irq_disable().
747 */
intel_idle(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)748 static int intel_idle(struct cpuidle_device *dev,
749 struct cpuidle_driver *drv, int index)
750 {
751 unsigned long ecx = 1; /* break on interrupt flag */
752 struct cpuidle_state *state = &drv->states[index];
753 unsigned long eax = flg2MWAIT(state->flags);
754 unsigned int cstate;
755 int cpu = smp_processor_id();
756
757 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
758
759 /*
760 * leave_mm() to avoid costly and often unnecessary wakeups
761 * for flushing the user TLB's associated with the active mm.
762 */
763 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
764 leave_mm(cpu);
765
766 if (!(lapic_timer_reliable_states & (1 << (cstate))))
767 tick_broadcast_enter();
768
769 mwait_idle_with_hints(eax, ecx);
770
771 if (!(lapic_timer_reliable_states & (1 << (cstate))))
772 tick_broadcast_exit();
773
774 return index;
775 }
776
777 /**
778 * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle
779 * @dev: cpuidle_device
780 * @drv: cpuidle driver
781 * @index: state index
782 */
intel_idle_freeze(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)783 static void intel_idle_freeze(struct cpuidle_device *dev,
784 struct cpuidle_driver *drv, int index)
785 {
786 unsigned long ecx = 1; /* break on interrupt flag */
787 unsigned long eax = flg2MWAIT(drv->states[index].flags);
788
789 mwait_idle_with_hints(eax, ecx);
790 }
791
__setup_broadcast_timer(void * arg)792 static void __setup_broadcast_timer(void *arg)
793 {
794 unsigned long on = (unsigned long)arg;
795
796 if (on)
797 tick_broadcast_enable();
798 else
799 tick_broadcast_disable();
800 }
801
cpu_hotplug_notify(struct notifier_block * n,unsigned long action,void * hcpu)802 static int cpu_hotplug_notify(struct notifier_block *n,
803 unsigned long action, void *hcpu)
804 {
805 int hotcpu = (unsigned long)hcpu;
806 struct cpuidle_device *dev;
807
808 switch (action & ~CPU_TASKS_FROZEN) {
809 case CPU_ONLINE:
810
811 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
812 smp_call_function_single(hotcpu, __setup_broadcast_timer,
813 (void *)true, 1);
814
815 /*
816 * Some systems can hotplug a cpu at runtime after
817 * the kernel has booted, we have to initialize the
818 * driver in this case
819 */
820 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
821 if (!dev->registered)
822 intel_idle_cpu_init(hotcpu);
823
824 break;
825 }
826 return NOTIFY_OK;
827 }
828
829 static struct notifier_block cpu_hotplug_notifier = {
830 .notifier_call = cpu_hotplug_notify,
831 };
832
auto_demotion_disable(void * dummy)833 static void auto_demotion_disable(void *dummy)
834 {
835 unsigned long long msr_bits;
836
837 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
838 msr_bits &= ~(icpu->auto_demotion_disable_flags);
839 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
840 }
c1e_promotion_disable(void * dummy)841 static void c1e_promotion_disable(void *dummy)
842 {
843 unsigned long long msr_bits;
844
845 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
846 msr_bits &= ~0x2;
847 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
848 }
849
850 static const struct idle_cpu idle_cpu_nehalem = {
851 .state_table = nehalem_cstates,
852 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
853 .disable_promotion_to_c1e = true,
854 };
855
856 static const struct idle_cpu idle_cpu_atom = {
857 .state_table = atom_cstates,
858 };
859
860 static const struct idle_cpu idle_cpu_lincroft = {
861 .state_table = atom_cstates,
862 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
863 };
864
865 static const struct idle_cpu idle_cpu_snb = {
866 .state_table = snb_cstates,
867 .disable_promotion_to_c1e = true,
868 };
869
870 static const struct idle_cpu idle_cpu_byt = {
871 .state_table = byt_cstates,
872 .disable_promotion_to_c1e = true,
873 .byt_auto_demotion_disable_flag = true,
874 };
875
876 static const struct idle_cpu idle_cpu_cht = {
877 .state_table = cht_cstates,
878 .disable_promotion_to_c1e = true,
879 .byt_auto_demotion_disable_flag = true,
880 };
881
882 static const struct idle_cpu idle_cpu_ivb = {
883 .state_table = ivb_cstates,
884 .disable_promotion_to_c1e = true,
885 };
886
887 static const struct idle_cpu idle_cpu_ivt = {
888 .state_table = ivt_cstates,
889 .disable_promotion_to_c1e = true,
890 };
891
892 static const struct idle_cpu idle_cpu_hsw = {
893 .state_table = hsw_cstates,
894 .disable_promotion_to_c1e = true,
895 };
896
897 static const struct idle_cpu idle_cpu_bdw = {
898 .state_table = bdw_cstates,
899 .disable_promotion_to_c1e = true,
900 };
901
902 static const struct idle_cpu idle_cpu_skl = {
903 .state_table = skl_cstates,
904 .disable_promotion_to_c1e = true,
905 };
906
907
908 static const struct idle_cpu idle_cpu_avn = {
909 .state_table = avn_cstates,
910 .disable_promotion_to_c1e = true,
911 };
912
913 static const struct idle_cpu idle_cpu_knl = {
914 .state_table = knl_cstates,
915 };
916
917 #define ICPU(model, cpu) \
918 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
919
920 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
921 ICPU(0x1a, idle_cpu_nehalem),
922 ICPU(0x1e, idle_cpu_nehalem),
923 ICPU(0x1f, idle_cpu_nehalem),
924 ICPU(0x25, idle_cpu_nehalem),
925 ICPU(0x2c, idle_cpu_nehalem),
926 ICPU(0x2e, idle_cpu_nehalem),
927 ICPU(0x1c, idle_cpu_atom),
928 ICPU(0x26, idle_cpu_lincroft),
929 ICPU(0x2f, idle_cpu_nehalem),
930 ICPU(0x2a, idle_cpu_snb),
931 ICPU(0x2d, idle_cpu_snb),
932 ICPU(0x36, idle_cpu_atom),
933 ICPU(0x37, idle_cpu_byt),
934 ICPU(0x4c, idle_cpu_cht),
935 ICPU(0x3a, idle_cpu_ivb),
936 ICPU(0x3e, idle_cpu_ivt),
937 ICPU(0x3c, idle_cpu_hsw),
938 ICPU(0x3f, idle_cpu_hsw),
939 ICPU(0x45, idle_cpu_hsw),
940 ICPU(0x46, idle_cpu_hsw),
941 ICPU(0x4d, idle_cpu_avn),
942 ICPU(0x3d, idle_cpu_bdw),
943 ICPU(0x47, idle_cpu_bdw),
944 ICPU(0x4f, idle_cpu_bdw),
945 ICPU(0x56, idle_cpu_bdw),
946 ICPU(0x4e, idle_cpu_skl),
947 ICPU(0x5e, idle_cpu_skl),
948 ICPU(0x57, idle_cpu_knl),
949 {}
950 };
951 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
952
953 /*
954 * intel_idle_probe()
955 */
intel_idle_probe(void)956 static int __init intel_idle_probe(void)
957 {
958 unsigned int eax, ebx, ecx;
959 const struct x86_cpu_id *id;
960
961 if (max_cstate == 0) {
962 pr_debug(PREFIX "disabled\n");
963 return -EPERM;
964 }
965
966 id = x86_match_cpu(intel_idle_ids);
967 if (!id) {
968 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
969 boot_cpu_data.x86 == 6)
970 pr_debug(PREFIX "does not run on family %d model %d\n",
971 boot_cpu_data.x86, boot_cpu_data.x86_model);
972 return -ENODEV;
973 }
974
975 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
976 return -ENODEV;
977
978 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
979
980 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
981 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
982 !mwait_substates)
983 return -ENODEV;
984
985 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
986
987 icpu = (const struct idle_cpu *)id->driver_data;
988 cpuidle_state_table = icpu->state_table;
989
990 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
991 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
992 else
993 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
994
995 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
996 " model 0x%X\n", boot_cpu_data.x86_model);
997
998 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
999 lapic_timer_reliable_states);
1000 return 0;
1001 }
1002
1003 /*
1004 * intel_idle_cpuidle_devices_uninit()
1005 * unregister, free cpuidle_devices
1006 */
intel_idle_cpuidle_devices_uninit(void)1007 static void intel_idle_cpuidle_devices_uninit(void)
1008 {
1009 int i;
1010 struct cpuidle_device *dev;
1011
1012 for_each_online_cpu(i) {
1013 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
1014 cpuidle_unregister_device(dev);
1015 }
1016
1017 free_percpu(intel_idle_cpuidle_devices);
1018 return;
1019 }
1020
1021 /*
1022 * ivt_idle_state_table_update(void)
1023 *
1024 * Tune IVT multi-socket targets
1025 * Assumption: num_sockets == (max_package_num + 1)
1026 */
ivt_idle_state_table_update(void)1027 static void ivt_idle_state_table_update(void)
1028 {
1029 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1030 int cpu, package_num, num_sockets = 1;
1031
1032 for_each_online_cpu(cpu) {
1033 package_num = topology_physical_package_id(cpu);
1034 if (package_num + 1 > num_sockets) {
1035 num_sockets = package_num + 1;
1036
1037 if (num_sockets > 4) {
1038 cpuidle_state_table = ivt_cstates_8s;
1039 return;
1040 }
1041 }
1042 }
1043
1044 if (num_sockets > 2)
1045 cpuidle_state_table = ivt_cstates_4s;
1046
1047 /* else, 1 and 2 socket systems use default ivt_cstates */
1048 }
1049 /*
1050 * sklh_idle_state_table_update(void)
1051 *
1052 * On SKL-H (model 0x5e) disable C8 and C9 if:
1053 * C10 is enabled and SGX disabled
1054 */
sklh_idle_state_table_update(void)1055 static void sklh_idle_state_table_update(void)
1056 {
1057 unsigned long long msr;
1058 unsigned int eax, ebx, ecx, edx;
1059
1060
1061 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1062 if (max_cstate <= 7)
1063 return;
1064
1065 /* if PC10 not present in CPUID.MWAIT.EDX */
1066 if ((mwait_substates & (0xF << 28)) == 0)
1067 return;
1068
1069 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr);
1070
1071 /* PC10 is not enabled in PKG C-state limit */
1072 if ((msr & 0xF) != 8)
1073 return;
1074
1075 ecx = 0;
1076 cpuid(7, &eax, &ebx, &ecx, &edx);
1077
1078 /* if SGX is present */
1079 if (ebx & (1 << 2)) {
1080
1081 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1082
1083 /* if SGX is enabled */
1084 if (msr & (1 << 18))
1085 return;
1086 }
1087
1088 skl_cstates[5].disabled = 1; /* C8-SKL */
1089 skl_cstates[6].disabled = 1; /* C9-SKL */
1090 }
1091 /*
1092 * intel_idle_state_table_update()
1093 *
1094 * Update the default state_table for this CPU-id
1095 */
1096
intel_idle_state_table_update(void)1097 static void intel_idle_state_table_update(void)
1098 {
1099 switch (boot_cpu_data.x86_model) {
1100
1101 case 0x3e: /* IVT */
1102 ivt_idle_state_table_update();
1103 break;
1104 case 0x5e: /* SKL-H */
1105 sklh_idle_state_table_update();
1106 break;
1107 }
1108 }
1109
1110 /*
1111 * intel_idle_cpuidle_driver_init()
1112 * allocate, initialize cpuidle_states
1113 */
intel_idle_cpuidle_driver_init(void)1114 static int __init intel_idle_cpuidle_driver_init(void)
1115 {
1116 int cstate;
1117 struct cpuidle_driver *drv = &intel_idle_driver;
1118
1119 intel_idle_state_table_update();
1120
1121 drv->state_count = 1;
1122
1123 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1124 int num_substates, mwait_hint, mwait_cstate;
1125
1126 if ((cpuidle_state_table[cstate].enter == NULL) &&
1127 (cpuidle_state_table[cstate].enter_freeze == NULL))
1128 break;
1129
1130 if (cstate + 1 > max_cstate) {
1131 printk(PREFIX "max_cstate %d reached\n",
1132 max_cstate);
1133 break;
1134 }
1135
1136 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1137 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
1138
1139 /* number of sub-states for this state in CPUID.MWAIT */
1140 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
1141 & MWAIT_SUBSTATE_MASK;
1142
1143 /* if NO sub-states for this state in CPUID, skip it */
1144 if (num_substates == 0)
1145 continue;
1146
1147 /* if state marked as disabled, skip it */
1148 if (cpuidle_state_table[cstate].disabled != 0) {
1149 pr_debug(PREFIX "state %s is disabled",
1150 cpuidle_state_table[cstate].name);
1151 continue;
1152 }
1153
1154
1155 if (((mwait_cstate + 1) > 2) &&
1156 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1157 mark_tsc_unstable("TSC halts in idle"
1158 " states deeper than C2");
1159
1160 drv->states[drv->state_count] = /* structure copy */
1161 cpuidle_state_table[cstate];
1162
1163 drv->state_count += 1;
1164 }
1165
1166 if (icpu->auto_demotion_disable_flags)
1167 on_each_cpu(auto_demotion_disable, NULL, 1);
1168
1169 if (icpu->byt_auto_demotion_disable_flag) {
1170 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1171 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1172 }
1173
1174 if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */
1175 on_each_cpu(c1e_promotion_disable, NULL, 1);
1176
1177 return 0;
1178 }
1179
1180
1181 /*
1182 * intel_idle_cpu_init()
1183 * allocate, initialize, register cpuidle_devices
1184 * @cpu: cpu/core to initialize
1185 */
intel_idle_cpu_init(int cpu)1186 static int intel_idle_cpu_init(int cpu)
1187 {
1188 struct cpuidle_device *dev;
1189
1190 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1191
1192 dev->cpu = cpu;
1193
1194 if (cpuidle_register_device(dev)) {
1195 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
1196 intel_idle_cpuidle_devices_uninit();
1197 return -EIO;
1198 }
1199
1200 if (icpu->auto_demotion_disable_flags)
1201 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
1202
1203 if (icpu->disable_promotion_to_c1e)
1204 smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
1205
1206 return 0;
1207 }
1208
intel_idle_init(void)1209 static int __init intel_idle_init(void)
1210 {
1211 int retval, i;
1212
1213 /* Do not load intel_idle at all for now if idle= is passed */
1214 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1215 return -ENODEV;
1216
1217 retval = intel_idle_probe();
1218 if (retval)
1219 return retval;
1220
1221 intel_idle_cpuidle_driver_init();
1222 retval = cpuidle_register_driver(&intel_idle_driver);
1223 if (retval) {
1224 struct cpuidle_driver *drv = cpuidle_get_driver();
1225 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
1226 drv ? drv->name : "none");
1227 return retval;
1228 }
1229
1230 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1231 if (intel_idle_cpuidle_devices == NULL)
1232 return -ENOMEM;
1233
1234 cpu_notifier_register_begin();
1235
1236 for_each_online_cpu(i) {
1237 retval = intel_idle_cpu_init(i);
1238 if (retval) {
1239 cpu_notifier_register_done();
1240 cpuidle_unregister_driver(&intel_idle_driver);
1241 return retval;
1242 }
1243 }
1244 __register_cpu_notifier(&cpu_hotplug_notifier);
1245
1246 cpu_notifier_register_done();
1247
1248 return 0;
1249 }
1250
intel_idle_exit(void)1251 static void __exit intel_idle_exit(void)
1252 {
1253 intel_idle_cpuidle_devices_uninit();
1254 cpuidle_unregister_driver(&intel_idle_driver);
1255
1256 cpu_notifier_register_begin();
1257
1258 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
1259 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
1260 __unregister_cpu_notifier(&cpu_hotplug_notifier);
1261
1262 cpu_notifier_register_done();
1263
1264 return;
1265 }
1266
1267 module_init(intel_idle_init);
1268 module_exit(intel_idle_exit);
1269
1270 module_param(max_cstate, int, 0444);
1271
1272 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
1273 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
1274 MODULE_LICENSE("GPL");
1275