1 /*
2 * Driver for the ADC present in the Atmel AT91 evaluation boards.
3 *
4 * Copyright 2011 Free Electrons
5 *
6 * Licensed under the GPLv2 or later.
7 */
8
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
25
26 #include <linux/platform_data/at91_adc.h>
27
28 #include <linux/iio/iio.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
33
34 /* Registers */
35 #define AT91_ADC_CR 0x00 /* Control Register */
36 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
37 #define AT91_ADC_START (1 << 1) /* Start Conversion */
38
39 #define AT91_ADC_MR 0x04 /* Mode Register */
40 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
41 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
42 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
43 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
44 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
45 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
46 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
47 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
48 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
49 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
50 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
51 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
52 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
53 #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
54 #define AT91_ADC_PRESCAL_(x) ((x) << 8)
55 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
56 #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
57 #define AT91_ADC_STARTUP_9X5 (0xf << 16)
58 #define AT91_ADC_STARTUP_(x) ((x) << 16)
59 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
60 #define AT91_ADC_SHTIM_(x) ((x) << 24)
61 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
62 #define AT91_ADC_PENDBC_(x) ((x) << 28)
63
64 #define AT91_ADC_TSR 0x0C
65 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
66 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
67
68 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
69 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
70 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
71 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
72
73 #define AT91_ADC_SR 0x1C /* Status Register */
74 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
75 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
76 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
77 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
78 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
79 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
80
81 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
82 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
83
84 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
85 #define AT91_ADC_LDATA (0x3ff)
86
87 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
88 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
89 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
90 #define AT91RL_ADC_IER_PEN (1 << 20)
91 #define AT91RL_ADC_IER_NOPEN (1 << 21)
92 #define AT91_ADC_IER_PEN (1 << 29)
93 #define AT91_ADC_IER_NOPEN (1 << 30)
94 #define AT91_ADC_IER_XRDY (1 << 20)
95 #define AT91_ADC_IER_YRDY (1 << 21)
96 #define AT91_ADC_IER_PRDY (1 << 22)
97 #define AT91_ADC_ISR_PENS (1 << 31)
98
99 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
100 #define AT91_ADC_DATA (0x3ff)
101
102 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
103
104 #define AT91_ADC_ACR 0x94 /* Analog Control Register */
105 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
106
107 #define AT91_ADC_TSMR 0xB0
108 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
109 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
110 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
111 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
112 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
113 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
114 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
115 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
116 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
117 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
118 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
119 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
120 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
121
122 #define AT91_ADC_TSXPOSR 0xB4
123 #define AT91_ADC_TSYPOSR 0xB8
124 #define AT91_ADC_TSPRESSR 0xBC
125
126 #define AT91_ADC_TRGR_9260 AT91_ADC_MR
127 #define AT91_ADC_TRGR_9G45 0x08
128 #define AT91_ADC_TRGR_9X5 0xC0
129
130 /* Trigger Register bit field */
131 #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
132 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
133 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
134 #define AT91_ADC_TRGR_NONE (0 << 0)
135 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
136
137 #define AT91_ADC_CHAN(st, ch) \
138 (st->registers->channel_base + (ch * 4))
139 #define at91_adc_readl(st, reg) \
140 (readl_relaxed(st->reg_base + reg))
141 #define at91_adc_writel(st, reg, val) \
142 (writel_relaxed(val, st->reg_base + reg))
143
144 #define DRIVER_NAME "at91_adc"
145 #define MAX_POS_BITS 12
146
147 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
148 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
149
150 #define MAX_RLPOS_BITS 10
151 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
152 #define TOUCH_SHTIM 0xa
153
154 /**
155 * struct at91_adc_reg_desc - Various informations relative to registers
156 * @channel_base: Base offset for the channel data registers
157 * @drdy_mask: Mask of the DRDY field in the relevant registers
158 (Interruptions registers mostly)
159 * @status_register: Offset of the Interrupt Status Register
160 * @trigger_register: Offset of the Trigger setup register
161 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
162 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
163 */
164 struct at91_adc_reg_desc {
165 u8 channel_base;
166 u32 drdy_mask;
167 u8 status_register;
168 u8 trigger_register;
169 u32 mr_prescal_mask;
170 u32 mr_startup_mask;
171 };
172
173 struct at91_adc_caps {
174 bool has_ts; /* Support touch screen */
175 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
176 /*
177 * Numbers of sampling data will be averaged. Can be 0~3.
178 * Hardware can average (2 ^ ts_filter_average) sample data.
179 */
180 u8 ts_filter_average;
181 /* Pen Detection input pull-up resistor, can be 0~3 */
182 u8 ts_pen_detect_sensitivity;
183
184 /* startup time calculate function */
185 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
186
187 u8 num_channels;
188 struct at91_adc_reg_desc registers;
189 };
190
191 struct at91_adc_state {
192 struct clk *adc_clk;
193 u16 *buffer;
194 unsigned long channels_mask;
195 struct clk *clk;
196 bool done;
197 int irq;
198 u16 last_value;
199 int chnb;
200 struct mutex lock;
201 u8 num_channels;
202 void __iomem *reg_base;
203 struct at91_adc_reg_desc *registers;
204 u32 startup_time;
205 u8 sample_hold_time;
206 bool sleep_mode;
207 struct iio_trigger **trig;
208 struct at91_adc_trigger *trigger_list;
209 u32 trigger_number;
210 bool use_external;
211 u32 vref_mv;
212 u32 res; /* resolution used for convertions */
213 bool low_res; /* the resolution corresponds to the lowest one */
214 wait_queue_head_t wq_data_avail;
215 struct at91_adc_caps *caps;
216
217 /*
218 * Following ADC channels are shared by touchscreen:
219 *
220 * CH0 -- Touch screen XP/UL
221 * CH1 -- Touch screen XM/UR
222 * CH2 -- Touch screen YP/LL
223 * CH3 -- Touch screen YM/Sense
224 * CH4 -- Touch screen LR(5-wire only)
225 *
226 * The bitfields below represents the reserved channel in the
227 * touchscreen mode.
228 */
229 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
230 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
231 enum atmel_adc_ts_type touchscreen_type;
232 struct input_dev *ts_input;
233
234 u16 ts_sample_period_val;
235 u32 ts_pressure_threshold;
236 u16 ts_pendbc;
237
238 bool ts_bufferedmeasure;
239 u32 ts_prev_absx;
240 u32 ts_prev_absy;
241 };
242
at91_adc_trigger_handler(int irq,void * p)243 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
244 {
245 struct iio_poll_func *pf = p;
246 struct iio_dev *idev = pf->indio_dev;
247 struct at91_adc_state *st = iio_priv(idev);
248 struct iio_chan_spec const *chan;
249 int i, j = 0;
250
251 for (i = 0; i < idev->masklength; i++) {
252 if (!test_bit(i, idev->active_scan_mask))
253 continue;
254 chan = idev->channels + i;
255 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
256 j++;
257 }
258
259 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
260
261 iio_trigger_notify_done(idev->trig);
262
263 /* Needed to ACK the DRDY interruption */
264 at91_adc_readl(st, AT91_ADC_LCDR);
265
266 enable_irq(st->irq);
267
268 return IRQ_HANDLED;
269 }
270
271 /* Handler for classic adc channel eoc trigger */
handle_adc_eoc_trigger(int irq,struct iio_dev * idev)272 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
273 {
274 struct at91_adc_state *st = iio_priv(idev);
275
276 if (iio_buffer_enabled(idev)) {
277 disable_irq_nosync(irq);
278 iio_trigger_poll(idev->trig);
279 } else {
280 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
281 /* Needed to ACK the DRDY interruption */
282 at91_adc_readl(st, AT91_ADC_LCDR);
283 st->done = true;
284 wake_up_interruptible(&st->wq_data_avail);
285 }
286 }
287
at91_ts_sample(struct at91_adc_state * st)288 static int at91_ts_sample(struct at91_adc_state *st)
289 {
290 unsigned int xscale, yscale, reg, z1, z2;
291 unsigned int x, y, pres, xpos, ypos;
292 unsigned int rxp = 1;
293 unsigned int factor = 1000;
294 struct iio_dev *idev = iio_priv_to_dev(st);
295
296 unsigned int xyz_mask_bits = st->res;
297 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
298
299 /* calculate position */
300 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
301 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
302 xpos = reg & xyz_mask;
303 x = (xpos << MAX_POS_BITS) - xpos;
304 xscale = (reg >> 16) & xyz_mask;
305 if (xscale == 0) {
306 dev_err(&idev->dev, "Error: xscale == 0!\n");
307 return -1;
308 }
309 x /= xscale;
310
311 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
312 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
313 ypos = reg & xyz_mask;
314 y = (ypos << MAX_POS_BITS) - ypos;
315 yscale = (reg >> 16) & xyz_mask;
316 if (yscale == 0) {
317 dev_err(&idev->dev, "Error: yscale == 0!\n");
318 return -1;
319 }
320 y /= yscale;
321
322 /* calculate the pressure */
323 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
324 z1 = reg & xyz_mask;
325 z2 = (reg >> 16) & xyz_mask;
326
327 if (z1 != 0)
328 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
329 / factor;
330 else
331 pres = st->ts_pressure_threshold; /* no pen contacted */
332
333 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
334 xpos, xscale, ypos, yscale, z1, z2, pres);
335
336 if (pres < st->ts_pressure_threshold) {
337 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
338 x, y, pres / factor);
339 input_report_abs(st->ts_input, ABS_X, x);
340 input_report_abs(st->ts_input, ABS_Y, y);
341 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
342 input_report_key(st->ts_input, BTN_TOUCH, 1);
343 input_sync(st->ts_input);
344 } else {
345 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
346 }
347
348 return 0;
349 }
350
at91_adc_rl_interrupt(int irq,void * private)351 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
352 {
353 struct iio_dev *idev = private;
354 struct at91_adc_state *st = iio_priv(idev);
355 u32 status = at91_adc_readl(st, st->registers->status_register);
356 unsigned int reg;
357
358 status &= at91_adc_readl(st, AT91_ADC_IMR);
359 if (status & GENMASK(st->num_channels - 1, 0))
360 handle_adc_eoc_trigger(irq, idev);
361
362 if (status & AT91RL_ADC_IER_PEN) {
363 /* Disabling pen debounce is required to get a NOPEN irq */
364 reg = at91_adc_readl(st, AT91_ADC_MR);
365 reg &= ~AT91_ADC_PENDBC;
366 at91_adc_writel(st, AT91_ADC_MR, reg);
367
368 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
369 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
370 | AT91_ADC_EOC(3));
371 /* Set up period trigger for sampling */
372 at91_adc_writel(st, st->registers->trigger_register,
373 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
374 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
375 } else if (status & AT91RL_ADC_IER_NOPEN) {
376 reg = at91_adc_readl(st, AT91_ADC_MR);
377 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
378 at91_adc_writel(st, AT91_ADC_MR, reg);
379 at91_adc_writel(st, st->registers->trigger_register,
380 AT91_ADC_TRGR_NONE);
381
382 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
383 | AT91_ADC_EOC(3));
384 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
385 st->ts_bufferedmeasure = false;
386 input_report_key(st->ts_input, BTN_TOUCH, 0);
387 input_sync(st->ts_input);
388 } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
389 /* Conversion finished and we've a touchscreen */
390 if (st->ts_bufferedmeasure) {
391 /*
392 * Last measurement is always discarded, since it can
393 * be erroneous.
394 * Always report previous measurement
395 */
396 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
397 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
398 input_report_key(st->ts_input, BTN_TOUCH, 1);
399 input_sync(st->ts_input);
400 } else
401 st->ts_bufferedmeasure = true;
402
403 /* Now make new measurement */
404 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
405 << MAX_RLPOS_BITS;
406 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
407
408 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
409 << MAX_RLPOS_BITS;
410 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
411 }
412
413 return IRQ_HANDLED;
414 }
415
at91_adc_9x5_interrupt(int irq,void * private)416 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
417 {
418 struct iio_dev *idev = private;
419 struct at91_adc_state *st = iio_priv(idev);
420 u32 status = at91_adc_readl(st, st->registers->status_register);
421 const uint32_t ts_data_irq_mask =
422 AT91_ADC_IER_XRDY |
423 AT91_ADC_IER_YRDY |
424 AT91_ADC_IER_PRDY;
425
426 if (status & GENMASK(st->num_channels - 1, 0))
427 handle_adc_eoc_trigger(irq, idev);
428
429 if (status & AT91_ADC_IER_PEN) {
430 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
431 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
432 ts_data_irq_mask);
433 /* Set up period trigger for sampling */
434 at91_adc_writel(st, st->registers->trigger_register,
435 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
436 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
437 } else if (status & AT91_ADC_IER_NOPEN) {
438 at91_adc_writel(st, st->registers->trigger_register, 0);
439 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
440 ts_data_irq_mask);
441 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
442
443 input_report_key(st->ts_input, BTN_TOUCH, 0);
444 input_sync(st->ts_input);
445 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
446 /* Now all touchscreen data is ready */
447
448 if (status & AT91_ADC_ISR_PENS) {
449 /* validate data by pen contact */
450 at91_ts_sample(st);
451 } else {
452 /* triggered by event that is no pen contact, just read
453 * them to clean the interrupt and discard all.
454 */
455 at91_adc_readl(st, AT91_ADC_TSXPOSR);
456 at91_adc_readl(st, AT91_ADC_TSYPOSR);
457 at91_adc_readl(st, AT91_ADC_TSPRESSR);
458 }
459 }
460
461 return IRQ_HANDLED;
462 }
463
at91_adc_channel_init(struct iio_dev * idev)464 static int at91_adc_channel_init(struct iio_dev *idev)
465 {
466 struct at91_adc_state *st = iio_priv(idev);
467 struct iio_chan_spec *chan_array, *timestamp;
468 int bit, idx = 0;
469 unsigned long rsvd_mask = 0;
470
471 /* If touchscreen is enable, then reserve the adc channels */
472 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
473 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
474 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
475 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
476
477 /* set up the channel mask to reserve touchscreen channels */
478 st->channels_mask &= ~rsvd_mask;
479
480 idev->num_channels = bitmap_weight(&st->channels_mask,
481 st->num_channels) + 1;
482
483 chan_array = devm_kzalloc(&idev->dev,
484 ((idev->num_channels + 1) *
485 sizeof(struct iio_chan_spec)),
486 GFP_KERNEL);
487
488 if (!chan_array)
489 return -ENOMEM;
490
491 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
492 struct iio_chan_spec *chan = chan_array + idx;
493
494 chan->type = IIO_VOLTAGE;
495 chan->indexed = 1;
496 chan->channel = bit;
497 chan->scan_index = idx;
498 chan->scan_type.sign = 'u';
499 chan->scan_type.realbits = st->res;
500 chan->scan_type.storagebits = 16;
501 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
502 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
503 idx++;
504 }
505 timestamp = chan_array + idx;
506
507 timestamp->type = IIO_TIMESTAMP;
508 timestamp->channel = -1;
509 timestamp->scan_index = idx;
510 timestamp->scan_type.sign = 's';
511 timestamp->scan_type.realbits = 64;
512 timestamp->scan_type.storagebits = 64;
513
514 idev->channels = chan_array;
515 return idev->num_channels;
516 }
517
at91_adc_get_trigger_value_by_name(struct iio_dev * idev,struct at91_adc_trigger * triggers,const char * trigger_name)518 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
519 struct at91_adc_trigger *triggers,
520 const char *trigger_name)
521 {
522 struct at91_adc_state *st = iio_priv(idev);
523 int i;
524
525 for (i = 0; i < st->trigger_number; i++) {
526 char *name = kasprintf(GFP_KERNEL,
527 "%s-dev%d-%s",
528 idev->name,
529 idev->id,
530 triggers[i].name);
531 if (!name)
532 return -ENOMEM;
533
534 if (strcmp(trigger_name, name) == 0) {
535 kfree(name);
536 if (triggers[i].value == 0)
537 return -EINVAL;
538 return triggers[i].value;
539 }
540
541 kfree(name);
542 }
543
544 return -EINVAL;
545 }
546
at91_adc_configure_trigger(struct iio_trigger * trig,bool state)547 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
548 {
549 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
550 struct at91_adc_state *st = iio_priv(idev);
551 struct at91_adc_reg_desc *reg = st->registers;
552 u32 status = at91_adc_readl(st, reg->trigger_register);
553 int value;
554 u8 bit;
555
556 value = at91_adc_get_trigger_value_by_name(idev,
557 st->trigger_list,
558 idev->trig->name);
559 if (value < 0)
560 return value;
561
562 if (state) {
563 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
564 if (st->buffer == NULL)
565 return -ENOMEM;
566
567 at91_adc_writel(st, reg->trigger_register,
568 status | value);
569
570 for_each_set_bit(bit, idev->active_scan_mask,
571 st->num_channels) {
572 struct iio_chan_spec const *chan = idev->channels + bit;
573 at91_adc_writel(st, AT91_ADC_CHER,
574 AT91_ADC_CH(chan->channel));
575 }
576
577 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
578
579 } else {
580 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
581
582 at91_adc_writel(st, reg->trigger_register,
583 status & ~value);
584
585 for_each_set_bit(bit, idev->active_scan_mask,
586 st->num_channels) {
587 struct iio_chan_spec const *chan = idev->channels + bit;
588 at91_adc_writel(st, AT91_ADC_CHDR,
589 AT91_ADC_CH(chan->channel));
590 }
591 kfree(st->buffer);
592 }
593
594 return 0;
595 }
596
597 static const struct iio_trigger_ops at91_adc_trigger_ops = {
598 .owner = THIS_MODULE,
599 .set_trigger_state = &at91_adc_configure_trigger,
600 };
601
at91_adc_allocate_trigger(struct iio_dev * idev,struct at91_adc_trigger * trigger)602 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
603 struct at91_adc_trigger *trigger)
604 {
605 struct iio_trigger *trig;
606 int ret;
607
608 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
609 idev->id, trigger->name);
610 if (trig == NULL)
611 return NULL;
612
613 trig->dev.parent = idev->dev.parent;
614 iio_trigger_set_drvdata(trig, idev);
615 trig->ops = &at91_adc_trigger_ops;
616
617 ret = iio_trigger_register(trig);
618 if (ret)
619 return NULL;
620
621 return trig;
622 }
623
at91_adc_trigger_init(struct iio_dev * idev)624 static int at91_adc_trigger_init(struct iio_dev *idev)
625 {
626 struct at91_adc_state *st = iio_priv(idev);
627 int i, ret;
628
629 st->trig = devm_kzalloc(&idev->dev,
630 st->trigger_number * sizeof(*st->trig),
631 GFP_KERNEL);
632
633 if (st->trig == NULL) {
634 ret = -ENOMEM;
635 goto error_ret;
636 }
637
638 for (i = 0; i < st->trigger_number; i++) {
639 if (st->trigger_list[i].is_external && !(st->use_external))
640 continue;
641
642 st->trig[i] = at91_adc_allocate_trigger(idev,
643 st->trigger_list + i);
644 if (st->trig[i] == NULL) {
645 dev_err(&idev->dev,
646 "Could not allocate trigger %d\n", i);
647 ret = -ENOMEM;
648 goto error_trigger;
649 }
650 }
651
652 return 0;
653
654 error_trigger:
655 for (i--; i >= 0; i--) {
656 iio_trigger_unregister(st->trig[i]);
657 iio_trigger_free(st->trig[i]);
658 }
659 error_ret:
660 return ret;
661 }
662
at91_adc_trigger_remove(struct iio_dev * idev)663 static void at91_adc_trigger_remove(struct iio_dev *idev)
664 {
665 struct at91_adc_state *st = iio_priv(idev);
666 int i;
667
668 for (i = 0; i < st->trigger_number; i++) {
669 iio_trigger_unregister(st->trig[i]);
670 iio_trigger_free(st->trig[i]);
671 }
672 }
673
at91_adc_buffer_init(struct iio_dev * idev)674 static int at91_adc_buffer_init(struct iio_dev *idev)
675 {
676 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
677 &at91_adc_trigger_handler, NULL);
678 }
679
at91_adc_buffer_remove(struct iio_dev * idev)680 static void at91_adc_buffer_remove(struct iio_dev *idev)
681 {
682 iio_triggered_buffer_cleanup(idev);
683 }
684
at91_adc_read_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)685 static int at91_adc_read_raw(struct iio_dev *idev,
686 struct iio_chan_spec const *chan,
687 int *val, int *val2, long mask)
688 {
689 struct at91_adc_state *st = iio_priv(idev);
690 int ret;
691
692 switch (mask) {
693 case IIO_CHAN_INFO_RAW:
694 mutex_lock(&st->lock);
695
696 st->chnb = chan->channel;
697 at91_adc_writel(st, AT91_ADC_CHER,
698 AT91_ADC_CH(chan->channel));
699 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
700 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
701
702 ret = wait_event_interruptible_timeout(st->wq_data_avail,
703 st->done,
704 msecs_to_jiffies(1000));
705
706 /* Disable interrupts, regardless if adc conversion was
707 * successful or not
708 */
709 at91_adc_writel(st, AT91_ADC_CHDR,
710 AT91_ADC_CH(chan->channel));
711 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
712
713 if (ret > 0) {
714 /* a valid conversion took place */
715 *val = st->last_value;
716 st->last_value = 0;
717 st->done = false;
718 ret = IIO_VAL_INT;
719 } else if (ret == 0) {
720 /* conversion timeout */
721 dev_err(&idev->dev, "ADC Channel %d timeout.\n",
722 chan->channel);
723 ret = -ETIMEDOUT;
724 }
725
726 mutex_unlock(&st->lock);
727 return ret;
728
729 case IIO_CHAN_INFO_SCALE:
730 *val = st->vref_mv;
731 *val2 = chan->scan_type.realbits;
732 return IIO_VAL_FRACTIONAL_LOG2;
733 default:
734 break;
735 }
736 return -EINVAL;
737 }
738
at91_adc_of_get_resolution(struct at91_adc_state * st,struct platform_device * pdev)739 static int at91_adc_of_get_resolution(struct at91_adc_state *st,
740 struct platform_device *pdev)
741 {
742 struct iio_dev *idev = iio_priv_to_dev(st);
743 struct device_node *np = pdev->dev.of_node;
744 int count, i, ret = 0;
745 char *res_name, *s;
746 u32 *resolutions;
747
748 count = of_property_count_strings(np, "atmel,adc-res-names");
749 if (count < 2) {
750 dev_err(&idev->dev, "You must specified at least two resolution names for "
751 "adc-res-names property in the DT\n");
752 return count;
753 }
754
755 resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL);
756 if (!resolutions)
757 return -ENOMEM;
758
759 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
760 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
761 ret = -ENODEV;
762 goto ret;
763 }
764
765 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
766 res_name = "highres";
767
768 for (i = 0; i < count; i++) {
769 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
770 continue;
771
772 if (strcmp(res_name, s))
773 continue;
774
775 st->res = resolutions[i];
776 if (!strcmp(res_name, "lowres"))
777 st->low_res = true;
778 else
779 st->low_res = false;
780
781 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
782 goto ret;
783 }
784
785 dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
786
787 ret:
788 kfree(resolutions);
789 return ret;
790 }
791
calc_startup_ticks_9260(u32 startup_time,u32 adc_clk_khz)792 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
793 {
794 /*
795 * Number of ticks needed to cover the startup time of the ADC
796 * as defined in the electrical characteristics of the board,
797 * divided by 8. The formula thus is :
798 * Startup Time = (ticks + 1) * 8 / ADC Clock
799 */
800 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
801 }
802
calc_startup_ticks_9x5(u32 startup_time,u32 adc_clk_khz)803 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
804 {
805 /*
806 * For sama5d3x and at91sam9x5, the formula changes to:
807 * Startup Time = <lookup_table_value> / ADC Clock
808 */
809 const int startup_lookup[] = {
810 0 , 8 , 16 , 24 ,
811 64 , 80 , 96 , 112,
812 512, 576, 640, 704,
813 768, 832, 896, 960
814 };
815 int i, size = ARRAY_SIZE(startup_lookup);
816 unsigned int ticks;
817
818 ticks = startup_time * adc_clk_khz / 1000;
819 for (i = 0; i < size; i++)
820 if (ticks < startup_lookup[i])
821 break;
822
823 ticks = i;
824 if (ticks == size)
825 /* Reach the end of lookup table */
826 ticks = size - 1;
827
828 return ticks;
829 }
830
831 static const struct of_device_id at91_adc_dt_ids[];
832
at91_adc_probe_dt_ts(struct device_node * node,struct at91_adc_state * st,struct device * dev)833 static int at91_adc_probe_dt_ts(struct device_node *node,
834 struct at91_adc_state *st, struct device *dev)
835 {
836 int ret;
837 u32 prop;
838
839 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
840 if (ret) {
841 dev_info(dev, "ADC Touch screen is disabled.\n");
842 return 0;
843 }
844
845 switch (prop) {
846 case 4:
847 case 5:
848 st->touchscreen_type = prop;
849 break;
850 default:
851 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
852 return -EINVAL;
853 }
854
855 if (!st->caps->has_tsmr)
856 return 0;
857 prop = 0;
858 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
859 st->ts_pressure_threshold = prop;
860 if (st->ts_pressure_threshold) {
861 return 0;
862 } else {
863 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
864 return -EINVAL;
865 }
866 }
867
at91_adc_probe_dt(struct at91_adc_state * st,struct platform_device * pdev)868 static int at91_adc_probe_dt(struct at91_adc_state *st,
869 struct platform_device *pdev)
870 {
871 struct iio_dev *idev = iio_priv_to_dev(st);
872 struct device_node *node = pdev->dev.of_node;
873 struct device_node *trig_node;
874 int i = 0, ret;
875 u32 prop;
876
877 if (!node)
878 return -EINVAL;
879
880 st->caps = (struct at91_adc_caps *)
881 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
882
883 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
884
885 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
886 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
887 ret = -EINVAL;
888 goto error_ret;
889 }
890 st->channels_mask = prop;
891
892 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
893
894 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
895 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
896 ret = -EINVAL;
897 goto error_ret;
898 }
899 st->startup_time = prop;
900
901 prop = 0;
902 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
903 st->sample_hold_time = prop;
904
905 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
906 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
907 ret = -EINVAL;
908 goto error_ret;
909 }
910 st->vref_mv = prop;
911
912 ret = at91_adc_of_get_resolution(st, pdev);
913 if (ret)
914 goto error_ret;
915
916 st->registers = &st->caps->registers;
917 st->num_channels = st->caps->num_channels;
918 st->trigger_number = of_get_child_count(node);
919 st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
920 sizeof(struct at91_adc_trigger),
921 GFP_KERNEL);
922 if (!st->trigger_list) {
923 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
924 ret = -ENOMEM;
925 goto error_ret;
926 }
927
928 for_each_child_of_node(node, trig_node) {
929 struct at91_adc_trigger *trig = st->trigger_list + i;
930 const char *name;
931
932 if (of_property_read_string(trig_node, "trigger-name", &name)) {
933 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
934 ret = -EINVAL;
935 goto error_ret;
936 }
937 trig->name = name;
938
939 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
940 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
941 ret = -EINVAL;
942 goto error_ret;
943 }
944 trig->value = prop;
945 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
946 i++;
947 }
948
949 /* Check if touchscreen is supported. */
950 if (st->caps->has_ts)
951 return at91_adc_probe_dt_ts(node, st, &idev->dev);
952 else
953 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
954
955 return 0;
956
957 error_ret:
958 return ret;
959 }
960
at91_adc_probe_pdata(struct at91_adc_state * st,struct platform_device * pdev)961 static int at91_adc_probe_pdata(struct at91_adc_state *st,
962 struct platform_device *pdev)
963 {
964 struct at91_adc_data *pdata = pdev->dev.platform_data;
965
966 if (!pdata)
967 return -EINVAL;
968
969 st->caps = (struct at91_adc_caps *)
970 platform_get_device_id(pdev)->driver_data;
971
972 st->use_external = pdata->use_external_triggers;
973 st->vref_mv = pdata->vref;
974 st->channels_mask = pdata->channels_used;
975 st->num_channels = st->caps->num_channels;
976 st->startup_time = pdata->startup_time;
977 st->trigger_number = pdata->trigger_number;
978 st->trigger_list = pdata->trigger_list;
979 st->registers = &st->caps->registers;
980 st->touchscreen_type = pdata->touchscreen_type;
981
982 return 0;
983 }
984
985 static const struct iio_info at91_adc_info = {
986 .driver_module = THIS_MODULE,
987 .read_raw = &at91_adc_read_raw,
988 };
989
990 /* Touchscreen related functions */
atmel_ts_open(struct input_dev * dev)991 static int atmel_ts_open(struct input_dev *dev)
992 {
993 struct at91_adc_state *st = input_get_drvdata(dev);
994
995 if (st->caps->has_tsmr)
996 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
997 else
998 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
999 return 0;
1000 }
1001
atmel_ts_close(struct input_dev * dev)1002 static void atmel_ts_close(struct input_dev *dev)
1003 {
1004 struct at91_adc_state *st = input_get_drvdata(dev);
1005
1006 if (st->caps->has_tsmr)
1007 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
1008 else
1009 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1010 }
1011
at91_ts_hw_init(struct at91_adc_state * st,u32 adc_clk_khz)1012 static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1013 {
1014 u32 reg = 0;
1015 int i = 0;
1016
1017 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1018 * pen detect noise.
1019 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1020 */
1021 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1022 1000, 1);
1023
1024 while (st->ts_pendbc >> ++i)
1025 ; /* Empty! Find the shift offset */
1026 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1027 st->ts_pendbc = i;
1028 else
1029 st->ts_pendbc = i - 1;
1030
1031 if (!st->caps->has_tsmr) {
1032 reg = at91_adc_readl(st, AT91_ADC_MR);
1033 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1034
1035 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1036 at91_adc_writel(st, AT91_ADC_MR, reg);
1037
1038 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1039 at91_adc_writel(st, AT91_ADC_TSR, reg);
1040
1041 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1042 adc_clk_khz / 1000) - 1, 1);
1043
1044 return 0;
1045 }
1046
1047 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1048 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1049 else
1050 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1051
1052 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1053 & AT91_ADC_TSMR_TSAV;
1054 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1055 reg |= AT91_ADC_TSMR_NOTSDMA;
1056 reg |= AT91_ADC_TSMR_PENDET_ENA;
1057 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
1058
1059 at91_adc_writel(st, AT91_ADC_TSMR, reg);
1060
1061 /* Change adc internal resistor value for better pen detection,
1062 * default value is 100 kOhm.
1063 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1064 * option only available on ES2 and higher
1065 */
1066 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1067 & AT91_ADC_ACR_PENDETSENS);
1068
1069 /* Sample Period Time = (TRGPER + 1) / ADCClock */
1070 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1071 adc_clk_khz / 1000) - 1, 1);
1072
1073 return 0;
1074 }
1075
at91_ts_register(struct at91_adc_state * st,struct platform_device * pdev)1076 static int at91_ts_register(struct at91_adc_state *st,
1077 struct platform_device *pdev)
1078 {
1079 struct input_dev *input;
1080 struct iio_dev *idev = iio_priv_to_dev(st);
1081 int ret;
1082
1083 input = input_allocate_device();
1084 if (!input) {
1085 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1086 return -ENOMEM;
1087 }
1088
1089 input->name = DRIVER_NAME;
1090 input->id.bustype = BUS_HOST;
1091 input->dev.parent = &pdev->dev;
1092 input->open = atmel_ts_open;
1093 input->close = atmel_ts_close;
1094
1095 __set_bit(EV_ABS, input->evbit);
1096 __set_bit(EV_KEY, input->evbit);
1097 __set_bit(BTN_TOUCH, input->keybit);
1098 if (st->caps->has_tsmr) {
1099 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1100 0, 0);
1101 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1102 0, 0);
1103 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1104 } else {
1105 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1106 dev_err(&pdev->dev,
1107 "This touchscreen controller only support 4 wires\n");
1108 ret = -EINVAL;
1109 goto err;
1110 }
1111
1112 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1113 0, 0);
1114 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1115 0, 0);
1116 }
1117
1118 st->ts_input = input;
1119 input_set_drvdata(input, st);
1120
1121 ret = input_register_device(input);
1122 if (ret)
1123 goto err;
1124
1125 return ret;
1126
1127 err:
1128 input_free_device(st->ts_input);
1129 return ret;
1130 }
1131
at91_ts_unregister(struct at91_adc_state * st)1132 static void at91_ts_unregister(struct at91_adc_state *st)
1133 {
1134 input_unregister_device(st->ts_input);
1135 }
1136
at91_adc_probe(struct platform_device * pdev)1137 static int at91_adc_probe(struct platform_device *pdev)
1138 {
1139 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1140 int ret;
1141 struct iio_dev *idev;
1142 struct at91_adc_state *st;
1143 struct resource *res;
1144 u32 reg;
1145
1146 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1147 if (!idev)
1148 return -ENOMEM;
1149
1150 st = iio_priv(idev);
1151
1152 if (pdev->dev.of_node)
1153 ret = at91_adc_probe_dt(st, pdev);
1154 else
1155 ret = at91_adc_probe_pdata(st, pdev);
1156
1157 if (ret) {
1158 dev_err(&pdev->dev, "No platform data available.\n");
1159 return -EINVAL;
1160 }
1161
1162 platform_set_drvdata(pdev, idev);
1163
1164 idev->dev.parent = &pdev->dev;
1165 idev->name = dev_name(&pdev->dev);
1166 idev->modes = INDIO_DIRECT_MODE;
1167 idev->info = &at91_adc_info;
1168
1169 st->irq = platform_get_irq(pdev, 0);
1170 if (st->irq < 0) {
1171 dev_err(&pdev->dev, "No IRQ ID is designated\n");
1172 return -ENODEV;
1173 }
1174
1175 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1176
1177 st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1178 if (IS_ERR(st->reg_base)) {
1179 return PTR_ERR(st->reg_base);
1180 }
1181
1182 /*
1183 * Disable all IRQs before setting up the handler
1184 */
1185 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1186 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1187
1188 if (st->caps->has_tsmr)
1189 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1190 pdev->dev.driver->name, idev);
1191 else
1192 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1193 pdev->dev.driver->name, idev);
1194 if (ret) {
1195 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1196 return ret;
1197 }
1198
1199 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1200 if (IS_ERR(st->clk)) {
1201 dev_err(&pdev->dev, "Failed to get the clock.\n");
1202 ret = PTR_ERR(st->clk);
1203 goto error_free_irq;
1204 }
1205
1206 ret = clk_prepare_enable(st->clk);
1207 if (ret) {
1208 dev_err(&pdev->dev,
1209 "Could not prepare or enable the clock.\n");
1210 goto error_free_irq;
1211 }
1212
1213 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1214 if (IS_ERR(st->adc_clk)) {
1215 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1216 ret = PTR_ERR(st->adc_clk);
1217 goto error_disable_clk;
1218 }
1219
1220 ret = clk_prepare_enable(st->adc_clk);
1221 if (ret) {
1222 dev_err(&pdev->dev,
1223 "Could not prepare or enable the ADC clock.\n");
1224 goto error_disable_clk;
1225 }
1226
1227 /*
1228 * Prescaler rate computation using the formula from the Atmel's
1229 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1230 * specified by the electrical characteristics of the board.
1231 */
1232 mstrclk = clk_get_rate(st->clk);
1233 adc_clk = clk_get_rate(st->adc_clk);
1234 adc_clk_khz = adc_clk / 1000;
1235
1236 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1237 mstrclk, adc_clk);
1238
1239 prsc = (mstrclk / (2 * adc_clk)) - 1;
1240
1241 if (!st->startup_time) {
1242 dev_err(&pdev->dev, "No startup time available.\n");
1243 ret = -EINVAL;
1244 goto error_disable_adc_clk;
1245 }
1246 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1247
1248 /*
1249 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1250 * the best converted final value between two channels selection
1251 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1252 */
1253 if (st->sample_hold_time > 0)
1254 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1255 - 1, 1);
1256 else
1257 shtim = 0;
1258
1259 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1260 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1261 if (st->low_res)
1262 reg |= AT91_ADC_LOWRES;
1263 if (st->sleep_mode)
1264 reg |= AT91_ADC_SLEEP;
1265 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1266 at91_adc_writel(st, AT91_ADC_MR, reg);
1267
1268 /* Setup the ADC channels available on the board */
1269 ret = at91_adc_channel_init(idev);
1270 if (ret < 0) {
1271 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1272 goto error_disable_adc_clk;
1273 }
1274
1275 init_waitqueue_head(&st->wq_data_avail);
1276 mutex_init(&st->lock);
1277
1278 /*
1279 * Since touch screen will set trigger register as period trigger. So
1280 * when touch screen is enabled, then we have to disable hardware
1281 * trigger for classic adc.
1282 */
1283 if (!st->touchscreen_type) {
1284 ret = at91_adc_buffer_init(idev);
1285 if (ret < 0) {
1286 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1287 goto error_disable_adc_clk;
1288 }
1289
1290 ret = at91_adc_trigger_init(idev);
1291 if (ret < 0) {
1292 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1293 at91_adc_buffer_remove(idev);
1294 goto error_disable_adc_clk;
1295 }
1296 } else {
1297 ret = at91_ts_register(st, pdev);
1298 if (ret)
1299 goto error_disable_adc_clk;
1300
1301 at91_ts_hw_init(st, adc_clk_khz);
1302 }
1303
1304 ret = iio_device_register(idev);
1305 if (ret < 0) {
1306 dev_err(&pdev->dev, "Couldn't register the device.\n");
1307 goto error_iio_device_register;
1308 }
1309
1310 return 0;
1311
1312 error_iio_device_register:
1313 if (!st->touchscreen_type) {
1314 at91_adc_trigger_remove(idev);
1315 at91_adc_buffer_remove(idev);
1316 } else {
1317 at91_ts_unregister(st);
1318 }
1319 error_disable_adc_clk:
1320 clk_disable_unprepare(st->adc_clk);
1321 error_disable_clk:
1322 clk_disable_unprepare(st->clk);
1323 error_free_irq:
1324 free_irq(st->irq, idev);
1325 return ret;
1326 }
1327
at91_adc_remove(struct platform_device * pdev)1328 static int at91_adc_remove(struct platform_device *pdev)
1329 {
1330 struct iio_dev *idev = platform_get_drvdata(pdev);
1331 struct at91_adc_state *st = iio_priv(idev);
1332
1333 iio_device_unregister(idev);
1334 if (!st->touchscreen_type) {
1335 at91_adc_trigger_remove(idev);
1336 at91_adc_buffer_remove(idev);
1337 } else {
1338 at91_ts_unregister(st);
1339 }
1340 clk_disable_unprepare(st->adc_clk);
1341 clk_disable_unprepare(st->clk);
1342 free_irq(st->irq, idev);
1343
1344 return 0;
1345 }
1346
1347 static struct at91_adc_caps at91sam9260_caps = {
1348 .calc_startup_ticks = calc_startup_ticks_9260,
1349 .num_channels = 4,
1350 .registers = {
1351 .channel_base = AT91_ADC_CHR(0),
1352 .drdy_mask = AT91_ADC_DRDY,
1353 .status_register = AT91_ADC_SR,
1354 .trigger_register = AT91_ADC_TRGR_9260,
1355 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1356 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1357 },
1358 };
1359
1360 static struct at91_adc_caps at91sam9rl_caps = {
1361 .has_ts = true,
1362 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1363 .num_channels = 6,
1364 .registers = {
1365 .channel_base = AT91_ADC_CHR(0),
1366 .drdy_mask = AT91_ADC_DRDY,
1367 .status_register = AT91_ADC_SR,
1368 .trigger_register = AT91_ADC_TRGR_9G45,
1369 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1370 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1371 },
1372 };
1373
1374 static struct at91_adc_caps at91sam9g45_caps = {
1375 .has_ts = true,
1376 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1377 .num_channels = 8,
1378 .registers = {
1379 .channel_base = AT91_ADC_CHR(0),
1380 .drdy_mask = AT91_ADC_DRDY,
1381 .status_register = AT91_ADC_SR,
1382 .trigger_register = AT91_ADC_TRGR_9G45,
1383 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1384 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1385 },
1386 };
1387
1388 static struct at91_adc_caps at91sam9x5_caps = {
1389 .has_ts = true,
1390 .has_tsmr = true,
1391 .ts_filter_average = 3,
1392 .ts_pen_detect_sensitivity = 2,
1393 .calc_startup_ticks = calc_startup_ticks_9x5,
1394 .num_channels = 12,
1395 .registers = {
1396 .channel_base = AT91_ADC_CDR0_9X5,
1397 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1398 .status_register = AT91_ADC_SR_9X5,
1399 .trigger_register = AT91_ADC_TRGR_9X5,
1400 /* prescal mask is same as 9G45 */
1401 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1402 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1403 },
1404 };
1405
1406 static const struct of_device_id at91_adc_dt_ids[] = {
1407 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1408 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1409 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1410 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1411 {},
1412 };
1413 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1414
1415 static const struct platform_device_id at91_adc_ids[] = {
1416 {
1417 .name = "at91sam9260-adc",
1418 .driver_data = (unsigned long)&at91sam9260_caps,
1419 }, {
1420 .name = "at91sam9rl-adc",
1421 .driver_data = (unsigned long)&at91sam9rl_caps,
1422 }, {
1423 .name = "at91sam9g45-adc",
1424 .driver_data = (unsigned long)&at91sam9g45_caps,
1425 }, {
1426 .name = "at91sam9x5-adc",
1427 .driver_data = (unsigned long)&at91sam9x5_caps,
1428 }, {
1429 /* terminator */
1430 }
1431 };
1432 MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1433
1434 static struct platform_driver at91_adc_driver = {
1435 .probe = at91_adc_probe,
1436 .remove = at91_adc_remove,
1437 .id_table = at91_adc_ids,
1438 .driver = {
1439 .name = DRIVER_NAME,
1440 .of_match_table = of_match_ptr(at91_adc_dt_ids),
1441 },
1442 };
1443
1444 module_platform_driver(at91_adc_driver);
1445
1446 MODULE_LICENSE("GPL");
1447 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1448 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1449