1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/log2.h>
35 #include <linux/slab.h>
36 #include <linux/netdevice.h>
37 #include <linux/vmalloc.h>
38
39 #include <rdma/ib_cache.h>
40 #include <rdma/ib_pack.h>
41 #include <rdma/ib_addr.h>
42 #include <rdma/ib_mad.h>
43
44 #include <linux/mlx4/driver.h>
45 #include <linux/mlx4/qp.h>
46
47 #include "mlx4_ib.h"
48 #include "user.h"
49
50 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
51 struct mlx4_ib_cq *recv_cq);
52 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54
55 enum {
56 MLX4_IB_ACK_REQ_FREQ = 8,
57 };
58
59 enum {
60 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
61 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
62 MLX4_IB_LINK_TYPE_IB = 0,
63 MLX4_IB_LINK_TYPE_ETH = 1
64 };
65
66 enum {
67 /*
68 * Largest possible UD header: send with GRH and immediate
69 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
70 * tag. (LRH would only use 8 bytes, so Ethernet is the
71 * biggest case)
72 */
73 MLX4_IB_UD_HEADER_SIZE = 82,
74 MLX4_IB_LSO_HEADER_SPARE = 128,
75 };
76
77 enum {
78 MLX4_IB_IBOE_ETHERTYPE = 0x8915
79 };
80
81 struct mlx4_ib_sqp {
82 struct mlx4_ib_qp qp;
83 int pkey_index;
84 u32 qkey;
85 u32 send_psn;
86 struct ib_ud_header ud_header;
87 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
88 };
89
90 enum {
91 MLX4_IB_MIN_SQ_STRIDE = 6,
92 MLX4_IB_CACHE_LINE_SIZE = 64,
93 };
94
95 enum {
96 MLX4_RAW_QP_MTU = 7,
97 MLX4_RAW_QP_MSGMAX = 31,
98 };
99
100 #ifndef ETH_ALEN
101 #define ETH_ALEN 6
102 #endif
103
104 static const __be32 mlx4_ib_opcode[] = {
105 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
106 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
107 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
108 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
109 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
110 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
111 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
112 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
113 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
114 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
115 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
116 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
117 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
118 [IB_WR_BIND_MW] = cpu_to_be32(MLX4_OPCODE_BIND_MW),
119 };
120
to_msqp(struct mlx4_ib_qp * mqp)121 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
122 {
123 return container_of(mqp, struct mlx4_ib_sqp, qp);
124 }
125
is_tunnel_qp(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)126 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
127 {
128 if (!mlx4_is_master(dev->dev))
129 return 0;
130
131 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
132 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
133 8 * MLX4_MFUNC_MAX;
134 }
135
is_sqp(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)136 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
137 {
138 int proxy_sqp = 0;
139 int real_sqp = 0;
140 int i;
141 /* PPF or Native -- real SQP */
142 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
143 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
144 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
145 if (real_sqp)
146 return 1;
147 /* VF or PF -- proxy SQP */
148 if (mlx4_is_mfunc(dev->dev)) {
149 for (i = 0; i < dev->dev->caps.num_ports; i++) {
150 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
151 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
152 proxy_sqp = 1;
153 break;
154 }
155 }
156 }
157 return proxy_sqp;
158 }
159
160 /* used for INIT/CLOSE port logic */
is_qp0(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)161 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
162 {
163 int proxy_qp0 = 0;
164 int real_qp0 = 0;
165 int i;
166 /* PPF or Native -- real QP0 */
167 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
168 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
169 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
170 if (real_qp0)
171 return 1;
172 /* VF or PF -- proxy QP0 */
173 if (mlx4_is_mfunc(dev->dev)) {
174 for (i = 0; i < dev->dev->caps.num_ports; i++) {
175 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
176 proxy_qp0 = 1;
177 break;
178 }
179 }
180 }
181 return proxy_qp0;
182 }
183
get_wqe(struct mlx4_ib_qp * qp,int offset)184 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
185 {
186 return mlx4_buf_offset(&qp->buf, offset);
187 }
188
get_recv_wqe(struct mlx4_ib_qp * qp,int n)189 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
190 {
191 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
192 }
193
get_send_wqe(struct mlx4_ib_qp * qp,int n)194 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
195 {
196 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
197 }
198
199 /*
200 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
201 * first four bytes of every 64 byte chunk with
202 * 0x7FFFFFF | (invalid_ownership_value << 31).
203 *
204 * When the max work request size is less than or equal to the WQE
205 * basic block size, as an optimization, we can stamp all WQEs with
206 * 0xffffffff, and skip the very first chunk of each WQE.
207 */
stamp_send_wqe(struct mlx4_ib_qp * qp,int n,int size)208 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
209 {
210 __be32 *wqe;
211 int i;
212 int s;
213 int ind;
214 void *buf;
215 __be32 stamp;
216 struct mlx4_wqe_ctrl_seg *ctrl;
217
218 if (qp->sq_max_wqes_per_wr > 1) {
219 s = roundup(size, 1U << qp->sq.wqe_shift);
220 for (i = 0; i < s; i += 64) {
221 ind = (i >> qp->sq.wqe_shift) + n;
222 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
223 cpu_to_be32(0xffffffff);
224 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
225 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
226 *wqe = stamp;
227 }
228 } else {
229 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
230 s = (ctrl->fence_size & 0x3f) << 4;
231 for (i = 64; i < s; i += 64) {
232 wqe = buf + i;
233 *wqe = cpu_to_be32(0xffffffff);
234 }
235 }
236 }
237
post_nop_wqe(struct mlx4_ib_qp * qp,int n,int size)238 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
239 {
240 struct mlx4_wqe_ctrl_seg *ctrl;
241 struct mlx4_wqe_inline_seg *inl;
242 void *wqe;
243 int s;
244
245 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
246 s = sizeof(struct mlx4_wqe_ctrl_seg);
247
248 if (qp->ibqp.qp_type == IB_QPT_UD) {
249 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
250 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
251 memset(dgram, 0, sizeof *dgram);
252 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
253 s += sizeof(struct mlx4_wqe_datagram_seg);
254 }
255
256 /* Pad the remainder of the WQE with an inline data segment. */
257 if (size > s) {
258 inl = wqe + s;
259 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
260 }
261 ctrl->srcrb_flags = 0;
262 ctrl->fence_size = size / 16;
263 /*
264 * Make sure descriptor is fully written before setting ownership bit
265 * (because HW can start executing as soon as we do).
266 */
267 wmb();
268
269 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
270 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
271
272 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
273 }
274
275 /* Post NOP WQE to prevent wrap-around in the middle of WR */
pad_wraparound(struct mlx4_ib_qp * qp,int ind)276 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
277 {
278 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
279 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
280 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
281 ind += s;
282 }
283 return ind;
284 }
285
mlx4_ib_qp_event(struct mlx4_qp * qp,enum mlx4_event type)286 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
287 {
288 struct ib_event event;
289 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
290
291 if (type == MLX4_EVENT_TYPE_PATH_MIG)
292 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
293
294 if (ibqp->event_handler) {
295 event.device = ibqp->device;
296 event.element.qp = ibqp;
297 switch (type) {
298 case MLX4_EVENT_TYPE_PATH_MIG:
299 event.event = IB_EVENT_PATH_MIG;
300 break;
301 case MLX4_EVENT_TYPE_COMM_EST:
302 event.event = IB_EVENT_COMM_EST;
303 break;
304 case MLX4_EVENT_TYPE_SQ_DRAINED:
305 event.event = IB_EVENT_SQ_DRAINED;
306 break;
307 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
308 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
309 break;
310 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
311 event.event = IB_EVENT_QP_FATAL;
312 break;
313 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
314 event.event = IB_EVENT_PATH_MIG_ERR;
315 break;
316 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
317 event.event = IB_EVENT_QP_REQ_ERR;
318 break;
319 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
320 event.event = IB_EVENT_QP_ACCESS_ERR;
321 break;
322 default:
323 pr_warn("Unexpected event type %d "
324 "on QP %06x\n", type, qp->qpn);
325 return;
326 }
327
328 ibqp->event_handler(&event, ibqp->qp_context);
329 }
330 }
331
send_wqe_overhead(enum mlx4_ib_qp_type type,u32 flags)332 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
333 {
334 /*
335 * UD WQEs must have a datagram segment.
336 * RC and UC WQEs might have a remote address segment.
337 * MLX WQEs need two extra inline data segments (for the UD
338 * header and space for the ICRC).
339 */
340 switch (type) {
341 case MLX4_IB_QPT_UD:
342 return sizeof (struct mlx4_wqe_ctrl_seg) +
343 sizeof (struct mlx4_wqe_datagram_seg) +
344 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
345 case MLX4_IB_QPT_PROXY_SMI_OWNER:
346 case MLX4_IB_QPT_PROXY_SMI:
347 case MLX4_IB_QPT_PROXY_GSI:
348 return sizeof (struct mlx4_wqe_ctrl_seg) +
349 sizeof (struct mlx4_wqe_datagram_seg) + 64;
350 case MLX4_IB_QPT_TUN_SMI_OWNER:
351 case MLX4_IB_QPT_TUN_GSI:
352 return sizeof (struct mlx4_wqe_ctrl_seg) +
353 sizeof (struct mlx4_wqe_datagram_seg);
354
355 case MLX4_IB_QPT_UC:
356 return sizeof (struct mlx4_wqe_ctrl_seg) +
357 sizeof (struct mlx4_wqe_raddr_seg);
358 case MLX4_IB_QPT_RC:
359 return sizeof (struct mlx4_wqe_ctrl_seg) +
360 sizeof (struct mlx4_wqe_masked_atomic_seg) +
361 sizeof (struct mlx4_wqe_raddr_seg);
362 case MLX4_IB_QPT_SMI:
363 case MLX4_IB_QPT_GSI:
364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 ALIGN(MLX4_IB_UD_HEADER_SIZE +
366 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
367 MLX4_INLINE_ALIGN) *
368 sizeof (struct mlx4_wqe_inline_seg),
369 sizeof (struct mlx4_wqe_data_seg)) +
370 ALIGN(4 +
371 sizeof (struct mlx4_wqe_inline_seg),
372 sizeof (struct mlx4_wqe_data_seg));
373 default:
374 return sizeof (struct mlx4_wqe_ctrl_seg);
375 }
376 }
377
set_rq_size(struct mlx4_ib_dev * dev,struct ib_qp_cap * cap,int is_user,int has_rq,struct mlx4_ib_qp * qp)378 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
379 int is_user, int has_rq, struct mlx4_ib_qp *qp)
380 {
381 /* Sanity check RQ size before proceeding */
382 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
383 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
384 return -EINVAL;
385
386 if (!has_rq) {
387 if (cap->max_recv_wr)
388 return -EINVAL;
389
390 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
391 } else {
392 /* HW requires >= 1 RQ entry with >= 1 gather entry */
393 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
394 return -EINVAL;
395
396 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
397 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
398 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
399 }
400
401 /* leave userspace return values as they were, so as not to break ABI */
402 if (is_user) {
403 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
404 cap->max_recv_sge = qp->rq.max_gs;
405 } else {
406 cap->max_recv_wr = qp->rq.max_post =
407 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
408 cap->max_recv_sge = min(qp->rq.max_gs,
409 min(dev->dev->caps.max_sq_sg,
410 dev->dev->caps.max_rq_sg));
411 }
412
413 return 0;
414 }
415
set_kernel_sq_size(struct mlx4_ib_dev * dev,struct ib_qp_cap * cap,enum mlx4_ib_qp_type type,struct mlx4_ib_qp * qp)416 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
417 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
418 {
419 int s;
420
421 /* Sanity check SQ size before proceeding */
422 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
423 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
424 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
425 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
426 return -EINVAL;
427
428 /*
429 * For MLX transport we need 2 extra S/G entries:
430 * one for the header and one for the checksum at the end
431 */
432 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
433 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
434 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
435 return -EINVAL;
436
437 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
438 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
439 send_wqe_overhead(type, qp->flags);
440
441 if (s > dev->dev->caps.max_sq_desc_sz)
442 return -EINVAL;
443
444 /*
445 * Hermon supports shrinking WQEs, such that a single work
446 * request can include multiple units of 1 << wqe_shift. This
447 * way, work requests can differ in size, and do not have to
448 * be a power of 2 in size, saving memory and speeding up send
449 * WR posting. Unfortunately, if we do this then the
450 * wqe_index field in CQEs can't be used to look up the WR ID
451 * anymore, so we do this only if selective signaling is off.
452 *
453 * Further, on 32-bit platforms, we can't use vmap() to make
454 * the QP buffer virtually contiguous. Thus we have to use
455 * constant-sized WRs to make sure a WR is always fully within
456 * a single page-sized chunk.
457 *
458 * Finally, we use NOP work requests to pad the end of the
459 * work queue, to avoid wrap-around in the middle of WR. We
460 * set NEC bit to avoid getting completions with error for
461 * these NOP WRs, but since NEC is only supported starting
462 * with firmware 2.2.232, we use constant-sized WRs for older
463 * firmware.
464 *
465 * And, since MLX QPs only support SEND, we use constant-sized
466 * WRs in this case.
467 *
468 * We look for the smallest value of wqe_shift such that the
469 * resulting number of wqes does not exceed device
470 * capabilities.
471 *
472 * We set WQE size to at least 64 bytes, this way stamping
473 * invalidates each WQE.
474 */
475 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
476 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
477 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
478 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
479 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
480 qp->sq.wqe_shift = ilog2(64);
481 else
482 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
483
484 for (;;) {
485 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
486
487 /*
488 * We need to leave 2 KB + 1 WR of headroom in the SQ to
489 * allow HW to prefetch.
490 */
491 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
492 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
493 qp->sq_max_wqes_per_wr +
494 qp->sq_spare_wqes);
495
496 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
497 break;
498
499 if (qp->sq_max_wqes_per_wr <= 1)
500 return -EINVAL;
501
502 ++qp->sq.wqe_shift;
503 }
504
505 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
506 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
507 send_wqe_overhead(type, qp->flags)) /
508 sizeof (struct mlx4_wqe_data_seg);
509
510 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
511 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
512 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
513 qp->rq.offset = 0;
514 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
515 } else {
516 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
517 qp->sq.offset = 0;
518 }
519
520 cap->max_send_wr = qp->sq.max_post =
521 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
522 cap->max_send_sge = min(qp->sq.max_gs,
523 min(dev->dev->caps.max_sq_sg,
524 dev->dev->caps.max_rq_sg));
525 /* We don't support inline sends for kernel QPs (yet) */
526 cap->max_inline_data = 0;
527
528 return 0;
529 }
530
set_user_sq_size(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp,struct mlx4_ib_create_qp * ucmd)531 static int set_user_sq_size(struct mlx4_ib_dev *dev,
532 struct mlx4_ib_qp *qp,
533 struct mlx4_ib_create_qp *ucmd)
534 {
535 /* Sanity check SQ size before proceeding */
536 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
537 ucmd->log_sq_stride >
538 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
539 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
540 return -EINVAL;
541
542 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
543 qp->sq.wqe_shift = ucmd->log_sq_stride;
544
545 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
546 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
547
548 return 0;
549 }
550
alloc_proxy_bufs(struct ib_device * dev,struct mlx4_ib_qp * qp)551 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
552 {
553 int i;
554
555 qp->sqp_proxy_rcv =
556 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
557 GFP_KERNEL);
558 if (!qp->sqp_proxy_rcv)
559 return -ENOMEM;
560 for (i = 0; i < qp->rq.wqe_cnt; i++) {
561 qp->sqp_proxy_rcv[i].addr =
562 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
563 GFP_KERNEL);
564 if (!qp->sqp_proxy_rcv[i].addr)
565 goto err;
566 qp->sqp_proxy_rcv[i].map =
567 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
568 sizeof (struct mlx4_ib_proxy_sqp_hdr),
569 DMA_FROM_DEVICE);
570 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
571 kfree(qp->sqp_proxy_rcv[i].addr);
572 goto err;
573 }
574 }
575 return 0;
576
577 err:
578 while (i > 0) {
579 --i;
580 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
581 sizeof (struct mlx4_ib_proxy_sqp_hdr),
582 DMA_FROM_DEVICE);
583 kfree(qp->sqp_proxy_rcv[i].addr);
584 }
585 kfree(qp->sqp_proxy_rcv);
586 qp->sqp_proxy_rcv = NULL;
587 return -ENOMEM;
588 }
589
free_proxy_bufs(struct ib_device * dev,struct mlx4_ib_qp * qp)590 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
591 {
592 int i;
593
594 for (i = 0; i < qp->rq.wqe_cnt; i++) {
595 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
596 sizeof (struct mlx4_ib_proxy_sqp_hdr),
597 DMA_FROM_DEVICE);
598 kfree(qp->sqp_proxy_rcv[i].addr);
599 }
600 kfree(qp->sqp_proxy_rcv);
601 }
602
qp_has_rq(struct ib_qp_init_attr * attr)603 static int qp_has_rq(struct ib_qp_init_attr *attr)
604 {
605 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
606 return 0;
607
608 return !attr->srq;
609 }
610
qp0_enabled_vf(struct mlx4_dev * dev,int qpn)611 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
612 {
613 int i;
614 for (i = 0; i < dev->caps.num_ports; i++) {
615 if (qpn == dev->caps.qp0_proxy[i])
616 return !!dev->caps.qp0_qkey[i];
617 }
618 return 0;
619 }
620
mlx4_ib_free_qp_counter(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)621 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
622 struct mlx4_ib_qp *qp)
623 {
624 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
625 mlx4_counter_free(dev->dev, qp->counter_index->index);
626 list_del(&qp->counter_index->list);
627 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
628
629 kfree(qp->counter_index);
630 qp->counter_index = NULL;
631 }
632
create_qp_common(struct mlx4_ib_dev * dev,struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata,int sqpn,struct mlx4_ib_qp ** caller_qp,gfp_t gfp)633 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
634 struct ib_qp_init_attr *init_attr,
635 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
636 gfp_t gfp)
637 {
638 int qpn;
639 int err;
640 struct mlx4_ib_sqp *sqp;
641 struct mlx4_ib_qp *qp;
642 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
643 struct mlx4_ib_cq *mcq;
644 unsigned long flags;
645
646 /* When tunneling special qps, we use a plain UD qp */
647 if (sqpn) {
648 if (mlx4_is_mfunc(dev->dev) &&
649 (!mlx4_is_master(dev->dev) ||
650 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
651 if (init_attr->qp_type == IB_QPT_GSI)
652 qp_type = MLX4_IB_QPT_PROXY_GSI;
653 else {
654 if (mlx4_is_master(dev->dev) ||
655 qp0_enabled_vf(dev->dev, sqpn))
656 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
657 else
658 qp_type = MLX4_IB_QPT_PROXY_SMI;
659 }
660 }
661 qpn = sqpn;
662 /* add extra sg entry for tunneling */
663 init_attr->cap.max_recv_sge++;
664 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
665 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
666 container_of(init_attr,
667 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
668 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
669 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
670 !mlx4_is_master(dev->dev))
671 return -EINVAL;
672 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
673 qp_type = MLX4_IB_QPT_TUN_GSI;
674 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
675 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
676 tnl_init->port))
677 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
678 else
679 qp_type = MLX4_IB_QPT_TUN_SMI;
680 /* we are definitely in the PPF here, since we are creating
681 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
682 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
683 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
684 sqpn = qpn;
685 }
686
687 if (!*caller_qp) {
688 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
689 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
690 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
691 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
692 if (!sqp)
693 return -ENOMEM;
694 qp = &sqp->qp;
695 qp->pri.vid = 0xFFFF;
696 qp->alt.vid = 0xFFFF;
697 } else {
698 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
699 if (!qp)
700 return -ENOMEM;
701 qp->pri.vid = 0xFFFF;
702 qp->alt.vid = 0xFFFF;
703 }
704 } else
705 qp = *caller_qp;
706
707 qp->mlx4_ib_qp_type = qp_type;
708
709 mutex_init(&qp->mutex);
710 spin_lock_init(&qp->sq.lock);
711 spin_lock_init(&qp->rq.lock);
712 INIT_LIST_HEAD(&qp->gid_list);
713 INIT_LIST_HEAD(&qp->steering_rules);
714
715 qp->state = IB_QPS_RESET;
716 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
717 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
718
719 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
720 if (err)
721 goto err;
722
723 if (pd->uobject) {
724 struct mlx4_ib_create_qp ucmd;
725
726 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
727 err = -EFAULT;
728 goto err;
729 }
730
731 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
732
733 err = set_user_sq_size(dev, qp, &ucmd);
734 if (err)
735 goto err;
736
737 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
738 qp->buf_size, 0, 0);
739 if (IS_ERR(qp->umem)) {
740 err = PTR_ERR(qp->umem);
741 goto err;
742 }
743
744 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
745 ilog2(qp->umem->page_size), &qp->mtt);
746 if (err)
747 goto err_buf;
748
749 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
750 if (err)
751 goto err_mtt;
752
753 if (qp_has_rq(init_attr)) {
754 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
755 ucmd.db_addr, &qp->db);
756 if (err)
757 goto err_mtt;
758 }
759 } else {
760 qp->sq_no_prefetch = 0;
761
762 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
763 qp->flags |= MLX4_IB_QP_LSO;
764
765 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
766 if (dev->steering_support ==
767 MLX4_STEERING_MODE_DEVICE_MANAGED)
768 qp->flags |= MLX4_IB_QP_NETIF;
769 else {
770 err = -EINVAL;
771 goto err;
772 }
773 }
774
775 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
776 if (err)
777 goto err;
778
779 if (qp_has_rq(init_attr)) {
780 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
781 if (err)
782 goto err;
783
784 *qp->db.db = 0;
785 }
786
787 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
788 err = -ENOMEM;
789 goto err_db;
790 }
791
792 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
793 &qp->mtt);
794 if (err)
795 goto err_buf;
796
797 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
798 if (err)
799 goto err_mtt;
800
801 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(u64), gfp);
802 if (!qp->sq.wrid)
803 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
804 gfp, PAGE_KERNEL);
805 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(u64), gfp);
806 if (!qp->rq.wrid)
807 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
808 gfp, PAGE_KERNEL);
809 if (!qp->sq.wrid || !qp->rq.wrid) {
810 err = -ENOMEM;
811 goto err_wrid;
812 }
813 }
814
815 if (sqpn) {
816 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
817 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
818 if (alloc_proxy_bufs(pd->device, qp)) {
819 err = -ENOMEM;
820 goto err_wrid;
821 }
822 }
823 } else {
824 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
825 * otherwise, the WQE BlueFlame setup flow wrongly causes
826 * VLAN insertion. */
827 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
828 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
829 (init_attr->cap.max_send_wr ?
830 MLX4_RESERVE_ETH_BF_QP : 0) |
831 (init_attr->cap.max_recv_wr ?
832 MLX4_RESERVE_A0_QP : 0));
833 else
834 if (qp->flags & MLX4_IB_QP_NETIF)
835 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
836 else
837 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
838 &qpn, 0);
839 if (err)
840 goto err_proxy;
841 }
842
843 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
844 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
845
846 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
847 if (err)
848 goto err_qpn;
849
850 if (init_attr->qp_type == IB_QPT_XRC_TGT)
851 qp->mqp.qpn |= (1 << 23);
852
853 /*
854 * Hardware wants QPN written in big-endian order (after
855 * shifting) for send doorbell. Precompute this value to save
856 * a little bit when posting sends.
857 */
858 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
859
860 qp->mqp.event = mlx4_ib_qp_event;
861 if (!*caller_qp)
862 *caller_qp = qp;
863
864 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
865 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
866 to_mcq(init_attr->recv_cq));
867 /* Maintain device to QPs access, needed for further handling
868 * via reset flow
869 */
870 list_add_tail(&qp->qps_list, &dev->qp_list);
871 /* Maintain CQ to QPs access, needed for further handling
872 * via reset flow
873 */
874 mcq = to_mcq(init_attr->send_cq);
875 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
876 mcq = to_mcq(init_attr->recv_cq);
877 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
878 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
879 to_mcq(init_attr->recv_cq));
880 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
881 return 0;
882
883 err_qpn:
884 if (!sqpn) {
885 if (qp->flags & MLX4_IB_QP_NETIF)
886 mlx4_ib_steer_qp_free(dev, qpn, 1);
887 else
888 mlx4_qp_release_range(dev->dev, qpn, 1);
889 }
890 err_proxy:
891 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
892 free_proxy_bufs(pd->device, qp);
893 err_wrid:
894 if (pd->uobject) {
895 if (qp_has_rq(init_attr))
896 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
897 } else {
898 kvfree(qp->sq.wrid);
899 kvfree(qp->rq.wrid);
900 }
901
902 err_mtt:
903 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
904
905 err_buf:
906 if (pd->uobject)
907 ib_umem_release(qp->umem);
908 else
909 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
910
911 err_db:
912 if (!pd->uobject && qp_has_rq(init_attr))
913 mlx4_db_free(dev->dev, &qp->db);
914
915 err:
916 if (!*caller_qp)
917 kfree(qp);
918 return err;
919 }
920
to_mlx4_state(enum ib_qp_state state)921 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
922 {
923 switch (state) {
924 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
925 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
926 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
927 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
928 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
929 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
930 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
931 default: return -1;
932 }
933 }
934
mlx4_ib_lock_cqs(struct mlx4_ib_cq * send_cq,struct mlx4_ib_cq * recv_cq)935 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
936 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
937 {
938 if (send_cq == recv_cq) {
939 spin_lock(&send_cq->lock);
940 __acquire(&recv_cq->lock);
941 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
942 spin_lock(&send_cq->lock);
943 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
944 } else {
945 spin_lock(&recv_cq->lock);
946 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
947 }
948 }
949
mlx4_ib_unlock_cqs(struct mlx4_ib_cq * send_cq,struct mlx4_ib_cq * recv_cq)950 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
951 __releases(&send_cq->lock) __releases(&recv_cq->lock)
952 {
953 if (send_cq == recv_cq) {
954 __release(&recv_cq->lock);
955 spin_unlock(&send_cq->lock);
956 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
957 spin_unlock(&recv_cq->lock);
958 spin_unlock(&send_cq->lock);
959 } else {
960 spin_unlock(&send_cq->lock);
961 spin_unlock(&recv_cq->lock);
962 }
963 }
964
del_gid_entries(struct mlx4_ib_qp * qp)965 static void del_gid_entries(struct mlx4_ib_qp *qp)
966 {
967 struct mlx4_ib_gid_entry *ge, *tmp;
968
969 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
970 list_del(&ge->list);
971 kfree(ge);
972 }
973 }
974
get_pd(struct mlx4_ib_qp * qp)975 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
976 {
977 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
978 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
979 else
980 return to_mpd(qp->ibqp.pd);
981 }
982
get_cqs(struct mlx4_ib_qp * qp,struct mlx4_ib_cq ** send_cq,struct mlx4_ib_cq ** recv_cq)983 static void get_cqs(struct mlx4_ib_qp *qp,
984 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
985 {
986 switch (qp->ibqp.qp_type) {
987 case IB_QPT_XRC_TGT:
988 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
989 *recv_cq = *send_cq;
990 break;
991 case IB_QPT_XRC_INI:
992 *send_cq = to_mcq(qp->ibqp.send_cq);
993 *recv_cq = *send_cq;
994 break;
995 default:
996 *send_cq = to_mcq(qp->ibqp.send_cq);
997 *recv_cq = to_mcq(qp->ibqp.recv_cq);
998 break;
999 }
1000 }
1001
destroy_qp_common(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp,int is_user)1002 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1003 int is_user)
1004 {
1005 struct mlx4_ib_cq *send_cq, *recv_cq;
1006 unsigned long flags;
1007
1008 if (qp->state != IB_QPS_RESET) {
1009 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1010 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1011 pr_warn("modify QP %06x to RESET failed.\n",
1012 qp->mqp.qpn);
1013 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1014 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1015 qp->pri.smac = 0;
1016 qp->pri.smac_port = 0;
1017 }
1018 if (qp->alt.smac) {
1019 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1020 qp->alt.smac = 0;
1021 }
1022 if (qp->pri.vid < 0x1000) {
1023 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1024 qp->pri.vid = 0xFFFF;
1025 qp->pri.candidate_vid = 0xFFFF;
1026 qp->pri.update_vid = 0;
1027 }
1028 if (qp->alt.vid < 0x1000) {
1029 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1030 qp->alt.vid = 0xFFFF;
1031 qp->alt.candidate_vid = 0xFFFF;
1032 qp->alt.update_vid = 0;
1033 }
1034 }
1035
1036 get_cqs(qp, &send_cq, &recv_cq);
1037
1038 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1039 mlx4_ib_lock_cqs(send_cq, recv_cq);
1040
1041 /* del from lists under both locks above to protect reset flow paths */
1042 list_del(&qp->qps_list);
1043 list_del(&qp->cq_send_list);
1044 list_del(&qp->cq_recv_list);
1045 if (!is_user) {
1046 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1047 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1048 if (send_cq != recv_cq)
1049 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1050 }
1051
1052 mlx4_qp_remove(dev->dev, &qp->mqp);
1053
1054 mlx4_ib_unlock_cqs(send_cq, recv_cq);
1055 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1056
1057 mlx4_qp_free(dev->dev, &qp->mqp);
1058
1059 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1060 if (qp->flags & MLX4_IB_QP_NETIF)
1061 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1062 else
1063 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1064 }
1065
1066 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1067
1068 if (is_user) {
1069 if (qp->rq.wqe_cnt)
1070 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1071 &qp->db);
1072 ib_umem_release(qp->umem);
1073 } else {
1074 kvfree(qp->sq.wrid);
1075 kvfree(qp->rq.wrid);
1076 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1077 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1078 free_proxy_bufs(&dev->ib_dev, qp);
1079 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1080 if (qp->rq.wqe_cnt)
1081 mlx4_db_free(dev->dev, &qp->db);
1082 }
1083
1084 del_gid_entries(qp);
1085 }
1086
get_sqp_num(struct mlx4_ib_dev * dev,struct ib_qp_init_attr * attr)1087 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1088 {
1089 /* Native or PPF */
1090 if (!mlx4_is_mfunc(dev->dev) ||
1091 (mlx4_is_master(dev->dev) &&
1092 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1093 return dev->dev->phys_caps.base_sqpn +
1094 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1095 attr->port_num - 1;
1096 }
1097 /* PF or VF -- creating proxies */
1098 if (attr->qp_type == IB_QPT_SMI)
1099 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1100 else
1101 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1102 }
1103
mlx4_ib_create_qp(struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1104 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1105 struct ib_qp_init_attr *init_attr,
1106 struct ib_udata *udata)
1107 {
1108 struct mlx4_ib_qp *qp = NULL;
1109 int err;
1110 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1111 u16 xrcdn = 0;
1112 gfp_t gfp;
1113
1114 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1115 GFP_NOIO : GFP_KERNEL;
1116 /*
1117 * We only support LSO, vendor flag1, and multicast loopback blocking,
1118 * and only for kernel UD QPs.
1119 */
1120 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1121 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1122 MLX4_IB_SRIOV_TUNNEL_QP |
1123 MLX4_IB_SRIOV_SQP |
1124 MLX4_IB_QP_NETIF |
1125 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1126 return ERR_PTR(-EINVAL);
1127
1128 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1129 if (init_attr->qp_type != IB_QPT_UD)
1130 return ERR_PTR(-EINVAL);
1131 }
1132
1133 if (init_attr->create_flags &&
1134 ((udata && init_attr->create_flags & ~(sup_u_create_flags)) ||
1135 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1136 MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1137 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)) &&
1138 init_attr->qp_type != IB_QPT_UD) ||
1139 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1140 init_attr->qp_type > IB_QPT_GSI)))
1141 return ERR_PTR(-EINVAL);
1142
1143 switch (init_attr->qp_type) {
1144 case IB_QPT_XRC_TGT:
1145 pd = to_mxrcd(init_attr->xrcd)->pd;
1146 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1147 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1148 /* fall through */
1149 case IB_QPT_XRC_INI:
1150 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1151 return ERR_PTR(-ENOSYS);
1152 init_attr->recv_cq = init_attr->send_cq;
1153 /* fall through */
1154 case IB_QPT_RC:
1155 case IB_QPT_UC:
1156 case IB_QPT_RAW_PACKET:
1157 qp = kzalloc(sizeof *qp, gfp);
1158 if (!qp)
1159 return ERR_PTR(-ENOMEM);
1160 qp->pri.vid = 0xFFFF;
1161 qp->alt.vid = 0xFFFF;
1162 /* fall through */
1163 case IB_QPT_UD:
1164 {
1165 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1166 udata, 0, &qp, gfp);
1167 if (err) {
1168 kfree(qp);
1169 return ERR_PTR(err);
1170 }
1171
1172 qp->ibqp.qp_num = qp->mqp.qpn;
1173 qp->xrcdn = xrcdn;
1174
1175 break;
1176 }
1177 case IB_QPT_SMI:
1178 case IB_QPT_GSI:
1179 {
1180 /* Userspace is not allowed to create special QPs: */
1181 if (udata)
1182 return ERR_PTR(-EINVAL);
1183
1184 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1185 get_sqp_num(to_mdev(pd->device), init_attr),
1186 &qp, gfp);
1187 if (err)
1188 return ERR_PTR(err);
1189
1190 qp->port = init_attr->port_num;
1191 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1192
1193 break;
1194 }
1195 default:
1196 /* Don't support raw QPs */
1197 return ERR_PTR(-EINVAL);
1198 }
1199
1200 return &qp->ibqp;
1201 }
1202
mlx4_ib_destroy_qp(struct ib_qp * qp)1203 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1204 {
1205 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1206 struct mlx4_ib_qp *mqp = to_mqp(qp);
1207 struct mlx4_ib_pd *pd;
1208
1209 if (is_qp0(dev, mqp))
1210 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1211
1212 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1213 dev->qp1_proxy[mqp->port - 1] == mqp) {
1214 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1215 dev->qp1_proxy[mqp->port - 1] = NULL;
1216 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1217 }
1218
1219 if (mqp->counter_index)
1220 mlx4_ib_free_qp_counter(dev, mqp);
1221
1222 pd = get_pd(mqp);
1223 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1224
1225 if (is_sqp(dev, mqp))
1226 kfree(to_msqp(mqp));
1227 else
1228 kfree(mqp);
1229
1230 return 0;
1231 }
1232
to_mlx4_st(struct mlx4_ib_dev * dev,enum mlx4_ib_qp_type type)1233 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1234 {
1235 switch (type) {
1236 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1237 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1238 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1239 case MLX4_IB_QPT_XRC_INI:
1240 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1241 case MLX4_IB_QPT_SMI:
1242 case MLX4_IB_QPT_GSI:
1243 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1244
1245 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1246 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1247 MLX4_QP_ST_MLX : -1);
1248 case MLX4_IB_QPT_PROXY_SMI:
1249 case MLX4_IB_QPT_TUN_SMI:
1250 case MLX4_IB_QPT_PROXY_GSI:
1251 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1252 MLX4_QP_ST_UD : -1);
1253 default: return -1;
1254 }
1255 }
1256
to_mlx4_access_flags(struct mlx4_ib_qp * qp,const struct ib_qp_attr * attr,int attr_mask)1257 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1258 int attr_mask)
1259 {
1260 u8 dest_rd_atomic;
1261 u32 access_flags;
1262 u32 hw_access_flags = 0;
1263
1264 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1265 dest_rd_atomic = attr->max_dest_rd_atomic;
1266 else
1267 dest_rd_atomic = qp->resp_depth;
1268
1269 if (attr_mask & IB_QP_ACCESS_FLAGS)
1270 access_flags = attr->qp_access_flags;
1271 else
1272 access_flags = qp->atomic_rd_en;
1273
1274 if (!dest_rd_atomic)
1275 access_flags &= IB_ACCESS_REMOTE_WRITE;
1276
1277 if (access_flags & IB_ACCESS_REMOTE_READ)
1278 hw_access_flags |= MLX4_QP_BIT_RRE;
1279 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1280 hw_access_flags |= MLX4_QP_BIT_RAE;
1281 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1282 hw_access_flags |= MLX4_QP_BIT_RWE;
1283
1284 return cpu_to_be32(hw_access_flags);
1285 }
1286
store_sqp_attrs(struct mlx4_ib_sqp * sqp,const struct ib_qp_attr * attr,int attr_mask)1287 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1288 int attr_mask)
1289 {
1290 if (attr_mask & IB_QP_PKEY_INDEX)
1291 sqp->pkey_index = attr->pkey_index;
1292 if (attr_mask & IB_QP_QKEY)
1293 sqp->qkey = attr->qkey;
1294 if (attr_mask & IB_QP_SQ_PSN)
1295 sqp->send_psn = attr->sq_psn;
1296 }
1297
mlx4_set_sched(struct mlx4_qp_path * path,u8 port)1298 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1299 {
1300 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1301 }
1302
_mlx4_set_path(struct mlx4_ib_dev * dev,const struct ib_ah_attr * ah,u64 smac,u16 vlan_tag,struct mlx4_qp_path * path,struct mlx4_roce_smac_vlan_info * smac_info,u8 port)1303 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1304 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1305 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1306 {
1307 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1308 IB_LINK_LAYER_ETHERNET;
1309 int vidx;
1310 int smac_index;
1311 int err;
1312
1313
1314 path->grh_mylmc = ah->src_path_bits & 0x7f;
1315 path->rlid = cpu_to_be16(ah->dlid);
1316 if (ah->static_rate) {
1317 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1318 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1319 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1320 --path->static_rate;
1321 } else
1322 path->static_rate = 0;
1323
1324 if (ah->ah_flags & IB_AH_GRH) {
1325 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1326 port,
1327 ah->grh.sgid_index);
1328
1329 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1330 pr_err("sgid_index (%u) too large. max is %d\n",
1331 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1332 return -1;
1333 }
1334
1335 path->grh_mylmc |= 1 << 7;
1336 path->mgid_index = real_sgid_index;
1337 path->hop_limit = ah->grh.hop_limit;
1338 path->tclass_flowlabel =
1339 cpu_to_be32((ah->grh.traffic_class << 20) |
1340 (ah->grh.flow_label));
1341 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1342 }
1343
1344 if (is_eth) {
1345 if (!(ah->ah_flags & IB_AH_GRH))
1346 return -1;
1347
1348 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1349 ((port - 1) << 6) | ((ah->sl & 7) << 3);
1350
1351 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1352 if (vlan_tag < 0x1000) {
1353 if (smac_info->vid < 0x1000) {
1354 /* both valid vlan ids */
1355 if (smac_info->vid != vlan_tag) {
1356 /* different VIDs. unreg old and reg new */
1357 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1358 if (err)
1359 return err;
1360 smac_info->candidate_vid = vlan_tag;
1361 smac_info->candidate_vlan_index = vidx;
1362 smac_info->candidate_vlan_port = port;
1363 smac_info->update_vid = 1;
1364 path->vlan_index = vidx;
1365 } else {
1366 path->vlan_index = smac_info->vlan_index;
1367 }
1368 } else {
1369 /* no current vlan tag in qp */
1370 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1371 if (err)
1372 return err;
1373 smac_info->candidate_vid = vlan_tag;
1374 smac_info->candidate_vlan_index = vidx;
1375 smac_info->candidate_vlan_port = port;
1376 smac_info->update_vid = 1;
1377 path->vlan_index = vidx;
1378 }
1379 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1380 path->fl = 1 << 6;
1381 } else {
1382 /* have current vlan tag. unregister it at modify-qp success */
1383 if (smac_info->vid < 0x1000) {
1384 smac_info->candidate_vid = 0xFFFF;
1385 smac_info->update_vid = 1;
1386 }
1387 }
1388
1389 /* get smac_index for RoCE use.
1390 * If no smac was yet assigned, register one.
1391 * If one was already assigned, but the new mac differs,
1392 * unregister the old one and register the new one.
1393 */
1394 if ((!smac_info->smac && !smac_info->smac_port) ||
1395 smac_info->smac != smac) {
1396 /* register candidate now, unreg if needed, after success */
1397 smac_index = mlx4_register_mac(dev->dev, port, smac);
1398 if (smac_index >= 0) {
1399 smac_info->candidate_smac_index = smac_index;
1400 smac_info->candidate_smac = smac;
1401 smac_info->candidate_smac_port = port;
1402 } else {
1403 return -EINVAL;
1404 }
1405 } else {
1406 smac_index = smac_info->smac_index;
1407 }
1408
1409 memcpy(path->dmac, ah->dmac, 6);
1410 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1411 /* put MAC table smac index for IBoE */
1412 path->grh_mylmc = (u8) (smac_index) | 0x80;
1413 } else {
1414 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1415 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1416 }
1417
1418 return 0;
1419 }
1420
mlx4_set_path(struct mlx4_ib_dev * dev,const struct ib_qp_attr * qp,enum ib_qp_attr_mask qp_attr_mask,struct mlx4_ib_qp * mqp,struct mlx4_qp_path * path,u8 port,u16 vlan_id,u8 * smac)1421 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1422 enum ib_qp_attr_mask qp_attr_mask,
1423 struct mlx4_ib_qp *mqp,
1424 struct mlx4_qp_path *path, u8 port,
1425 u16 vlan_id, u8 *smac)
1426 {
1427 return _mlx4_set_path(dev, &qp->ah_attr,
1428 mlx4_mac_to_u64(smac),
1429 vlan_id,
1430 path, &mqp->pri, port);
1431 }
1432
mlx4_set_alt_path(struct mlx4_ib_dev * dev,const struct ib_qp_attr * qp,enum ib_qp_attr_mask qp_attr_mask,struct mlx4_ib_qp * mqp,struct mlx4_qp_path * path,u8 port)1433 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1434 const struct ib_qp_attr *qp,
1435 enum ib_qp_attr_mask qp_attr_mask,
1436 struct mlx4_ib_qp *mqp,
1437 struct mlx4_qp_path *path, u8 port)
1438 {
1439 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1440 0,
1441 0xffff,
1442 path, &mqp->alt, port);
1443 }
1444
update_mcg_macs(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)1445 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1446 {
1447 struct mlx4_ib_gid_entry *ge, *tmp;
1448
1449 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1450 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1451 ge->added = 1;
1452 ge->port = qp->port;
1453 }
1454 }
1455 }
1456
handle_eth_ud_smac_index(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp,struct mlx4_qp_context * context)1457 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1458 struct mlx4_ib_qp *qp,
1459 struct mlx4_qp_context *context)
1460 {
1461 u64 u64_mac;
1462 int smac_index;
1463
1464 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1465
1466 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1467 if (!qp->pri.smac && !qp->pri.smac_port) {
1468 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1469 if (smac_index >= 0) {
1470 qp->pri.candidate_smac_index = smac_index;
1471 qp->pri.candidate_smac = u64_mac;
1472 qp->pri.candidate_smac_port = qp->port;
1473 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1474 } else {
1475 return -ENOENT;
1476 }
1477 }
1478 return 0;
1479 }
1480
create_qp_lb_counter(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)1481 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1482 {
1483 struct counter_index *new_counter_index;
1484 int err;
1485 u32 tmp_idx;
1486
1487 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1488 IB_LINK_LAYER_ETHERNET ||
1489 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1490 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1491 return 0;
1492
1493 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1494 if (err)
1495 return err;
1496
1497 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1498 if (!new_counter_index) {
1499 mlx4_counter_free(dev->dev, tmp_idx);
1500 return -ENOMEM;
1501 }
1502
1503 new_counter_index->index = tmp_idx;
1504 new_counter_index->allocated = 1;
1505 qp->counter_index = new_counter_index;
1506
1507 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1508 list_add_tail(&new_counter_index->list,
1509 &dev->counters_table[qp->port - 1].counters_list);
1510 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1511
1512 return 0;
1513 }
1514
__mlx4_ib_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)1515 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1516 const struct ib_qp_attr *attr, int attr_mask,
1517 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1518 {
1519 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1520 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1521 struct mlx4_ib_pd *pd;
1522 struct mlx4_ib_cq *send_cq, *recv_cq;
1523 struct mlx4_qp_context *context;
1524 enum mlx4_qp_optpar optpar = 0;
1525 int sqd_event;
1526 int steer_qp = 0;
1527 int err = -EINVAL;
1528 int counter_index;
1529
1530 /* APM is not supported under RoCE */
1531 if (attr_mask & IB_QP_ALT_PATH &&
1532 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1533 IB_LINK_LAYER_ETHERNET)
1534 return -ENOTSUPP;
1535
1536 context = kzalloc(sizeof *context, GFP_KERNEL);
1537 if (!context)
1538 return -ENOMEM;
1539
1540 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1541 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1542
1543 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1544 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1545 else {
1546 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1547 switch (attr->path_mig_state) {
1548 case IB_MIG_MIGRATED:
1549 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1550 break;
1551 case IB_MIG_REARM:
1552 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1553 break;
1554 case IB_MIG_ARMED:
1555 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1556 break;
1557 }
1558 }
1559
1560 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1561 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1562 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1563 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1564 else if (ibqp->qp_type == IB_QPT_UD) {
1565 if (qp->flags & MLX4_IB_QP_LSO)
1566 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1567 ilog2(dev->dev->caps.max_gso_sz);
1568 else
1569 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
1570 } else if (attr_mask & IB_QP_PATH_MTU) {
1571 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1572 pr_err("path MTU (%u) is invalid\n",
1573 attr->path_mtu);
1574 goto out;
1575 }
1576 context->mtu_msgmax = (attr->path_mtu << 5) |
1577 ilog2(dev->dev->caps.max_msg_sz);
1578 }
1579
1580 if (qp->rq.wqe_cnt)
1581 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1582 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1583
1584 if (qp->sq.wqe_cnt)
1585 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1586 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1587
1588 if (new_state == IB_QPS_RESET && qp->counter_index)
1589 mlx4_ib_free_qp_counter(dev, qp);
1590
1591 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1592 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1593 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1594 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1595 context->param3 |= cpu_to_be32(1 << 30);
1596 }
1597
1598 if (qp->ibqp.uobject)
1599 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1600 else
1601 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1602
1603 if (attr_mask & IB_QP_DEST_QPN)
1604 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1605
1606 if (attr_mask & IB_QP_PORT) {
1607 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1608 !(attr_mask & IB_QP_AV)) {
1609 mlx4_set_sched(&context->pri_path, attr->port_num);
1610 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1611 }
1612 }
1613
1614 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1615 err = create_qp_lb_counter(dev, qp);
1616 if (err)
1617 goto out;
1618
1619 counter_index =
1620 dev->counters_table[qp->port - 1].default_counter;
1621 if (qp->counter_index)
1622 counter_index = qp->counter_index->index;
1623
1624 if (counter_index != -1) {
1625 context->pri_path.counter_index = counter_index;
1626 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1627 if (qp->counter_index) {
1628 context->pri_path.fl |=
1629 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1630 context->pri_path.vlan_control |=
1631 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1632 }
1633 } else
1634 context->pri_path.counter_index =
1635 MLX4_SINK_COUNTER_INDEX(dev->dev);
1636
1637 if (qp->flags & MLX4_IB_QP_NETIF) {
1638 mlx4_ib_steer_qp_reg(dev, qp, 1);
1639 steer_qp = 1;
1640 }
1641 }
1642
1643 if (attr_mask & IB_QP_PKEY_INDEX) {
1644 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1645 context->pri_path.disable_pkey_check = 0x40;
1646 context->pri_path.pkey_index = attr->pkey_index;
1647 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1648 }
1649
1650 if (attr_mask & IB_QP_AV) {
1651 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1652 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1653 union ib_gid gid;
1654 struct ib_gid_attr gid_attr;
1655 u16 vlan = 0xffff;
1656 u8 smac[ETH_ALEN];
1657 int status = 0;
1658
1659 if (rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1660 attr->ah_attr.ah_flags & IB_AH_GRH) {
1661 int index = attr->ah_attr.grh.sgid_index;
1662
1663 status = ib_get_cached_gid(ibqp->device, port_num,
1664 index, &gid, &gid_attr);
1665 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1666 status = -ENOENT;
1667 if (!status && gid_attr.ndev) {
1668 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1669 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1670 dev_put(gid_attr.ndev);
1671 }
1672 }
1673 if (status)
1674 goto out;
1675
1676 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1677 port_num, vlan, smac))
1678 goto out;
1679
1680 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1681 MLX4_QP_OPTPAR_SCHED_QUEUE);
1682 }
1683
1684 if (attr_mask & IB_QP_TIMEOUT) {
1685 context->pri_path.ackto |= attr->timeout << 3;
1686 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1687 }
1688
1689 if (attr_mask & IB_QP_ALT_PATH) {
1690 if (attr->alt_port_num == 0 ||
1691 attr->alt_port_num > dev->dev->caps.num_ports)
1692 goto out;
1693
1694 if (attr->alt_pkey_index >=
1695 dev->dev->caps.pkey_table_len[attr->alt_port_num])
1696 goto out;
1697
1698 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1699 &context->alt_path,
1700 attr->alt_port_num))
1701 goto out;
1702
1703 context->alt_path.pkey_index = attr->alt_pkey_index;
1704 context->alt_path.ackto = attr->alt_timeout << 3;
1705 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1706 }
1707
1708 pd = get_pd(qp);
1709 get_cqs(qp, &send_cq, &recv_cq);
1710 context->pd = cpu_to_be32(pd->pdn);
1711 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1712 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1713 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1714
1715 /* Set "fast registration enabled" for all kernel QPs */
1716 if (!qp->ibqp.uobject)
1717 context->params1 |= cpu_to_be32(1 << 11);
1718
1719 if (attr_mask & IB_QP_RNR_RETRY) {
1720 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1721 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1722 }
1723
1724 if (attr_mask & IB_QP_RETRY_CNT) {
1725 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1726 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1727 }
1728
1729 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1730 if (attr->max_rd_atomic)
1731 context->params1 |=
1732 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1733 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1734 }
1735
1736 if (attr_mask & IB_QP_SQ_PSN)
1737 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1738
1739 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1740 if (attr->max_dest_rd_atomic)
1741 context->params2 |=
1742 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1743 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1744 }
1745
1746 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1747 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1748 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1749 }
1750
1751 if (ibqp->srq)
1752 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1753
1754 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1755 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1756 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1757 }
1758 if (attr_mask & IB_QP_RQ_PSN)
1759 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1760
1761 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1762 if (attr_mask & IB_QP_QKEY) {
1763 if (qp->mlx4_ib_qp_type &
1764 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1765 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1766 else {
1767 if (mlx4_is_mfunc(dev->dev) &&
1768 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1769 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1770 MLX4_RESERVED_QKEY_BASE) {
1771 pr_err("Cannot use reserved QKEY"
1772 " 0x%x (range 0xffff0000..0xffffffff"
1773 " is reserved)\n", attr->qkey);
1774 err = -EINVAL;
1775 goto out;
1776 }
1777 context->qkey = cpu_to_be32(attr->qkey);
1778 }
1779 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1780 }
1781
1782 if (ibqp->srq)
1783 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1784
1785 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1786 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1787
1788 if (cur_state == IB_QPS_INIT &&
1789 new_state == IB_QPS_RTR &&
1790 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1791 ibqp->qp_type == IB_QPT_UD ||
1792 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1793 context->pri_path.sched_queue = (qp->port - 1) << 6;
1794 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1795 qp->mlx4_ib_qp_type &
1796 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1797 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1798 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1799 context->pri_path.fl = 0x80;
1800 } else {
1801 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1802 context->pri_path.fl = 0x80;
1803 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1804 }
1805 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1806 IB_LINK_LAYER_ETHERNET) {
1807 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1808 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1809 context->pri_path.feup = 1 << 7; /* don't fsm */
1810 /* handle smac_index */
1811 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1812 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1813 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1814 err = handle_eth_ud_smac_index(dev, qp, context);
1815 if (err) {
1816 err = -EINVAL;
1817 goto out;
1818 }
1819 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1820 dev->qp1_proxy[qp->port - 1] = qp;
1821 }
1822 }
1823 }
1824
1825 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1826 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1827 MLX4_IB_LINK_TYPE_ETH;
1828 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1829 /* set QP to receive both tunneled & non-tunneled packets */
1830 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1831 context->srqn = cpu_to_be32(7 << 28);
1832 }
1833 }
1834
1835 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1836 int is_eth = rdma_port_get_link_layer(
1837 &dev->ib_dev, qp->port) ==
1838 IB_LINK_LAYER_ETHERNET;
1839 if (is_eth) {
1840 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1841 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1842 }
1843 }
1844
1845
1846 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1847 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1848 sqd_event = 1;
1849 else
1850 sqd_event = 0;
1851
1852 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1853 context->rlkey |= (1 << 4);
1854
1855 /*
1856 * Before passing a kernel QP to the HW, make sure that the
1857 * ownership bits of the send queue are set and the SQ
1858 * headroom is stamped so that the hardware doesn't start
1859 * processing stale work requests.
1860 */
1861 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1862 struct mlx4_wqe_ctrl_seg *ctrl;
1863 int i;
1864
1865 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1866 ctrl = get_send_wqe(qp, i);
1867 ctrl->owner_opcode = cpu_to_be32(1 << 31);
1868 if (qp->sq_max_wqes_per_wr == 1)
1869 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1870
1871 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1872 }
1873 }
1874
1875 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1876 to_mlx4_state(new_state), context, optpar,
1877 sqd_event, &qp->mqp);
1878 if (err)
1879 goto out;
1880
1881 qp->state = new_state;
1882
1883 if (attr_mask & IB_QP_ACCESS_FLAGS)
1884 qp->atomic_rd_en = attr->qp_access_flags;
1885 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1886 qp->resp_depth = attr->max_dest_rd_atomic;
1887 if (attr_mask & IB_QP_PORT) {
1888 qp->port = attr->port_num;
1889 update_mcg_macs(dev, qp);
1890 }
1891 if (attr_mask & IB_QP_ALT_PATH)
1892 qp->alt_port = attr->alt_port_num;
1893
1894 if (is_sqp(dev, qp))
1895 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1896
1897 /*
1898 * If we moved QP0 to RTR, bring the IB link up; if we moved
1899 * QP0 to RESET or ERROR, bring the link back down.
1900 */
1901 if (is_qp0(dev, qp)) {
1902 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1903 if (mlx4_INIT_PORT(dev->dev, qp->port))
1904 pr_warn("INIT_PORT failed for port %d\n",
1905 qp->port);
1906
1907 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1908 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1909 mlx4_CLOSE_PORT(dev->dev, qp->port);
1910 }
1911
1912 /*
1913 * If we moved a kernel QP to RESET, clean up all old CQ
1914 * entries and reinitialize the QP.
1915 */
1916 if (new_state == IB_QPS_RESET) {
1917 if (!ibqp->uobject) {
1918 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1919 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1920 if (send_cq != recv_cq)
1921 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1922
1923 qp->rq.head = 0;
1924 qp->rq.tail = 0;
1925 qp->sq.head = 0;
1926 qp->sq.tail = 0;
1927 qp->sq_next_wqe = 0;
1928 if (qp->rq.wqe_cnt)
1929 *qp->db.db = 0;
1930
1931 if (qp->flags & MLX4_IB_QP_NETIF)
1932 mlx4_ib_steer_qp_reg(dev, qp, 0);
1933 }
1934 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1935 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1936 qp->pri.smac = 0;
1937 qp->pri.smac_port = 0;
1938 }
1939 if (qp->alt.smac) {
1940 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1941 qp->alt.smac = 0;
1942 }
1943 if (qp->pri.vid < 0x1000) {
1944 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1945 qp->pri.vid = 0xFFFF;
1946 qp->pri.candidate_vid = 0xFFFF;
1947 qp->pri.update_vid = 0;
1948 }
1949
1950 if (qp->alt.vid < 0x1000) {
1951 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1952 qp->alt.vid = 0xFFFF;
1953 qp->alt.candidate_vid = 0xFFFF;
1954 qp->alt.update_vid = 0;
1955 }
1956 }
1957 out:
1958 if (err && qp->counter_index)
1959 mlx4_ib_free_qp_counter(dev, qp);
1960 if (err && steer_qp)
1961 mlx4_ib_steer_qp_reg(dev, qp, 0);
1962 kfree(context);
1963 if (qp->pri.candidate_smac ||
1964 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
1965 if (err) {
1966 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1967 } else {
1968 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
1969 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1970 qp->pri.smac = qp->pri.candidate_smac;
1971 qp->pri.smac_index = qp->pri.candidate_smac_index;
1972 qp->pri.smac_port = qp->pri.candidate_smac_port;
1973 }
1974 qp->pri.candidate_smac = 0;
1975 qp->pri.candidate_smac_index = 0;
1976 qp->pri.candidate_smac_port = 0;
1977 }
1978 if (qp->alt.candidate_smac) {
1979 if (err) {
1980 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1981 } else {
1982 if (qp->alt.smac)
1983 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1984 qp->alt.smac = qp->alt.candidate_smac;
1985 qp->alt.smac_index = qp->alt.candidate_smac_index;
1986 qp->alt.smac_port = qp->alt.candidate_smac_port;
1987 }
1988 qp->alt.candidate_smac = 0;
1989 qp->alt.candidate_smac_index = 0;
1990 qp->alt.candidate_smac_port = 0;
1991 }
1992
1993 if (qp->pri.update_vid) {
1994 if (err) {
1995 if (qp->pri.candidate_vid < 0x1000)
1996 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1997 qp->pri.candidate_vid);
1998 } else {
1999 if (qp->pri.vid < 0x1000)
2000 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2001 qp->pri.vid);
2002 qp->pri.vid = qp->pri.candidate_vid;
2003 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2004 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2005 }
2006 qp->pri.candidate_vid = 0xFFFF;
2007 qp->pri.update_vid = 0;
2008 }
2009
2010 if (qp->alt.update_vid) {
2011 if (err) {
2012 if (qp->alt.candidate_vid < 0x1000)
2013 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2014 qp->alt.candidate_vid);
2015 } else {
2016 if (qp->alt.vid < 0x1000)
2017 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2018 qp->alt.vid);
2019 qp->alt.vid = qp->alt.candidate_vid;
2020 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2021 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2022 }
2023 qp->alt.candidate_vid = 0xFFFF;
2024 qp->alt.update_vid = 0;
2025 }
2026
2027 return err;
2028 }
2029
mlx4_ib_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)2030 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2031 int attr_mask, struct ib_udata *udata)
2032 {
2033 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2034 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2035 enum ib_qp_state cur_state, new_state;
2036 int err = -EINVAL;
2037 int ll;
2038 mutex_lock(&qp->mutex);
2039
2040 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2041 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2042
2043 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2044 ll = IB_LINK_LAYER_UNSPECIFIED;
2045 } else {
2046 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2047 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2048 }
2049
2050 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2051 attr_mask, ll)) {
2052 pr_debug("qpn 0x%x: invalid attribute mask specified "
2053 "for transition %d to %d. qp_type %d,"
2054 " attr_mask 0x%x\n",
2055 ibqp->qp_num, cur_state, new_state,
2056 ibqp->qp_type, attr_mask);
2057 goto out;
2058 }
2059
2060 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2061 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2062 if ((ibqp->qp_type == IB_QPT_RC) ||
2063 (ibqp->qp_type == IB_QPT_UD) ||
2064 (ibqp->qp_type == IB_QPT_UC) ||
2065 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2066 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2067 attr->port_num = mlx4_ib_bond_next_port(dev);
2068 }
2069 } else {
2070 /* no sense in changing port_num
2071 * when ports are bonded */
2072 attr_mask &= ~IB_QP_PORT;
2073 }
2074 }
2075
2076 if ((attr_mask & IB_QP_PORT) &&
2077 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2078 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2079 "for transition %d to %d. qp_type %d\n",
2080 ibqp->qp_num, attr->port_num, cur_state,
2081 new_state, ibqp->qp_type);
2082 goto out;
2083 }
2084
2085 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2086 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2087 IB_LINK_LAYER_ETHERNET))
2088 goto out;
2089
2090 if (attr_mask & IB_QP_PKEY_INDEX) {
2091 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2092 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2093 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2094 "for transition %d to %d. qp_type %d\n",
2095 ibqp->qp_num, attr->pkey_index, cur_state,
2096 new_state, ibqp->qp_type);
2097 goto out;
2098 }
2099 }
2100
2101 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2102 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2103 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2104 "Transition %d to %d. qp_type %d\n",
2105 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2106 new_state, ibqp->qp_type);
2107 goto out;
2108 }
2109
2110 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2111 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2112 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2113 "Transition %d to %d. qp_type %d\n",
2114 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2115 new_state, ibqp->qp_type);
2116 goto out;
2117 }
2118
2119 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2120 err = 0;
2121 goto out;
2122 }
2123
2124 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2125
2126 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2127 attr->port_num = 1;
2128
2129 out:
2130 mutex_unlock(&qp->mutex);
2131 return err;
2132 }
2133
vf_get_qp0_qkey(struct mlx4_dev * dev,int qpn,u32 * qkey)2134 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2135 {
2136 int i;
2137 for (i = 0; i < dev->caps.num_ports; i++) {
2138 if (qpn == dev->caps.qp0_proxy[i] ||
2139 qpn == dev->caps.qp0_tunnel[i]) {
2140 *qkey = dev->caps.qp0_qkey[i];
2141 return 0;
2142 }
2143 }
2144 return -EINVAL;
2145 }
2146
build_sriov_qp0_header(struct mlx4_ib_sqp * sqp,struct ib_ud_wr * wr,void * wqe,unsigned * mlx_seg_len)2147 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2148 struct ib_ud_wr *wr,
2149 void *wqe, unsigned *mlx_seg_len)
2150 {
2151 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2152 struct ib_device *ib_dev = &mdev->ib_dev;
2153 struct mlx4_wqe_mlx_seg *mlx = wqe;
2154 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2155 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2156 u16 pkey;
2157 u32 qkey;
2158 int send_size;
2159 int header_size;
2160 int spc;
2161 int err;
2162 int i;
2163
2164 if (wr->wr.opcode != IB_WR_SEND)
2165 return -EINVAL;
2166
2167 send_size = 0;
2168
2169 for (i = 0; i < wr->wr.num_sge; ++i)
2170 send_size += wr->wr.sg_list[i].length;
2171
2172 /* for proxy-qp0 sends, need to add in size of tunnel header */
2173 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2174 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2175 send_size += sizeof (struct mlx4_ib_tunnel_header);
2176
2177 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2178
2179 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2180 sqp->ud_header.lrh.service_level =
2181 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2182 sqp->ud_header.lrh.destination_lid =
2183 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2184 sqp->ud_header.lrh.source_lid =
2185 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2186 }
2187
2188 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2189
2190 /* force loopback */
2191 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2192 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2193
2194 sqp->ud_header.lrh.virtual_lane = 0;
2195 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2196 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2197 if (err)
2198 return err;
2199 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2200 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2201 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2202 else
2203 sqp->ud_header.bth.destination_qpn =
2204 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2205
2206 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2207 if (mlx4_is_master(mdev->dev)) {
2208 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2209 return -EINVAL;
2210 } else {
2211 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2212 return -EINVAL;
2213 }
2214 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2215 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2216
2217 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2218 sqp->ud_header.immediate_present = 0;
2219
2220 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2221
2222 /*
2223 * Inline data segments may not cross a 64 byte boundary. If
2224 * our UD header is bigger than the space available up to the
2225 * next 64 byte boundary in the WQE, use two inline data
2226 * segments to hold the UD header.
2227 */
2228 spc = MLX4_INLINE_ALIGN -
2229 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2230 if (header_size <= spc) {
2231 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2232 memcpy(inl + 1, sqp->header_buf, header_size);
2233 i = 1;
2234 } else {
2235 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2236 memcpy(inl + 1, sqp->header_buf, spc);
2237
2238 inl = (void *) (inl + 1) + spc;
2239 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2240 /*
2241 * Need a barrier here to make sure all the data is
2242 * visible before the byte_count field is set.
2243 * Otherwise the HCA prefetcher could grab the 64-byte
2244 * chunk with this inline segment and get a valid (!=
2245 * 0xffffffff) byte count but stale data, and end up
2246 * generating a packet with bad headers.
2247 *
2248 * The first inline segment's byte_count field doesn't
2249 * need a barrier, because it comes after a
2250 * control/MLX segment and therefore is at an offset
2251 * of 16 mod 64.
2252 */
2253 wmb();
2254 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2255 i = 2;
2256 }
2257
2258 *mlx_seg_len =
2259 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2260 return 0;
2261 }
2262
mlx4_u64_to_smac(u8 * dst_mac,u64 src_mac)2263 static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2264 {
2265 int i;
2266
2267 for (i = ETH_ALEN; i; i--) {
2268 dst_mac[i - 1] = src_mac & 0xff;
2269 src_mac >>= 8;
2270 }
2271 }
2272
build_mlx_header(struct mlx4_ib_sqp * sqp,struct ib_ud_wr * wr,void * wqe,unsigned * mlx_seg_len)2273 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
2274 void *wqe, unsigned *mlx_seg_len)
2275 {
2276 struct ib_device *ib_dev = sqp->qp.ibqp.device;
2277 struct mlx4_wqe_mlx_seg *mlx = wqe;
2278 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2279 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2280 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2281 union ib_gid sgid;
2282 u16 pkey;
2283 int send_size;
2284 int header_size;
2285 int spc;
2286 int i;
2287 int err = 0;
2288 u16 vlan = 0xffff;
2289 bool is_eth;
2290 bool is_vlan = false;
2291 bool is_grh;
2292
2293 send_size = 0;
2294 for (i = 0; i < wr->wr.num_sge; ++i)
2295 send_size += wr->wr.sg_list[i].length;
2296
2297 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2298 is_grh = mlx4_ib_ah_grh_present(ah);
2299 if (is_eth) {
2300 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2301 /* When multi-function is enabled, the ib_core gid
2302 * indexes don't necessarily match the hw ones, so
2303 * we must use our own cache */
2304 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2305 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2306 ah->av.ib.gid_index, &sgid.raw[0]);
2307 if (err)
2308 return err;
2309 } else {
2310 err = ib_get_cached_gid(ib_dev,
2311 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2312 ah->av.ib.gid_index, &sgid,
2313 NULL);
2314 if (!err && !memcmp(&sgid, &zgid, sizeof(sgid)))
2315 err = -ENOENT;
2316 if (err)
2317 return err;
2318 }
2319
2320 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2321 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2322 is_vlan = 1;
2323 }
2324 }
2325 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2326
2327 if (!is_eth) {
2328 sqp->ud_header.lrh.service_level =
2329 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2330 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2331 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2332 }
2333
2334 if (is_grh) {
2335 sqp->ud_header.grh.traffic_class =
2336 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2337 sqp->ud_header.grh.flow_label =
2338 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2339 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
2340 if (is_eth) {
2341 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2342 } else {
2343 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2344 /* When multi-function is enabled, the ib_core gid
2345 * indexes don't necessarily match the hw ones, so
2346 * we must use our own cache
2347 */
2348 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2349 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
2350 demux[sqp->qp.port - 1].
2351 subnet_prefix)));
2352 sqp->ud_header.grh.source_gid.global.interface_id =
2353 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2354 guid_cache[ah->av.ib.gid_index];
2355 } else {
2356 ib_get_cached_gid(ib_dev,
2357 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2358 ah->av.ib.gid_index,
2359 &sqp->ud_header.grh.source_gid, NULL);
2360 }
2361 }
2362 memcpy(sqp->ud_header.grh.destination_gid.raw,
2363 ah->av.ib.dgid, 16);
2364 }
2365
2366 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2367
2368 if (!is_eth) {
2369 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2370 (sqp->ud_header.lrh.destination_lid ==
2371 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2372 (sqp->ud_header.lrh.service_level << 8));
2373 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2374 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2375 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2376 }
2377
2378 switch (wr->wr.opcode) {
2379 case IB_WR_SEND:
2380 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2381 sqp->ud_header.immediate_present = 0;
2382 break;
2383 case IB_WR_SEND_WITH_IMM:
2384 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2385 sqp->ud_header.immediate_present = 1;
2386 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
2387 break;
2388 default:
2389 return -EINVAL;
2390 }
2391
2392 if (is_eth) {
2393 struct in6_addr in6;
2394
2395 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2396
2397 mlx->sched_prio = cpu_to_be16(pcp);
2398
2399 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2400 /* FIXME: cache smac value? */
2401 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2402 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2403 memcpy(&in6, sgid.raw, sizeof(in6));
2404
2405 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2406 u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2407 u8 smac[ETH_ALEN];
2408
2409 mlx4_u64_to_smac(smac, mac);
2410 memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2411 } else {
2412 /* use the src mac of the tunnel */
2413 memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2414 }
2415
2416 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2417 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2418 if (!is_vlan) {
2419 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2420 } else {
2421 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2422 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2423 }
2424 } else {
2425 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2426 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2427 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2428 }
2429 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2430 if (!sqp->qp.ibqp.qp_num)
2431 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index,
2432 &pkey);
2433 else
2434 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index,
2435 &pkey);
2436 if (err)
2437 return err;
2438
2439 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2440 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2441 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2442 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2443 sqp->qkey : wr->remote_qkey);
2444 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2445
2446 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2447
2448 if (0) {
2449 pr_err("built UD header of size %d:\n", header_size);
2450 for (i = 0; i < header_size / 4; ++i) {
2451 if (i % 8 == 0)
2452 pr_err(" [%02x] ", i * 4);
2453 pr_cont(" %08x",
2454 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2455 if ((i + 1) % 8 == 0)
2456 pr_cont("\n");
2457 }
2458 pr_err("\n");
2459 }
2460
2461 /*
2462 * Inline data segments may not cross a 64 byte boundary. If
2463 * our UD header is bigger than the space available up to the
2464 * next 64 byte boundary in the WQE, use two inline data
2465 * segments to hold the UD header.
2466 */
2467 spc = MLX4_INLINE_ALIGN -
2468 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2469 if (header_size <= spc) {
2470 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2471 memcpy(inl + 1, sqp->header_buf, header_size);
2472 i = 1;
2473 } else {
2474 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2475 memcpy(inl + 1, sqp->header_buf, spc);
2476
2477 inl = (void *) (inl + 1) + spc;
2478 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2479 /*
2480 * Need a barrier here to make sure all the data is
2481 * visible before the byte_count field is set.
2482 * Otherwise the HCA prefetcher could grab the 64-byte
2483 * chunk with this inline segment and get a valid (!=
2484 * 0xffffffff) byte count but stale data, and end up
2485 * generating a packet with bad headers.
2486 *
2487 * The first inline segment's byte_count field doesn't
2488 * need a barrier, because it comes after a
2489 * control/MLX segment and therefore is at an offset
2490 * of 16 mod 64.
2491 */
2492 wmb();
2493 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2494 i = 2;
2495 }
2496
2497 *mlx_seg_len =
2498 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2499 return 0;
2500 }
2501
mlx4_wq_overflow(struct mlx4_ib_wq * wq,int nreq,struct ib_cq * ib_cq)2502 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2503 {
2504 unsigned cur;
2505 struct mlx4_ib_cq *cq;
2506
2507 cur = wq->head - wq->tail;
2508 if (likely(cur + nreq < wq->max_post))
2509 return 0;
2510
2511 cq = to_mcq(ib_cq);
2512 spin_lock(&cq->lock);
2513 cur = wq->head - wq->tail;
2514 spin_unlock(&cq->lock);
2515
2516 return cur + nreq >= wq->max_post;
2517 }
2518
convert_access(int acc)2519 static __be32 convert_access(int acc)
2520 {
2521 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2522 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2523 (acc & IB_ACCESS_REMOTE_WRITE ?
2524 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2525 (acc & IB_ACCESS_REMOTE_READ ?
2526 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
2527 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2528 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2529 }
2530
set_reg_seg(struct mlx4_wqe_fmr_seg * fseg,struct ib_reg_wr * wr)2531 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2532 struct ib_reg_wr *wr)
2533 {
2534 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2535
2536 fseg->flags = convert_access(wr->access);
2537 fseg->mem_key = cpu_to_be32(wr->key);
2538 fseg->buf_list = cpu_to_be64(mr->page_map);
2539 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2540 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2541 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2542 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2543 fseg->reserved[0] = 0;
2544 fseg->reserved[1] = 0;
2545 }
2546
set_bind_seg(struct mlx4_wqe_bind_seg * bseg,struct ib_bind_mw_wr * wr)2547 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg,
2548 struct ib_bind_mw_wr *wr)
2549 {
2550 bseg->flags1 =
2551 convert_access(wr->bind_info.mw_access_flags) &
2552 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ |
2553 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2554 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2555 bseg->flags2 = 0;
2556 if (wr->mw->type == IB_MW_TYPE_2)
2557 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2558 if (wr->bind_info.mw_access_flags & IB_ZERO_BASED)
2559 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2560 bseg->new_rkey = cpu_to_be32(wr->rkey);
2561 bseg->lkey = cpu_to_be32(wr->bind_info.mr->lkey);
2562 bseg->addr = cpu_to_be64(wr->bind_info.addr);
2563 bseg->length = cpu_to_be64(wr->bind_info.length);
2564 }
2565
set_local_inv_seg(struct mlx4_wqe_local_inval_seg * iseg,u32 rkey)2566 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2567 {
2568 memset(iseg, 0, sizeof(*iseg));
2569 iseg->mem_key = cpu_to_be32(rkey);
2570 }
2571
set_raddr_seg(struct mlx4_wqe_raddr_seg * rseg,u64 remote_addr,u32 rkey)2572 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2573 u64 remote_addr, u32 rkey)
2574 {
2575 rseg->raddr = cpu_to_be64(remote_addr);
2576 rseg->rkey = cpu_to_be32(rkey);
2577 rseg->reserved = 0;
2578 }
2579
set_atomic_seg(struct mlx4_wqe_atomic_seg * aseg,struct ib_atomic_wr * wr)2580 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2581 struct ib_atomic_wr *wr)
2582 {
2583 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2584 aseg->swap_add = cpu_to_be64(wr->swap);
2585 aseg->compare = cpu_to_be64(wr->compare_add);
2586 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2587 aseg->swap_add = cpu_to_be64(wr->compare_add);
2588 aseg->compare = cpu_to_be64(wr->compare_add_mask);
2589 } else {
2590 aseg->swap_add = cpu_to_be64(wr->compare_add);
2591 aseg->compare = 0;
2592 }
2593
2594 }
2595
set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg * aseg,struct ib_atomic_wr * wr)2596 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2597 struct ib_atomic_wr *wr)
2598 {
2599 aseg->swap_add = cpu_to_be64(wr->swap);
2600 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2601 aseg->compare = cpu_to_be64(wr->compare_add);
2602 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
2603 }
2604
set_datagram_seg(struct mlx4_wqe_datagram_seg * dseg,struct ib_ud_wr * wr)2605 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2606 struct ib_ud_wr *wr)
2607 {
2608 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2609 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2610 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2611 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2612 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
2613 }
2614
set_tunnel_datagram_seg(struct mlx4_ib_dev * dev,struct mlx4_wqe_datagram_seg * dseg,struct ib_ud_wr * wr,enum mlx4_ib_qp_type qpt)2615 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2616 struct mlx4_wqe_datagram_seg *dseg,
2617 struct ib_ud_wr *wr,
2618 enum mlx4_ib_qp_type qpt)
2619 {
2620 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
2621 struct mlx4_av sqp_av = {0};
2622 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2623
2624 /* force loopback */
2625 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2626 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2627 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2628 cpu_to_be32(0xf0000000);
2629
2630 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2631 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2632 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2633 else
2634 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2635 /* Use QKEY from the QP context, which is set by master */
2636 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2637 }
2638
build_tunnel_header(struct ib_ud_wr * wr,void * wqe,unsigned * mlx_seg_len)2639 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
2640 {
2641 struct mlx4_wqe_inline_seg *inl = wqe;
2642 struct mlx4_ib_tunnel_header hdr;
2643 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2644 int spc;
2645 int i;
2646
2647 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2648 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2649 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2650 hdr.qkey = cpu_to_be32(wr->remote_qkey);
2651 memcpy(hdr.mac, ah->av.eth.mac, 6);
2652 hdr.vlan = ah->av.eth.vlan;
2653
2654 spc = MLX4_INLINE_ALIGN -
2655 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2656 if (sizeof (hdr) <= spc) {
2657 memcpy(inl + 1, &hdr, sizeof (hdr));
2658 wmb();
2659 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2660 i = 1;
2661 } else {
2662 memcpy(inl + 1, &hdr, spc);
2663 wmb();
2664 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2665
2666 inl = (void *) (inl + 1) + spc;
2667 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2668 wmb();
2669 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2670 i = 2;
2671 }
2672
2673 *mlx_seg_len =
2674 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2675 }
2676
set_mlx_icrc_seg(void * dseg)2677 static void set_mlx_icrc_seg(void *dseg)
2678 {
2679 u32 *t = dseg;
2680 struct mlx4_wqe_inline_seg *iseg = dseg;
2681
2682 t[1] = 0;
2683
2684 /*
2685 * Need a barrier here before writing the byte_count field to
2686 * make sure that all the data is visible before the
2687 * byte_count field is set. Otherwise, if the segment begins
2688 * a new cacheline, the HCA prefetcher could grab the 64-byte
2689 * chunk and get a valid (!= * 0xffffffff) byte count but
2690 * stale data, and end up sending the wrong data.
2691 */
2692 wmb();
2693
2694 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2695 }
2696
set_data_seg(struct mlx4_wqe_data_seg * dseg,struct ib_sge * sg)2697 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2698 {
2699 dseg->lkey = cpu_to_be32(sg->lkey);
2700 dseg->addr = cpu_to_be64(sg->addr);
2701
2702 /*
2703 * Need a barrier here before writing the byte_count field to
2704 * make sure that all the data is visible before the
2705 * byte_count field is set. Otherwise, if the segment begins
2706 * a new cacheline, the HCA prefetcher could grab the 64-byte
2707 * chunk and get a valid (!= * 0xffffffff) byte count but
2708 * stale data, and end up sending the wrong data.
2709 */
2710 wmb();
2711
2712 dseg->byte_count = cpu_to_be32(sg->length);
2713 }
2714
__set_data_seg(struct mlx4_wqe_data_seg * dseg,struct ib_sge * sg)2715 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2716 {
2717 dseg->byte_count = cpu_to_be32(sg->length);
2718 dseg->lkey = cpu_to_be32(sg->lkey);
2719 dseg->addr = cpu_to_be64(sg->addr);
2720 }
2721
build_lso_seg(struct mlx4_wqe_lso_seg * wqe,struct ib_ud_wr * wr,struct mlx4_ib_qp * qp,unsigned * lso_seg_len,__be32 * lso_hdr_sz,__be32 * blh)2722 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
2723 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2724 __be32 *lso_hdr_sz, __be32 *blh)
2725 {
2726 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
2727
2728 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2729 *blh = cpu_to_be32(1 << 6);
2730
2731 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2732 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
2733 return -EINVAL;
2734
2735 memcpy(wqe->header, wr->header, wr->hlen);
2736
2737 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
2738 *lso_seg_len = halign;
2739 return 0;
2740 }
2741
send_ieth(struct ib_send_wr * wr)2742 static __be32 send_ieth(struct ib_send_wr *wr)
2743 {
2744 switch (wr->opcode) {
2745 case IB_WR_SEND_WITH_IMM:
2746 case IB_WR_RDMA_WRITE_WITH_IMM:
2747 return wr->ex.imm_data;
2748
2749 case IB_WR_SEND_WITH_INV:
2750 return cpu_to_be32(wr->ex.invalidate_rkey);
2751
2752 default:
2753 return 0;
2754 }
2755 }
2756
add_zero_len_inline(void * wqe)2757 static void add_zero_len_inline(void *wqe)
2758 {
2759 struct mlx4_wqe_inline_seg *inl = wqe;
2760 memset(wqe, 0, 16);
2761 inl->byte_count = cpu_to_be32(1 << 31);
2762 }
2763
mlx4_ib_post_send(struct ib_qp * ibqp,struct ib_send_wr * wr,struct ib_send_wr ** bad_wr)2764 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2765 struct ib_send_wr **bad_wr)
2766 {
2767 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2768 void *wqe;
2769 struct mlx4_wqe_ctrl_seg *ctrl;
2770 struct mlx4_wqe_data_seg *dseg;
2771 unsigned long flags;
2772 int nreq;
2773 int err = 0;
2774 unsigned ind;
2775 int uninitialized_var(stamp);
2776 int uninitialized_var(size);
2777 unsigned uninitialized_var(seglen);
2778 __be32 dummy;
2779 __be32 *lso_wqe;
2780 __be32 uninitialized_var(lso_hdr_sz);
2781 __be32 blh;
2782 int i;
2783 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2784
2785 spin_lock_irqsave(&qp->sq.lock, flags);
2786 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2787 err = -EIO;
2788 *bad_wr = wr;
2789 nreq = 0;
2790 goto out;
2791 }
2792
2793 ind = qp->sq_next_wqe;
2794
2795 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2796 lso_wqe = &dummy;
2797 blh = 0;
2798
2799 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2800 err = -ENOMEM;
2801 *bad_wr = wr;
2802 goto out;
2803 }
2804
2805 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2806 err = -EINVAL;
2807 *bad_wr = wr;
2808 goto out;
2809 }
2810
2811 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2812 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2813
2814 ctrl->srcrb_flags =
2815 (wr->send_flags & IB_SEND_SIGNALED ?
2816 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2817 (wr->send_flags & IB_SEND_SOLICITED ?
2818 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2819 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2820 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2821 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2822 qp->sq_signal_bits;
2823
2824 ctrl->imm = send_ieth(wr);
2825
2826 wqe += sizeof *ctrl;
2827 size = sizeof *ctrl / 16;
2828
2829 switch (qp->mlx4_ib_qp_type) {
2830 case MLX4_IB_QPT_RC:
2831 case MLX4_IB_QPT_UC:
2832 switch (wr->opcode) {
2833 case IB_WR_ATOMIC_CMP_AND_SWP:
2834 case IB_WR_ATOMIC_FETCH_AND_ADD:
2835 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2836 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2837 atomic_wr(wr)->rkey);
2838 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2839
2840 set_atomic_seg(wqe, atomic_wr(wr));
2841 wqe += sizeof (struct mlx4_wqe_atomic_seg);
2842
2843 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2844 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2845
2846 break;
2847
2848 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2849 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2850 atomic_wr(wr)->rkey);
2851 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2852
2853 set_masked_atomic_seg(wqe, atomic_wr(wr));
2854 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2855
2856 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2857 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2858
2859 break;
2860
2861 case IB_WR_RDMA_READ:
2862 case IB_WR_RDMA_WRITE:
2863 case IB_WR_RDMA_WRITE_WITH_IMM:
2864 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2865 rdma_wr(wr)->rkey);
2866 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2867 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2868 break;
2869
2870 case IB_WR_LOCAL_INV:
2871 ctrl->srcrb_flags |=
2872 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2873 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2874 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2875 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2876 break;
2877
2878 case IB_WR_REG_MR:
2879 ctrl->srcrb_flags |=
2880 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2881 set_reg_seg(wqe, reg_wr(wr));
2882 wqe += sizeof(struct mlx4_wqe_fmr_seg);
2883 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
2884 break;
2885
2886 case IB_WR_BIND_MW:
2887 ctrl->srcrb_flags |=
2888 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2889 set_bind_seg(wqe, bind_mw_wr(wr));
2890 wqe += sizeof(struct mlx4_wqe_bind_seg);
2891 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2892 break;
2893 default:
2894 /* No extra segments required for sends */
2895 break;
2896 }
2897 break;
2898
2899 case MLX4_IB_QPT_TUN_SMI_OWNER:
2900 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2901 ctrl, &seglen);
2902 if (unlikely(err)) {
2903 *bad_wr = wr;
2904 goto out;
2905 }
2906 wqe += seglen;
2907 size += seglen / 16;
2908 break;
2909 case MLX4_IB_QPT_TUN_SMI:
2910 case MLX4_IB_QPT_TUN_GSI:
2911 /* this is a UD qp used in MAD responses to slaves. */
2912 set_datagram_seg(wqe, ud_wr(wr));
2913 /* set the forced-loopback bit in the data seg av */
2914 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2915 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2916 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2917 break;
2918 case MLX4_IB_QPT_UD:
2919 set_datagram_seg(wqe, ud_wr(wr));
2920 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2921 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2922
2923 if (wr->opcode == IB_WR_LSO) {
2924 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
2925 &lso_hdr_sz, &blh);
2926 if (unlikely(err)) {
2927 *bad_wr = wr;
2928 goto out;
2929 }
2930 lso_wqe = (__be32 *) wqe;
2931 wqe += seglen;
2932 size += seglen / 16;
2933 }
2934 break;
2935
2936 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2937 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2938 ctrl, &seglen);
2939 if (unlikely(err)) {
2940 *bad_wr = wr;
2941 goto out;
2942 }
2943 wqe += seglen;
2944 size += seglen / 16;
2945 /* to start tunnel header on a cache-line boundary */
2946 add_zero_len_inline(wqe);
2947 wqe += 16;
2948 size++;
2949 build_tunnel_header(ud_wr(wr), wqe, &seglen);
2950 wqe += seglen;
2951 size += seglen / 16;
2952 break;
2953 case MLX4_IB_QPT_PROXY_SMI:
2954 case MLX4_IB_QPT_PROXY_GSI:
2955 /* If we are tunneling special qps, this is a UD qp.
2956 * In this case we first add a UD segment targeting
2957 * the tunnel qp, and then add a header with address
2958 * information */
2959 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
2960 ud_wr(wr),
2961 qp->mlx4_ib_qp_type);
2962 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2963 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2964 build_tunnel_header(ud_wr(wr), wqe, &seglen);
2965 wqe += seglen;
2966 size += seglen / 16;
2967 break;
2968
2969 case MLX4_IB_QPT_SMI:
2970 case MLX4_IB_QPT_GSI:
2971 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
2972 &seglen);
2973 if (unlikely(err)) {
2974 *bad_wr = wr;
2975 goto out;
2976 }
2977 wqe += seglen;
2978 size += seglen / 16;
2979 break;
2980
2981 default:
2982 break;
2983 }
2984
2985 /*
2986 * Write data segments in reverse order, so as to
2987 * overwrite cacheline stamp last within each
2988 * cacheline. This avoids issues with WQE
2989 * prefetching.
2990 */
2991
2992 dseg = wqe;
2993 dseg += wr->num_sge - 1;
2994 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2995
2996 /* Add one more inline data segment for ICRC for MLX sends */
2997 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2998 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2999 qp->mlx4_ib_qp_type &
3000 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3001 set_mlx_icrc_seg(dseg + 1);
3002 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3003 }
3004
3005 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3006 set_data_seg(dseg, wr->sg_list + i);
3007
3008 /*
3009 * Possibly overwrite stamping in cacheline with LSO
3010 * segment only after making sure all data segments
3011 * are written.
3012 */
3013 wmb();
3014 *lso_wqe = lso_hdr_sz;
3015
3016 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
3017 MLX4_WQE_CTRL_FENCE : 0) | size;
3018
3019 /*
3020 * Make sure descriptor is fully written before
3021 * setting ownership bit (because HW can start
3022 * executing as soon as we do).
3023 */
3024 wmb();
3025
3026 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3027 *bad_wr = wr;
3028 err = -EINVAL;
3029 goto out;
3030 }
3031
3032 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3033 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3034
3035 stamp = ind + qp->sq_spare_wqes;
3036 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3037
3038 /*
3039 * We can improve latency by not stamping the last
3040 * send queue WQE until after ringing the doorbell, so
3041 * only stamp here if there are still more WQEs to post.
3042 *
3043 * Same optimization applies to padding with NOP wqe
3044 * in case of WQE shrinking (used to prevent wrap-around
3045 * in the middle of WR).
3046 */
3047 if (wr->next) {
3048 stamp_send_wqe(qp, stamp, size * 16);
3049 ind = pad_wraparound(qp, ind);
3050 }
3051 }
3052
3053 out:
3054 if (likely(nreq)) {
3055 qp->sq.head += nreq;
3056
3057 /*
3058 * Make sure that descriptors are written before
3059 * doorbell record.
3060 */
3061 wmb();
3062
3063 writel(qp->doorbell_qpn,
3064 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3065
3066 /*
3067 * Make sure doorbells don't leak out of SQ spinlock
3068 * and reach the HCA out of order.
3069 */
3070 mmiowb();
3071
3072 stamp_send_wqe(qp, stamp, size * 16);
3073
3074 ind = pad_wraparound(qp, ind);
3075 qp->sq_next_wqe = ind;
3076 }
3077
3078 spin_unlock_irqrestore(&qp->sq.lock, flags);
3079
3080 return err;
3081 }
3082
mlx4_ib_post_recv(struct ib_qp * ibqp,struct ib_recv_wr * wr,struct ib_recv_wr ** bad_wr)3083 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3084 struct ib_recv_wr **bad_wr)
3085 {
3086 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3087 struct mlx4_wqe_data_seg *scat;
3088 unsigned long flags;
3089 int err = 0;
3090 int nreq;
3091 int ind;
3092 int max_gs;
3093 int i;
3094 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3095
3096 max_gs = qp->rq.max_gs;
3097 spin_lock_irqsave(&qp->rq.lock, flags);
3098
3099 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3100 err = -EIO;
3101 *bad_wr = wr;
3102 nreq = 0;
3103 goto out;
3104 }
3105
3106 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3107
3108 for (nreq = 0; wr; ++nreq, wr = wr->next) {
3109 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3110 err = -ENOMEM;
3111 *bad_wr = wr;
3112 goto out;
3113 }
3114
3115 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3116 err = -EINVAL;
3117 *bad_wr = wr;
3118 goto out;
3119 }
3120
3121 scat = get_recv_wqe(qp, ind);
3122
3123 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3124 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3125 ib_dma_sync_single_for_device(ibqp->device,
3126 qp->sqp_proxy_rcv[ind].map,
3127 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3128 DMA_FROM_DEVICE);
3129 scat->byte_count =
3130 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3131 /* use dma lkey from upper layer entry */
3132 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3133 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3134 scat++;
3135 max_gs--;
3136 }
3137
3138 for (i = 0; i < wr->num_sge; ++i)
3139 __set_data_seg(scat + i, wr->sg_list + i);
3140
3141 if (i < max_gs) {
3142 scat[i].byte_count = 0;
3143 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3144 scat[i].addr = 0;
3145 }
3146
3147 qp->rq.wrid[ind] = wr->wr_id;
3148
3149 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3150 }
3151
3152 out:
3153 if (likely(nreq)) {
3154 qp->rq.head += nreq;
3155
3156 /*
3157 * Make sure that descriptors are written before
3158 * doorbell record.
3159 */
3160 wmb();
3161
3162 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3163 }
3164
3165 spin_unlock_irqrestore(&qp->rq.lock, flags);
3166
3167 return err;
3168 }
3169
to_ib_qp_state(enum mlx4_qp_state mlx4_state)3170 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3171 {
3172 switch (mlx4_state) {
3173 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3174 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3175 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3176 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3177 case MLX4_QP_STATE_SQ_DRAINING:
3178 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3179 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3180 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3181 default: return -1;
3182 }
3183 }
3184
to_ib_mig_state(int mlx4_mig_state)3185 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3186 {
3187 switch (mlx4_mig_state) {
3188 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3189 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3190 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3191 default: return -1;
3192 }
3193 }
3194
to_ib_qp_access_flags(int mlx4_flags)3195 static int to_ib_qp_access_flags(int mlx4_flags)
3196 {
3197 int ib_flags = 0;
3198
3199 if (mlx4_flags & MLX4_QP_BIT_RRE)
3200 ib_flags |= IB_ACCESS_REMOTE_READ;
3201 if (mlx4_flags & MLX4_QP_BIT_RWE)
3202 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3203 if (mlx4_flags & MLX4_QP_BIT_RAE)
3204 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3205
3206 return ib_flags;
3207 }
3208
to_ib_ah_attr(struct mlx4_ib_dev * ibdev,struct ib_ah_attr * ib_ah_attr,struct mlx4_qp_path * path)3209 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3210 struct mlx4_qp_path *path)
3211 {
3212 struct mlx4_dev *dev = ibdev->dev;
3213 int is_eth;
3214
3215 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3216 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3217
3218 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3219 return;
3220
3221 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3222 IB_LINK_LAYER_ETHERNET;
3223 if (is_eth)
3224 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3225 ((path->sched_queue & 4) << 1);
3226 else
3227 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3228
3229 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
3230 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3231 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3232 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3233 if (ib_ah_attr->ah_flags) {
3234 ib_ah_attr->grh.sgid_index = path->mgid_index;
3235 ib_ah_attr->grh.hop_limit = path->hop_limit;
3236 ib_ah_attr->grh.traffic_class =
3237 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3238 ib_ah_attr->grh.flow_label =
3239 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3240 memcpy(ib_ah_attr->grh.dgid.raw,
3241 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3242 }
3243 }
3244
mlx4_ib_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3245 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3246 struct ib_qp_init_attr *qp_init_attr)
3247 {
3248 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3249 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3250 struct mlx4_qp_context context;
3251 int mlx4_state;
3252 int err = 0;
3253
3254 mutex_lock(&qp->mutex);
3255
3256 if (qp->state == IB_QPS_RESET) {
3257 qp_attr->qp_state = IB_QPS_RESET;
3258 goto done;
3259 }
3260
3261 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3262 if (err) {
3263 err = -EINVAL;
3264 goto out;
3265 }
3266
3267 mlx4_state = be32_to_cpu(context.flags) >> 28;
3268
3269 qp->state = to_ib_qp_state(mlx4_state);
3270 qp_attr->qp_state = qp->state;
3271 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3272 qp_attr->path_mig_state =
3273 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3274 qp_attr->qkey = be32_to_cpu(context.qkey);
3275 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3276 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3277 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3278 qp_attr->qp_access_flags =
3279 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3280
3281 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3282 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3283 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3284 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3285 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3286 }
3287
3288 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3289 if (qp_attr->qp_state == IB_QPS_INIT)
3290 qp_attr->port_num = qp->port;
3291 else
3292 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3293
3294 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3295 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3296
3297 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3298
3299 qp_attr->max_dest_rd_atomic =
3300 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3301 qp_attr->min_rnr_timer =
3302 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3303 qp_attr->timeout = context.pri_path.ackto >> 3;
3304 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3305 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3306 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3307
3308 done:
3309 qp_attr->cur_qp_state = qp_attr->qp_state;
3310 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3311 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3312
3313 if (!ibqp->uobject) {
3314 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3315 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3316 } else {
3317 qp_attr->cap.max_send_wr = 0;
3318 qp_attr->cap.max_send_sge = 0;
3319 }
3320
3321 /*
3322 * We don't support inline sends for kernel QPs (yet), and we
3323 * don't know what userspace's value should be.
3324 */
3325 qp_attr->cap.max_inline_data = 0;
3326
3327 qp_init_attr->cap = qp_attr->cap;
3328
3329 qp_init_attr->create_flags = 0;
3330 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3331 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3332
3333 if (qp->flags & MLX4_IB_QP_LSO)
3334 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3335
3336 if (qp->flags & MLX4_IB_QP_NETIF)
3337 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3338
3339 qp_init_attr->sq_sig_type =
3340 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3341 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3342
3343 out:
3344 mutex_unlock(&qp->mutex);
3345 return err;
3346 }
3347
3348