1 /*
2 * SS4200-E Hardware API
3 * Copyright (c) 2009, Intel Corporation.
4 * Copyright IBM Corporation, 2009
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Author: Dave Hansen <dave@sr71.net>
20 */
21
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24 #include <linux/dmi.h>
25 #include <linux/init.h>
26 #include <linux/ioport.h>
27 #include <linux/kernel.h>
28 #include <linux/leds.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/types.h>
32 #include <linux/uaccess.h>
33
34 MODULE_AUTHOR("Rodney Girod <rgirod@confocus.com>, Dave Hansen <dave@sr71.net>");
35 MODULE_DESCRIPTION("Intel NAS/Home Server ICH7 GPIO Driver");
36 MODULE_LICENSE("GPL");
37
38 /*
39 * ICH7 LPC/GPIO PCI Config register offsets
40 */
41 #define PMBASE 0x040
42 #define GPIO_BASE 0x048
43 #define GPIO_CTRL 0x04c
44 #define GPIO_EN 0x010
45
46 /*
47 * The ICH7 GPIO register block is 64 bytes in size.
48 */
49 #define ICH7_GPIO_SIZE 64
50
51 /*
52 * Define register offsets within the ICH7 register block.
53 */
54 #define GPIO_USE_SEL 0x000
55 #define GP_IO_SEL 0x004
56 #define GP_LVL 0x00c
57 #define GPO_BLINK 0x018
58 #define GPI_INV 0x030
59 #define GPIO_USE_SEL2 0x034
60 #define GP_IO_SEL2 0x038
61 #define GP_LVL2 0x03c
62
63 /*
64 * PCI ID of the Intel ICH7 LPC Device within which the GPIO block lives.
65 */
66 static const struct pci_device_id ich7_lpc_pci_id[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0) },
68 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1) },
69 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_30) },
70 { } /* NULL entry */
71 };
72
73 MODULE_DEVICE_TABLE(pci, ich7_lpc_pci_id);
74
ss4200_led_dmi_callback(const struct dmi_system_id * id)75 static int __init ss4200_led_dmi_callback(const struct dmi_system_id *id)
76 {
77 pr_info("detected '%s'\n", id->ident);
78 return 1;
79 }
80
81 static bool nodetect;
82 module_param_named(nodetect, nodetect, bool, 0);
83 MODULE_PARM_DESC(nodetect, "Skip DMI-based hardware detection");
84
85 /*
86 * struct nas_led_whitelist - List of known good models
87 *
88 * Contains the known good models this driver is compatible with.
89 * When adding a new model try to be as strict as possible. This
90 * makes it possible to keep the false positives (the model is
91 * detected as working, but in reality it is not) as low as
92 * possible.
93 */
94 static struct dmi_system_id nas_led_whitelist[] __initdata = {
95 {
96 .callback = ss4200_led_dmi_callback,
97 .ident = "Intel SS4200-E",
98 .matches = {
99 DMI_MATCH(DMI_SYS_VENDOR, "Intel"),
100 DMI_MATCH(DMI_PRODUCT_NAME, "SS4200-E"),
101 DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")
102 }
103 },
104 {}
105 };
106
107 /*
108 * Base I/O address assigned to the Power Management register block
109 */
110 static u32 g_pm_io_base;
111
112 /*
113 * Base I/O address assigned to the ICH7 GPIO register block
114 */
115 static u32 nas_gpio_io_base;
116
117 /*
118 * When we successfully register a region, we are returned a resource.
119 * We use these to identify which regions we need to release on our way
120 * back out.
121 */
122 static struct resource *gp_gpio_resource;
123
124 struct nasgpio_led {
125 char *name;
126 u32 gpio_bit;
127 struct led_classdev led_cdev;
128 };
129
130 /*
131 * gpio_bit(s) are the ICH7 GPIO bit assignments
132 */
133 static struct nasgpio_led nasgpio_leds[] = {
134 { .name = "hdd1:blue:sata", .gpio_bit = 0 },
135 { .name = "hdd1:amber:sata", .gpio_bit = 1 },
136 { .name = "hdd2:blue:sata", .gpio_bit = 2 },
137 { .name = "hdd2:amber:sata", .gpio_bit = 3 },
138 { .name = "hdd3:blue:sata", .gpio_bit = 4 },
139 { .name = "hdd3:amber:sata", .gpio_bit = 5 },
140 { .name = "hdd4:blue:sata", .gpio_bit = 6 },
141 { .name = "hdd4:amber:sata", .gpio_bit = 7 },
142 { .name = "power:blue:power", .gpio_bit = 27},
143 { .name = "power:amber:power", .gpio_bit = 28},
144 };
145
146 #define NAS_RECOVERY 0x00000400 /* GPIO10 */
147
148 static struct nasgpio_led *
led_classdev_to_nasgpio_led(struct led_classdev * led_cdev)149 led_classdev_to_nasgpio_led(struct led_classdev *led_cdev)
150 {
151 return container_of(led_cdev, struct nasgpio_led, led_cdev);
152 }
153
get_led_named(char * name)154 static struct nasgpio_led *get_led_named(char *name)
155 {
156 int i;
157 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
158 if (strcmp(nasgpio_leds[i].name, name))
159 continue;
160 return &nasgpio_leds[i];
161 }
162 return NULL;
163 }
164
165 /*
166 * This protects access to the gpio ports.
167 */
168 static DEFINE_SPINLOCK(nasgpio_gpio_lock);
169
170 /*
171 * There are two gpio ports, one for blinking and the other
172 * for power. @port tells us if we're doing blinking or
173 * power control.
174 *
175 * Caller must hold nasgpio_gpio_lock
176 */
__nasgpio_led_set_attr(struct led_classdev * led_cdev,u32 port,u32 value)177 static void __nasgpio_led_set_attr(struct led_classdev *led_cdev,
178 u32 port, u32 value)
179 {
180 struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
181 u32 gpio_out;
182
183 gpio_out = inl(nas_gpio_io_base + port);
184 if (value)
185 gpio_out |= (1<<led->gpio_bit);
186 else
187 gpio_out &= ~(1<<led->gpio_bit);
188
189 outl(gpio_out, nas_gpio_io_base + port);
190 }
191
nasgpio_led_set_attr(struct led_classdev * led_cdev,u32 port,u32 value)192 static void nasgpio_led_set_attr(struct led_classdev *led_cdev,
193 u32 port, u32 value)
194 {
195 spin_lock(&nasgpio_gpio_lock);
196 __nasgpio_led_set_attr(led_cdev, port, value);
197 spin_unlock(&nasgpio_gpio_lock);
198 }
199
nasgpio_led_get_attr(struct led_classdev * led_cdev,u32 port)200 static u32 nasgpio_led_get_attr(struct led_classdev *led_cdev, u32 port)
201 {
202 struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
203 u32 gpio_in;
204
205 spin_lock(&nasgpio_gpio_lock);
206 gpio_in = inl(nas_gpio_io_base + port);
207 spin_unlock(&nasgpio_gpio_lock);
208 if (gpio_in & (1<<led->gpio_bit))
209 return 1;
210 return 0;
211 }
212
213 /*
214 * There is actual brightness control in the hardware,
215 * but it is via smbus commands and not implemented
216 * in this driver.
217 */
nasgpio_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)218 static void nasgpio_led_set_brightness(struct led_classdev *led_cdev,
219 enum led_brightness brightness)
220 {
221 u32 setting = 0;
222 if (brightness >= LED_HALF)
223 setting = 1;
224 /*
225 * Hold the lock across both operations. This ensures
226 * consistency so that both the "turn off blinking"
227 * and "turn light off" operations complete as a set.
228 */
229 spin_lock(&nasgpio_gpio_lock);
230 /*
231 * LED class documentation asks that past blink state
232 * be disabled when brightness is turned to zero.
233 */
234 if (brightness == 0)
235 __nasgpio_led_set_attr(led_cdev, GPO_BLINK, 0);
236 __nasgpio_led_set_attr(led_cdev, GP_LVL, setting);
237 spin_unlock(&nasgpio_gpio_lock);
238 }
239
nasgpio_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)240 static int nasgpio_led_set_blink(struct led_classdev *led_cdev,
241 unsigned long *delay_on,
242 unsigned long *delay_off)
243 {
244 u32 setting = 1;
245 if (!(*delay_on == 0 && *delay_off == 0) &&
246 !(*delay_on == 500 && *delay_off == 500))
247 return -EINVAL;
248 /*
249 * These are very approximate.
250 */
251 *delay_on = 500;
252 *delay_off = 500;
253
254 nasgpio_led_set_attr(led_cdev, GPO_BLINK, setting);
255
256 return 0;
257 }
258
259
260 /*
261 * Initialize the ICH7 GPIO registers for NAS usage. The BIOS should have
262 * already taken care of this, but we will do so in a non destructive manner
263 * so that we have what we need whether the BIOS did it or not.
264 */
ich7_gpio_init(struct device * dev)265 static int ich7_gpio_init(struct device *dev)
266 {
267 int i;
268 u32 config_data = 0;
269 u32 all_nas_led = 0;
270
271 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
272 all_nas_led |= (1<<nasgpio_leds[i].gpio_bit);
273
274 spin_lock(&nasgpio_gpio_lock);
275 /*
276 * We need to enable all of the GPIO lines used by the NAS box,
277 * so we will read the current Use Selection and add our usage
278 * to it. This should be benign with regard to the original
279 * BIOS configuration.
280 */
281 config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
282 dev_dbg(dev, ": Data read from GPIO_USE_SEL = 0x%08x\n", config_data);
283 config_data |= all_nas_led + NAS_RECOVERY;
284 outl(config_data, nas_gpio_io_base + GPIO_USE_SEL);
285 config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
286 dev_dbg(dev, ": GPIO_USE_SEL = 0x%08x\n\n", config_data);
287
288 /*
289 * The LED GPIO outputs need to be configured for output, so we
290 * will ensure that all LED lines are cleared for output and the
291 * RECOVERY line ready for input. This too should be benign with
292 * regard to BIOS configuration.
293 */
294 config_data = inl(nas_gpio_io_base + GP_IO_SEL);
295 dev_dbg(dev, ": Data read from GP_IO_SEL = 0x%08x\n",
296 config_data);
297 config_data &= ~all_nas_led;
298 config_data |= NAS_RECOVERY;
299 outl(config_data, nas_gpio_io_base + GP_IO_SEL);
300 config_data = inl(nas_gpio_io_base + GP_IO_SEL);
301 dev_dbg(dev, ": GP_IO_SEL = 0x%08x\n", config_data);
302
303 /*
304 * In our final system, the BIOS will initialize the state of all
305 * of the LEDs. For now, we turn them all off (or Low).
306 */
307 config_data = inl(nas_gpio_io_base + GP_LVL);
308 dev_dbg(dev, ": Data read from GP_LVL = 0x%08x\n", config_data);
309 /*
310 * In our final system, the BIOS will initialize the blink state of all
311 * of the LEDs. For now, we turn blink off for all of them.
312 */
313 config_data = inl(nas_gpio_io_base + GPO_BLINK);
314 dev_dbg(dev, ": Data read from GPO_BLINK = 0x%08x\n", config_data);
315
316 /*
317 * At this moment, I am unsure if anything needs to happen with GPI_INV
318 */
319 config_data = inl(nas_gpio_io_base + GPI_INV);
320 dev_dbg(dev, ": Data read from GPI_INV = 0x%08x\n", config_data);
321
322 spin_unlock(&nasgpio_gpio_lock);
323 return 0;
324 }
325
ich7_lpc_cleanup(struct device * dev)326 static void ich7_lpc_cleanup(struct device *dev)
327 {
328 /*
329 * If we were given exclusive use of the GPIO
330 * I/O Address range, we must return it.
331 */
332 if (gp_gpio_resource) {
333 dev_dbg(dev, ": Releasing GPIO I/O addresses\n");
334 release_region(nas_gpio_io_base, ICH7_GPIO_SIZE);
335 gp_gpio_resource = NULL;
336 }
337 }
338
339 /*
340 * The OS has determined that the LPC of the Intel ICH7 Southbridge is present
341 * so we can retrive the required operational information and prepare the GPIO.
342 */
343 static struct pci_dev *nas_gpio_pci_dev;
ich7_lpc_probe(struct pci_dev * dev,const struct pci_device_id * id)344 static int ich7_lpc_probe(struct pci_dev *dev,
345 const struct pci_device_id *id)
346 {
347 int status;
348 u32 gc = 0;
349
350 status = pci_enable_device(dev);
351 if (status) {
352 dev_err(&dev->dev, "pci_enable_device failed\n");
353 return -EIO;
354 }
355
356 nas_gpio_pci_dev = dev;
357 status = pci_read_config_dword(dev, PMBASE, &g_pm_io_base);
358 if (status)
359 goto out;
360 g_pm_io_base &= 0x00000ff80;
361
362 status = pci_read_config_dword(dev, GPIO_CTRL, &gc);
363 if (!(GPIO_EN & gc)) {
364 status = -EEXIST;
365 dev_info(&dev->dev,
366 "ERROR: The LPC GPIO Block has not been enabled.\n");
367 goto out;
368 }
369
370 status = pci_read_config_dword(dev, GPIO_BASE, &nas_gpio_io_base);
371 if (0 > status) {
372 dev_info(&dev->dev, "Unable to read GPIOBASE.\n");
373 goto out;
374 }
375 dev_dbg(&dev->dev, ": GPIOBASE = 0x%08x\n", nas_gpio_io_base);
376 nas_gpio_io_base &= 0x00000ffc0;
377
378 /*
379 * Insure that we have exclusive access to the GPIO I/O address range.
380 */
381 gp_gpio_resource = request_region(nas_gpio_io_base, ICH7_GPIO_SIZE,
382 KBUILD_MODNAME);
383 if (NULL == gp_gpio_resource) {
384 dev_info(&dev->dev,
385 "ERROR Unable to register GPIO I/O addresses.\n");
386 status = -1;
387 goto out;
388 }
389
390 /*
391 * Initialize the GPIO for NAS/Home Server Use
392 */
393 ich7_gpio_init(&dev->dev);
394
395 out:
396 if (status) {
397 ich7_lpc_cleanup(&dev->dev);
398 pci_disable_device(dev);
399 }
400 return status;
401 }
402
ich7_lpc_remove(struct pci_dev * dev)403 static void ich7_lpc_remove(struct pci_dev *dev)
404 {
405 ich7_lpc_cleanup(&dev->dev);
406 pci_disable_device(dev);
407 }
408
409 /*
410 * pci_driver structure passed to the PCI modules
411 */
412 static struct pci_driver nas_gpio_pci_driver = {
413 .name = KBUILD_MODNAME,
414 .id_table = ich7_lpc_pci_id,
415 .probe = ich7_lpc_probe,
416 .remove = ich7_lpc_remove,
417 };
418
get_classdev_for_led_nr(int nr)419 static struct led_classdev *get_classdev_for_led_nr(int nr)
420 {
421 struct nasgpio_led *nas_led = &nasgpio_leds[nr];
422 struct led_classdev *led = &nas_led->led_cdev;
423 return led;
424 }
425
426
set_power_light_amber_noblink(void)427 static void set_power_light_amber_noblink(void)
428 {
429 struct nasgpio_led *amber = get_led_named("power:amber:power");
430 struct nasgpio_led *blue = get_led_named("power:blue:power");
431
432 if (!amber || !blue)
433 return;
434 /*
435 * LED_OFF implies disabling future blinking
436 */
437 pr_debug("setting blue off and amber on\n");
438
439 nasgpio_led_set_brightness(&blue->led_cdev, LED_OFF);
440 nasgpio_led_set_brightness(&amber->led_cdev, LED_FULL);
441 }
442
nas_led_blink_show(struct device * dev,struct device_attribute * attr,char * buf)443 static ssize_t nas_led_blink_show(struct device *dev,
444 struct device_attribute *attr, char *buf)
445 {
446 struct led_classdev *led = dev_get_drvdata(dev);
447 int blinking = 0;
448 if (nasgpio_led_get_attr(led, GPO_BLINK))
449 blinking = 1;
450 return sprintf(buf, "%u\n", blinking);
451 }
452
nas_led_blink_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)453 static ssize_t nas_led_blink_store(struct device *dev,
454 struct device_attribute *attr,
455 const char *buf, size_t size)
456 {
457 int ret;
458 struct led_classdev *led = dev_get_drvdata(dev);
459 unsigned long blink_state;
460
461 ret = kstrtoul(buf, 10, &blink_state);
462 if (ret)
463 return ret;
464
465 nasgpio_led_set_attr(led, GPO_BLINK, blink_state);
466
467 return size;
468 }
469
470 static DEVICE_ATTR(blink, 0644, nas_led_blink_show, nas_led_blink_store);
471
472 static struct attribute *nasgpio_led_attrs[] = {
473 &dev_attr_blink.attr,
474 NULL
475 };
476 ATTRIBUTE_GROUPS(nasgpio_led);
477
register_nasgpio_led(int led_nr)478 static int register_nasgpio_led(int led_nr)
479 {
480 int ret;
481 struct nasgpio_led *nas_led = &nasgpio_leds[led_nr];
482 struct led_classdev *led = get_classdev_for_led_nr(led_nr);
483
484 led->name = nas_led->name;
485 led->brightness = LED_OFF;
486 if (nasgpio_led_get_attr(led, GP_LVL))
487 led->brightness = LED_FULL;
488 led->brightness_set = nasgpio_led_set_brightness;
489 led->blink_set = nasgpio_led_set_blink;
490 led->groups = nasgpio_led_groups;
491 ret = led_classdev_register(&nas_gpio_pci_dev->dev, led);
492 if (ret)
493 return ret;
494
495 return 0;
496 }
497
unregister_nasgpio_led(int led_nr)498 static void unregister_nasgpio_led(int led_nr)
499 {
500 struct led_classdev *led = get_classdev_for_led_nr(led_nr);
501 led_classdev_unregister(led);
502 }
503 /*
504 * module load/initialization
505 */
nas_gpio_init(void)506 static int __init nas_gpio_init(void)
507 {
508 int i;
509 int ret = 0;
510 int nr_devices = 0;
511
512 nr_devices = dmi_check_system(nas_led_whitelist);
513 if (nodetect) {
514 pr_info("skipping hardware autodetection\n");
515 pr_info("Please send 'dmidecode' output to dave@sr71.net\n");
516 nr_devices++;
517 }
518
519 if (nr_devices <= 0) {
520 pr_info("no LED devices found\n");
521 return -ENODEV;
522 }
523
524 pr_info("registering PCI driver\n");
525 ret = pci_register_driver(&nas_gpio_pci_driver);
526 if (ret)
527 return ret;
528 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
529 ret = register_nasgpio_led(i);
530 if (ret)
531 goto out_err;
532 }
533 /*
534 * When the system powers on, the BIOS leaves the power
535 * light blue and blinking. This will turn it solid
536 * amber once the driver is loaded.
537 */
538 set_power_light_amber_noblink();
539 return 0;
540 out_err:
541 for (i--; i >= 0; i--)
542 unregister_nasgpio_led(i);
543 pci_unregister_driver(&nas_gpio_pci_driver);
544 return ret;
545 }
546
547 /*
548 * module unload
549 */
nas_gpio_exit(void)550 static void __exit nas_gpio_exit(void)
551 {
552 int i;
553 pr_info("Unregistering driver\n");
554 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
555 unregister_nasgpio_led(i);
556 pci_unregister_driver(&nas_gpio_pci_driver);
557 }
558
559 module_init(nas_gpio_init);
560 module_exit(nas_gpio_exit);
561