1 /*
2 * cxd2841er.c
3 *
4 * Sony CXD2441ER digital demodulator driver
5 *
6 * Copyright 2012 Sony Corporation
7 * Copyright (C) 2014 NetUP Inc.
8 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
9 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/string.h>
25 #include <linux/slab.h>
26 #include <linux/bitops.h>
27 #include <linux/math64.h>
28 #include <linux/log2.h>
29 #include <linux/dynamic_debug.h>
30
31 #include "dvb_math.h"
32 #include "dvb_frontend.h"
33 #include "cxd2841er.h"
34 #include "cxd2841er_priv.h"
35
36 #define MAX_WRITE_REGSIZE 16
37
38 enum cxd2841er_state {
39 STATE_SHUTDOWN = 0,
40 STATE_SLEEP_S,
41 STATE_ACTIVE_S,
42 STATE_SLEEP_TC,
43 STATE_ACTIVE_TC
44 };
45
46 struct cxd2841er_priv {
47 struct dvb_frontend frontend;
48 struct i2c_adapter *i2c;
49 u8 i2c_addr_slvx;
50 u8 i2c_addr_slvt;
51 const struct cxd2841er_config *config;
52 enum cxd2841er_state state;
53 u8 system;
54 };
55
56 static const struct cxd2841er_cnr_data s_cn_data[] = {
57 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
58 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
59 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
60 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
61 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
62 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
63 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
64 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
65 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
66 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
67 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
68 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
69 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
70 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
71 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
72 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
73 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
74 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
75 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
76 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
77 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
78 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
79 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
80 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
81 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
82 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
83 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
84 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
85 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
86 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
87 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
88 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
89 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
90 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
91 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
92 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
93 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
94 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
95 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
96 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
97 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
98 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
99 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
100 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
101 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
102 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
103 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
104 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
105 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
106 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
107 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
108 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
109 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
110 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
111 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
112 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
113 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
114 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
115 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
116 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
117 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
118 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
119 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
120 { 0x0015, 19900 }, { 0x0014, 20000 },
121 };
122
123 static const struct cxd2841er_cnr_data s2_cn_data[] = {
124 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
125 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
126 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
127 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
128 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
129 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
130 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
131 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
132 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
133 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
134 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
135 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
136 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
137 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
138 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
139 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
140 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
141 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
142 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
143 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
144 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
145 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
146 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
147 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
148 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
149 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
150 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
151 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
152 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
153 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
154 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
155 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
156 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
157 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
158 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
159 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
160 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
161 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
162 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
163 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
164 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
165 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
166 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
167 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
168 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
169 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
170 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
171 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
172 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
173 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
174 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
175 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
176 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
177 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
178 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
179 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
180 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
181 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
182 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
183 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
184 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
185 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
186 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
187 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
188 };
189
190 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
191
cxd2841er_i2c_debug(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 write,const u8 * data,u32 len)192 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
193 u8 addr, u8 reg, u8 write,
194 const u8 *data, u32 len)
195 {
196 dev_dbg(&priv->i2c->dev,
197 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
198 (write == 0 ? "read" : "write"), addr, reg, len);
199 print_hex_dump_bytes("cxd2841er: I2C data: ",
200 DUMP_PREFIX_OFFSET, data, len);
201 }
202
cxd2841er_write_regs(struct cxd2841er_priv * priv,u8 addr,u8 reg,const u8 * data,u32 len)203 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
204 u8 addr, u8 reg, const u8 *data, u32 len)
205 {
206 int ret;
207 u8 buf[MAX_WRITE_REGSIZE + 1];
208 u8 i2c_addr = (addr == I2C_SLVX ?
209 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
210 struct i2c_msg msg[1] = {
211 {
212 .addr = i2c_addr,
213 .flags = 0,
214 .len = len + 1,
215 .buf = buf,
216 }
217 };
218
219 if (len + 1 >= sizeof(buf)) {
220 dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
221 reg, len + 1);
222 return -E2BIG;
223 }
224
225 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
226 buf[0] = reg;
227 memcpy(&buf[1], data, len);
228
229 ret = i2c_transfer(priv->i2c, msg, 1);
230 if (ret >= 0 && ret != 1)
231 ret = -EIO;
232 if (ret < 0) {
233 dev_warn(&priv->i2c->dev,
234 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
235 KBUILD_MODNAME, ret, i2c_addr, reg, len);
236 return ret;
237 }
238 return 0;
239 }
240
cxd2841er_write_reg(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 val)241 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
242 u8 addr, u8 reg, u8 val)
243 {
244 u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
245
246 return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
247 }
248
cxd2841er_read_regs(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 * val,u32 len)249 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
250 u8 addr, u8 reg, u8 *val, u32 len)
251 {
252 int ret;
253 u8 i2c_addr = (addr == I2C_SLVX ?
254 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
255 struct i2c_msg msg[2] = {
256 {
257 .addr = i2c_addr,
258 .flags = 0,
259 .len = 1,
260 .buf = ®,
261 }, {
262 .addr = i2c_addr,
263 .flags = I2C_M_RD,
264 .len = len,
265 .buf = val,
266 }
267 };
268
269 ret = i2c_transfer(priv->i2c, &msg[0], 1);
270 if (ret >= 0 && ret != 1)
271 ret = -EIO;
272 if (ret < 0) {
273 dev_warn(&priv->i2c->dev,
274 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
275 KBUILD_MODNAME, ret, i2c_addr, reg);
276 return ret;
277 }
278 ret = i2c_transfer(priv->i2c, &msg[1], 1);
279 if (ret >= 0 && ret != 1)
280 ret = -EIO;
281 if (ret < 0) {
282 dev_warn(&priv->i2c->dev,
283 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
284 KBUILD_MODNAME, ret, i2c_addr, reg);
285 return ret;
286 }
287 return 0;
288 }
289
cxd2841er_read_reg(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 * val)290 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
291 u8 addr, u8 reg, u8 *val)
292 {
293 return cxd2841er_read_regs(priv, addr, reg, val, 1);
294 }
295
cxd2841er_set_reg_bits(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 data,u8 mask)296 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
297 u8 addr, u8 reg, u8 data, u8 mask)
298 {
299 int res;
300 u8 rdata;
301
302 if (mask != 0xff) {
303 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
304 if (res)
305 return res;
306 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
307 }
308 return cxd2841er_write_reg(priv, addr, reg, data);
309 }
310
cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv * priv,u32 symbol_rate)311 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
312 u32 symbol_rate)
313 {
314 u32 reg_value = 0;
315 u8 data[3] = {0, 0, 0};
316
317 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
318 /*
319 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
320 * = ((symbolRateKSps * 2^14) + 500) / 1000
321 * = ((symbolRateKSps * 16384) + 500) / 1000
322 */
323 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
324 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
325 dev_err(&priv->i2c->dev,
326 "%s(): reg_value is out of range\n", __func__);
327 return -EINVAL;
328 }
329 data[0] = (u8)((reg_value >> 16) & 0x0F);
330 data[1] = (u8)((reg_value >> 8) & 0xFF);
331 data[2] = (u8)(reg_value & 0xFF);
332 /* Set SLV-T Bank : 0xAE */
333 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
334 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
335 return 0;
336 }
337
338 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
339 u8 system);
340
cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv * priv,u8 system,u32 symbol_rate)341 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
342 u8 system, u32 symbol_rate)
343 {
344 int ret;
345 u8 data[4] = { 0, 0, 0, 0 };
346
347 if (priv->state != STATE_SLEEP_S) {
348 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
349 __func__, (int)priv->state);
350 return -EINVAL;
351 }
352 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
353 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
354 /* Set demod mode */
355 if (system == SYS_DVBS) {
356 data[0] = 0x0A;
357 } else if (system == SYS_DVBS2) {
358 data[0] = 0x0B;
359 } else {
360 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
361 __func__, system);
362 return -EINVAL;
363 }
364 /* Set SLV-X Bank : 0x00 */
365 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
366 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
367 /* DVB-S/S2 */
368 data[0] = 0x00;
369 /* Set SLV-T Bank : 0x00 */
370 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
371 /* Enable S/S2 auto detection 1 */
372 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
373 /* Set SLV-T Bank : 0xAE */
374 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
375 /* Enable S/S2 auto detection 2 */
376 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
377 /* Set SLV-T Bank : 0x00 */
378 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
379 /* Enable demod clock */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
381 /* Enable ADC clock */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
383 /* Enable ADC 1 */
384 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
385 /* Enable ADC 2 */
386 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
387 /* Set SLV-X Bank : 0x00 */
388 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
389 /* Enable ADC 3 */
390 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
391 /* Set SLV-T Bank : 0xA3 */
392 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
393 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
394 data[0] = 0x07;
395 data[1] = 0x3B;
396 data[2] = 0x08;
397 data[3] = 0xC5;
398 /* Set SLV-T Bank : 0xAB */
399 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
400 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
401 data[0] = 0x05;
402 data[1] = 0x80;
403 data[2] = 0x0A;
404 data[3] = 0x80;
405 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
406 data[0] = 0x0C;
407 data[1] = 0xCC;
408 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
409 /* Set demod parameter */
410 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
411 if (ret != 0)
412 return ret;
413 /* Set SLV-T Bank : 0x00 */
414 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
415 /* disable Hi-Z setting 1 */
416 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
417 /* disable Hi-Z setting 2 */
418 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
419 priv->state = STATE_ACTIVE_S;
420 return 0;
421 }
422
423 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
424 u32 bandwidth);
425
426 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
427 u32 bandwidth);
428
429 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
430 u32 bandwidth);
431
cxd2841er_retune_active(struct cxd2841er_priv * priv,struct dtv_frontend_properties * p)432 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
433 struct dtv_frontend_properties *p)
434 {
435 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
436 if (priv->state != STATE_ACTIVE_S &&
437 priv->state != STATE_ACTIVE_TC) {
438 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
439 __func__, priv->state);
440 return -EINVAL;
441 }
442 /* Set SLV-T Bank : 0x00 */
443 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
444 /* disable TS output */
445 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
446 if (priv->state == STATE_ACTIVE_S)
447 return cxd2841er_dvbs2_set_symbol_rate(
448 priv, p->symbol_rate / 1000);
449 else if (priv->state == STATE_ACTIVE_TC) {
450 switch (priv->system) {
451 case SYS_DVBT:
452 return cxd2841er_sleep_tc_to_active_t_band(
453 priv, p->bandwidth_hz);
454 case SYS_DVBT2:
455 return cxd2841er_sleep_tc_to_active_t2_band(
456 priv, p->bandwidth_hz);
457 case SYS_DVBC_ANNEX_A:
458 return cxd2841er_sleep_tc_to_active_c_band(
459 priv, 8000000);
460 }
461 }
462 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
463 __func__, priv->system);
464 return -EINVAL;
465 }
466
cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv * priv)467 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
468 {
469 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
470 if (priv->state != STATE_ACTIVE_S) {
471 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
472 __func__, priv->state);
473 return -EINVAL;
474 }
475 /* Set SLV-T Bank : 0x00 */
476 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
477 /* disable TS output */
478 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
479 /* enable Hi-Z setting 1 */
480 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
481 /* enable Hi-Z setting 2 */
482 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
483 /* Set SLV-X Bank : 0x00 */
484 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
485 /* disable ADC 1 */
486 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
487 /* Set SLV-T Bank : 0x00 */
488 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
489 /* disable ADC clock */
490 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
491 /* disable ADC 2 */
492 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
493 /* disable ADC 3 */
494 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
495 /* SADC Bias ON */
496 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
497 /* disable demod clock */
498 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
499 /* Set SLV-T Bank : 0xAE */
500 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
501 /* disable S/S2 auto detection1 */
502 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
503 /* Set SLV-T Bank : 0x00 */
504 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
505 /* disable S/S2 auto detection2 */
506 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
507 priv->state = STATE_SLEEP_S;
508 return 0;
509 }
510
cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv * priv)511 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
512 {
513 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
514 if (priv->state != STATE_SLEEP_S) {
515 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
516 __func__, priv->state);
517 return -EINVAL;
518 }
519 /* Set SLV-T Bank : 0x00 */
520 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
521 /* Disable DSQOUT */
522 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
523 /* Disable DSQIN */
524 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
525 /* Set SLV-X Bank : 0x00 */
526 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
527 /* Disable oscillator */
528 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
529 /* Set demod mode */
530 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
531 priv->state = STATE_SHUTDOWN;
532 return 0;
533 }
534
cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv * priv)535 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
536 {
537 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
538 if (priv->state != STATE_SLEEP_TC) {
539 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
540 __func__, priv->state);
541 return -EINVAL;
542 }
543 /* Set SLV-X Bank : 0x00 */
544 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
545 /* Disable oscillator */
546 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
547 /* Set demod mode */
548 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
549 priv->state = STATE_SHUTDOWN;
550 return 0;
551 }
552
cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv * priv)553 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
554 {
555 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
556 if (priv->state != STATE_ACTIVE_TC) {
557 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
558 __func__, priv->state);
559 return -EINVAL;
560 }
561 /* Set SLV-T Bank : 0x00 */
562 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
563 /* disable TS output */
564 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
565 /* enable Hi-Z setting 1 */
566 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
567 /* enable Hi-Z setting 2 */
568 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
569 /* Set SLV-X Bank : 0x00 */
570 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
571 /* disable ADC 1 */
572 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
573 /* Set SLV-T Bank : 0x00 */
574 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
575 /* Disable ADC 2 */
576 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
577 /* Disable ADC 3 */
578 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
579 /* Disable ADC clock */
580 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
581 /* Disable RF level monitor */
582 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
583 /* Disable demod clock */
584 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
585 priv->state = STATE_SLEEP_TC;
586 return 0;
587 }
588
cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv * priv)589 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
590 {
591 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
592 if (priv->state != STATE_ACTIVE_TC) {
593 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
594 __func__, priv->state);
595 return -EINVAL;
596 }
597 /* Set SLV-T Bank : 0x00 */
598 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
599 /* disable TS output */
600 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
601 /* enable Hi-Z setting 1 */
602 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
603 /* enable Hi-Z setting 2 */
604 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
605 /* Cancel DVB-T2 setting */
606 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
607 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
608 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
609 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
610 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
611 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
612 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
613 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
614 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
615 /* Set SLV-X Bank : 0x00 */
616 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
617 /* disable ADC 1 */
618 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
619 /* Set SLV-T Bank : 0x00 */
620 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
621 /* Disable ADC 2 */
622 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
623 /* Disable ADC 3 */
624 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
625 /* Disable ADC clock */
626 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
627 /* Disable RF level monitor */
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
629 /* Disable demod clock */
630 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
631 priv->state = STATE_SLEEP_TC;
632 return 0;
633 }
634
cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv * priv)635 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
636 {
637 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
638 if (priv->state != STATE_ACTIVE_TC) {
639 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
640 __func__, priv->state);
641 return -EINVAL;
642 }
643 /* Set SLV-T Bank : 0x00 */
644 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
645 /* disable TS output */
646 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
647 /* enable Hi-Z setting 1 */
648 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
649 /* enable Hi-Z setting 2 */
650 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
651 /* Cancel DVB-C setting */
652 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
653 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
654 /* Set SLV-X Bank : 0x00 */
655 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
656 /* disable ADC 1 */
657 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
658 /* Set SLV-T Bank : 0x00 */
659 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
660 /* Disable ADC 2 */
661 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
662 /* Disable ADC 3 */
663 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
664 /* Disable ADC clock */
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
666 /* Disable RF level monitor */
667 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
668 /* Disable demod clock */
669 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
670 priv->state = STATE_SLEEP_TC;
671 return 0;
672 }
673
cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv * priv)674 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
675 {
676 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
677 if (priv->state != STATE_SHUTDOWN) {
678 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
679 __func__, priv->state);
680 return -EINVAL;
681 }
682 /* Set SLV-X Bank : 0x00 */
683 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
684 /* Clear all demodulator registers */
685 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
686 usleep_range(3000, 5000);
687 /* Set SLV-X Bank : 0x00 */
688 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
689 /* Set demod SW reset */
690 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
691 /* Set X'tal clock to 20.5Mhz */
692 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
693 /* Set demod mode */
694 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
695 /* Clear demod SW reset */
696 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
697 usleep_range(1000, 2000);
698 /* Set SLV-T Bank : 0x00 */
699 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
700 /* enable DSQOUT */
701 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
702 /* enable DSQIN */
703 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
704 /* TADC Bias On */
705 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
706 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
707 /* SADC Bias On */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
709 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
711 priv->state = STATE_SLEEP_S;
712 return 0;
713 }
714
cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv * priv)715 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
716 {
717 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
718 if (priv->state != STATE_SHUTDOWN) {
719 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
720 __func__, priv->state);
721 return -EINVAL;
722 }
723 /* Set SLV-X Bank : 0x00 */
724 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
725 /* Clear all demodulator registers */
726 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
727 usleep_range(3000, 5000);
728 /* Set SLV-X Bank : 0x00 */
729 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
730 /* Set demod SW reset */
731 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
732 /* Set X'tal clock to 20.5Mhz */
733 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
734 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
735 /* Clear demod SW reset */
736 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
737 usleep_range(1000, 2000);
738 /* Set SLV-T Bank : 0x00 */
739 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
740 /* TADC Bias On */
741 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
742 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
743 /* SADC Bias On */
744 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
745 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
746 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
747 priv->state = STATE_SLEEP_TC;
748 return 0;
749 }
750
cxd2841er_tune_done(struct cxd2841er_priv * priv)751 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
752 {
753 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
754 /* Set SLV-T Bank : 0x00 */
755 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
756 /* SW Reset */
757 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
758 /* Enable TS output */
759 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
760 return 0;
761 }
762
763 /* Set TS parallel mode */
cxd2841er_set_ts_clock_mode(struct cxd2841er_priv * priv,u8 system)764 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
765 u8 system)
766 {
767 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
768
769 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
770 /* Set SLV-T Bank : 0x00 */
771 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
772 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
773 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
774 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
775 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
776 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
777
778 /*
779 * slave Bank Addr Bit default Name
780 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
781 */
782 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
783 /*
784 * Disable TS IF Clock
785 * slave Bank Addr Bit default Name
786 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
787 */
788 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
789 /*
790 * slave Bank Addr Bit default Name
791 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
792 */
793 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
794 /*
795 * Enable TS IF Clock
796 * slave Bank Addr Bit default Name
797 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
798 */
799 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
800
801 if (system == SYS_DVBT) {
802 /* Enable parity period for DVB-T */
803 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
804 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
805 } else if (system == SYS_DVBC_ANNEX_A) {
806 /* Enable parity period for DVB-C */
807 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
808 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
809 }
810 }
811
cxd2841er_chip_id(struct cxd2841er_priv * priv)812 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
813 {
814 u8 chip_id;
815
816 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
817 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
818 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
819 return chip_id;
820 }
821
cxd2841er_read_status_s(struct dvb_frontend * fe,enum fe_status * status)822 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
823 enum fe_status *status)
824 {
825 u8 reg = 0;
826 struct cxd2841er_priv *priv = fe->demodulator_priv;
827
828 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
829 *status = 0;
830 if (priv->state != STATE_ACTIVE_S) {
831 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
832 __func__, priv->state);
833 return -EINVAL;
834 }
835 /* Set SLV-T Bank : 0xA0 */
836 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
837 /*
838 * slave Bank Addr Bit Signal name
839 * <SLV-T> A0h 11h [2] ITSLOCK
840 */
841 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®);
842 if (reg & 0x04) {
843 *status = FE_HAS_SIGNAL
844 | FE_HAS_CARRIER
845 | FE_HAS_VITERBI
846 | FE_HAS_SYNC
847 | FE_HAS_LOCK;
848 }
849 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
850 return 0;
851 }
852
cxd2841er_read_status_t_t2(struct cxd2841er_priv * priv,u8 * sync,u8 * tslock,u8 * unlock)853 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
854 u8 *sync, u8 *tslock, u8 *unlock)
855 {
856 u8 data = 0;
857
858 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
859 if (priv->state != STATE_ACTIVE_TC)
860 return -EINVAL;
861 if (priv->system == SYS_DVBT) {
862 /* Set SLV-T Bank : 0x10 */
863 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
864 } else {
865 /* Set SLV-T Bank : 0x20 */
866 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
867 }
868 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
869 if ((data & 0x07) == 0x07) {
870 dev_dbg(&priv->i2c->dev,
871 "%s(): invalid hardware state detected\n", __func__);
872 *sync = 0;
873 *tslock = 0;
874 *unlock = 0;
875 } else {
876 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
877 *tslock = ((data & 0x20) ? 1 : 0);
878 *unlock = ((data & 0x10) ? 1 : 0);
879 }
880 return 0;
881 }
882
cxd2841er_read_status_c(struct cxd2841er_priv * priv,u8 * tslock)883 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
884 {
885 u8 data;
886
887 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
888 if (priv->state != STATE_ACTIVE_TC)
889 return -EINVAL;
890 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
891 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
892 if ((data & 0x01) == 0) {
893 *tslock = 0;
894 } else {
895 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
896 *tslock = ((data & 0x20) ? 1 : 0);
897 }
898 return 0;
899 }
900
cxd2841er_read_status_tc(struct dvb_frontend * fe,enum fe_status * status)901 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
902 enum fe_status *status)
903 {
904 int ret = 0;
905 u8 sync = 0;
906 u8 tslock = 0;
907 u8 unlock = 0;
908 struct cxd2841er_priv *priv = fe->demodulator_priv;
909
910 *status = 0;
911 if (priv->state == STATE_ACTIVE_TC) {
912 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
913 ret = cxd2841er_read_status_t_t2(
914 priv, &sync, &tslock, &unlock);
915 if (ret)
916 goto done;
917 if (unlock)
918 goto done;
919 if (sync)
920 *status = FE_HAS_SIGNAL |
921 FE_HAS_CARRIER |
922 FE_HAS_VITERBI |
923 FE_HAS_SYNC;
924 if (tslock)
925 *status |= FE_HAS_LOCK;
926 } else if (priv->system == SYS_DVBC_ANNEX_A) {
927 ret = cxd2841er_read_status_c(priv, &tslock);
928 if (ret)
929 goto done;
930 if (tslock)
931 *status = FE_HAS_SIGNAL |
932 FE_HAS_CARRIER |
933 FE_HAS_VITERBI |
934 FE_HAS_SYNC |
935 FE_HAS_LOCK;
936 }
937 }
938 done:
939 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
940 return ret;
941 }
942
cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv * priv,int * offset)943 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
944 int *offset)
945 {
946 u8 data[3];
947 u8 is_hs_mode;
948 s32 cfrl_ctrlval;
949 s32 temp_div, temp_q, temp_r;
950
951 if (priv->state != STATE_ACTIVE_S) {
952 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
953 __func__, priv->state);
954 return -EINVAL;
955 }
956 /*
957 * Get High Sampling Rate mode
958 * slave Bank Addr Bit Signal name
959 * <SLV-T> A0h 10h [0] ITRL_LOCK
960 */
961 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
962 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
963 if (data[0] & 0x01) {
964 /*
965 * slave Bank Addr Bit Signal name
966 * <SLV-T> A0h 50h [4] IHSMODE
967 */
968 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
969 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
970 } else {
971 dev_dbg(&priv->i2c->dev,
972 "%s(): unable to detect sampling rate mode\n",
973 __func__);
974 return -EINVAL;
975 }
976 /*
977 * slave Bank Addr Bit Signal name
978 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
979 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
980 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
981 */
982 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
983 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
984 (((u32)data[1] & 0xFF) << 8) |
985 ((u32)data[2] & 0xFF), 20);
986 temp_div = (is_hs_mode ? 1048576 : 1572864);
987 if (cfrl_ctrlval > 0) {
988 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
989 temp_div, &temp_r);
990 } else {
991 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
992 temp_div, &temp_r);
993 }
994 if (temp_r >= temp_div / 2)
995 temp_q++;
996 if (cfrl_ctrlval > 0)
997 temp_q *= -1;
998 *offset = temp_q;
999 return 0;
1000 }
1001
cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv * priv,u32 bandwidth,int * offset)1002 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1003 u32 bandwidth, int *offset)
1004 {
1005 u8 data[4];
1006
1007 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1008 if (priv->state != STATE_ACTIVE_TC) {
1009 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1010 __func__, priv->state);
1011 return -EINVAL;
1012 }
1013 if (priv->system != SYS_DVBT2) {
1014 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1015 __func__, priv->system);
1016 return -EINVAL;
1017 }
1018 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1019 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1020 *offset = -1 * sign_extend32(
1021 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1022 ((u32)data[2] << 8) | (u32)data[3], 27);
1023 switch (bandwidth) {
1024 case 1712000:
1025 *offset /= 582;
1026 break;
1027 case 5000000:
1028 case 6000000:
1029 case 7000000:
1030 case 8000000:
1031 *offset *= (bandwidth / 1000000);
1032 *offset /= 940;
1033 break;
1034 default:
1035 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1036 __func__, bandwidth);
1037 return -EINVAL;
1038 }
1039 return 0;
1040 }
1041
cxd2841er_get_carrier_offset_c(struct cxd2841er_priv * priv,int * offset)1042 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1043 int *offset)
1044 {
1045 u8 data[2];
1046
1047 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1048 if (priv->state != STATE_ACTIVE_TC) {
1049 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1050 __func__, priv->state);
1051 return -EINVAL;
1052 }
1053 if (priv->system != SYS_DVBC_ANNEX_A) {
1054 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1055 __func__, priv->system);
1056 return -EINVAL;
1057 }
1058 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1059 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1060 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1061 | (u32)data[1], 13), 16384);
1062 return 0;
1063 }
1064
cxd2841er_read_packet_errors_t(struct cxd2841er_priv * priv,u32 * penum)1065 static int cxd2841er_read_packet_errors_t(
1066 struct cxd2841er_priv *priv, u32 *penum)
1067 {
1068 u8 data[3];
1069
1070 *penum = 0;
1071 if (priv->state != STATE_ACTIVE_TC) {
1072 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1073 __func__, priv->state);
1074 return -EINVAL;
1075 }
1076 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1077 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1078 if (data[2] & 0x01)
1079 *penum = ((u32)data[0] << 8) | (u32)data[1];
1080 return 0;
1081 }
1082
cxd2841er_read_packet_errors_t2(struct cxd2841er_priv * priv,u32 * penum)1083 static int cxd2841er_read_packet_errors_t2(
1084 struct cxd2841er_priv *priv, u32 *penum)
1085 {
1086 u8 data[3];
1087
1088 *penum = 0;
1089 if (priv->state != STATE_ACTIVE_TC) {
1090 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1091 __func__, priv->state);
1092 return -EINVAL;
1093 }
1094 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1095 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1096 if (data[0] & 0x01)
1097 *penum = ((u32)data[1] << 8) | (u32)data[2];
1098 return 0;
1099 }
1100
cxd2841er_mon_read_ber_s(struct cxd2841er_priv * priv)1101 static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1102 {
1103 u8 data[11];
1104 u32 bit_error, bit_count;
1105 u32 temp_q, temp_r;
1106
1107 /* Set SLV-T Bank : 0xA0 */
1108 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1109 /*
1110 * slave Bank Addr Bit Signal name
1111 * <SLV-T> A0h 35h [0] IFVBER_VALID
1112 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1113 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1114 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1115 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1116 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1117 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1118 */
1119 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1120 if (data[0] & 0x01) {
1121 bit_error = ((u32)(data[1] & 0x3F) << 16) |
1122 ((u32)(data[2] & 0xFF) << 8) |
1123 (u32)(data[3] & 0xFF);
1124 bit_count = ((u32)(data[8] & 0x3F) << 16) |
1125 ((u32)(data[9] & 0xFF) << 8) |
1126 (u32)(data[10] & 0xFF);
1127 /*
1128 * BER = bitError / bitCount
1129 * = (bitError * 10^7) / bitCount
1130 * = ((bitError * 625 * 125 * 128) / bitCount
1131 */
1132 if ((bit_count == 0) || (bit_error > bit_count)) {
1133 dev_dbg(&priv->i2c->dev,
1134 "%s(): invalid bit_error %d, bit_count %d\n",
1135 __func__, bit_error, bit_count);
1136 return 0;
1137 }
1138 temp_q = div_u64_rem(10000000ULL * bit_error,
1139 bit_count, &temp_r);
1140 if (bit_count != 1 && temp_r >= bit_count / 2)
1141 temp_q++;
1142 return temp_q;
1143 }
1144 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1145 return 0;
1146 }
1147
1148
cxd2841er_mon_read_ber_s2(struct cxd2841er_priv * priv)1149 static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1150 {
1151 u8 data[5];
1152 u32 bit_error, period;
1153 u32 temp_q, temp_r;
1154 u32 result = 0;
1155
1156 /* Set SLV-T Bank : 0xB2 */
1157 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1158 /*
1159 * slave Bank Addr Bit Signal name
1160 * <SLV-T> B2h 30h [0] IFLBER_VALID
1161 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1162 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1163 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1164 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1165 */
1166 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1167 if (data[0] & 0x01) {
1168 /* Bit error count */
1169 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1170 ((u32)(data[2] & 0xFF) << 16) |
1171 ((u32)(data[3] & 0xFF) << 8) |
1172 (u32)(data[4] & 0xFF);
1173
1174 /* Set SLV-T Bank : 0xA0 */
1175 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1176 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1177 /* Measurement period */
1178 period = (u32)(1 << (data[0] & 0x0F));
1179 if (period == 0) {
1180 dev_dbg(&priv->i2c->dev,
1181 "%s(): period is 0\n", __func__);
1182 return 0;
1183 }
1184 if (bit_error > (period * 64800)) {
1185 dev_dbg(&priv->i2c->dev,
1186 "%s(): invalid bit_err 0x%x period 0x%x\n",
1187 __func__, bit_error, period);
1188 return 0;
1189 }
1190 /*
1191 * BER = bitError / (period * 64800)
1192 * = (bitError * 10^7) / (period * 64800)
1193 * = (bitError * 10^5) / (period * 648)
1194 * = (bitError * 12500) / (period * 81)
1195 * = (bitError * 10) * 1250 / (period * 81)
1196 */
1197 temp_q = div_u64_rem(12500ULL * bit_error,
1198 period * 81, &temp_r);
1199 if (temp_r >= period * 40)
1200 temp_q++;
1201 result = temp_q;
1202 } else {
1203 dev_dbg(&priv->i2c->dev,
1204 "%s(): no data available\n", __func__);
1205 }
1206 return result;
1207 }
1208
cxd2841er_read_ber_t2(struct cxd2841er_priv * priv,u32 * ber)1209 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1210 {
1211 u8 data[4];
1212 u32 div, q, r;
1213 u32 bit_err, period_exp, n_ldpc;
1214
1215 *ber = 0;
1216 if (priv->state != STATE_ACTIVE_TC) {
1217 dev_dbg(&priv->i2c->dev,
1218 "%s(): invalid state %d\n", __func__, priv->state);
1219 return -EINVAL;
1220 }
1221 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1222 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1223 if (!(data[0] & 0x10)) {
1224 dev_dbg(&priv->i2c->dev,
1225 "%s(): no valid BER data\n", __func__);
1226 return 0;
1227 }
1228 bit_err = ((u32)(data[0] & 0x0f) << 24) |
1229 ((u32)data[1] << 16) |
1230 ((u32)data[2] << 8) |
1231 (u32)data[3];
1232 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1233 period_exp = data[0] & 0x0f;
1234 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1235 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1236 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1237 if (bit_err > ((1U << period_exp) * n_ldpc)) {
1238 dev_dbg(&priv->i2c->dev,
1239 "%s(): invalid BER value\n", __func__);
1240 return -EINVAL;
1241 }
1242 if (period_exp >= 4) {
1243 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1244 q = div_u64_rem(3125ULL * bit_err, div, &r);
1245 } else {
1246 div = (1U << period_exp) * (n_ldpc / 200);
1247 q = div_u64_rem(50000ULL * bit_err, div, &r);
1248 }
1249 *ber = (r >= div / 2) ? q + 1 : q;
1250 return 0;
1251 }
1252
cxd2841er_read_ber_t(struct cxd2841er_priv * priv,u32 * ber)1253 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1254 {
1255 u8 data[2];
1256 u32 div, q, r;
1257 u32 bit_err, period;
1258
1259 *ber = 0;
1260 if (priv->state != STATE_ACTIVE_TC) {
1261 dev_dbg(&priv->i2c->dev,
1262 "%s(): invalid state %d\n", __func__, priv->state);
1263 return -EINVAL;
1264 }
1265 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1266 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1267 if (!(data[0] & 0x01)) {
1268 dev_dbg(&priv->i2c->dev,
1269 "%s(): no valid BER data\n", __func__);
1270 return 0;
1271 }
1272 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1273 bit_err = ((u32)data[0] << 8) | (u32)data[1];
1274 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1275 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1276 div = period / 128;
1277 q = div_u64_rem(78125ULL * bit_err, div, &r);
1278 *ber = (r >= div / 2) ? q + 1 : q;
1279 return 0;
1280 }
1281
cxd2841er_dvbs_read_snr(struct cxd2841er_priv * priv,u8 delsys)1282 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1283 {
1284 u8 data[3];
1285 u32 res = 0, value;
1286 int min_index, max_index, index;
1287 static const struct cxd2841er_cnr_data *cn_data;
1288
1289 /* Set SLV-T Bank : 0xA1 */
1290 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1291 /*
1292 * slave Bank Addr Bit Signal name
1293 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1294 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1295 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1296 */
1297 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1298 if (data[0] & 0x01) {
1299 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1300 min_index = 0;
1301 if (delsys == SYS_DVBS) {
1302 cn_data = s_cn_data;
1303 max_index = sizeof(s_cn_data) /
1304 sizeof(s_cn_data[0]) - 1;
1305 } else {
1306 cn_data = s2_cn_data;
1307 max_index = sizeof(s2_cn_data) /
1308 sizeof(s2_cn_data[0]) - 1;
1309 }
1310 if (value >= cn_data[min_index].value) {
1311 res = cn_data[min_index].cnr_x1000;
1312 goto done;
1313 }
1314 if (value <= cn_data[max_index].value) {
1315 res = cn_data[max_index].cnr_x1000;
1316 goto done;
1317 }
1318 while ((max_index - min_index) > 1) {
1319 index = (max_index + min_index) / 2;
1320 if (value == cn_data[index].value) {
1321 res = cn_data[index].cnr_x1000;
1322 goto done;
1323 } else if (value > cn_data[index].value)
1324 max_index = index;
1325 else
1326 min_index = index;
1327 if ((max_index - min_index) <= 1) {
1328 if (value == cn_data[max_index].value) {
1329 res = cn_data[max_index].cnr_x1000;
1330 goto done;
1331 } else {
1332 res = cn_data[min_index].cnr_x1000;
1333 goto done;
1334 }
1335 }
1336 }
1337 } else {
1338 dev_dbg(&priv->i2c->dev,
1339 "%s(): no data available\n", __func__);
1340 }
1341 done:
1342 return res;
1343 }
1344
cxd2841er_read_snr_t(struct cxd2841er_priv * priv,u32 * snr)1345 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1346 {
1347 u32 reg;
1348 u8 data[2];
1349
1350 *snr = 0;
1351 if (priv->state != STATE_ACTIVE_TC) {
1352 dev_dbg(&priv->i2c->dev,
1353 "%s(): invalid state %d\n", __func__, priv->state);
1354 return -EINVAL;
1355 }
1356 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1357 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1358 reg = ((u32)data[0] << 8) | (u32)data[1];
1359 if (reg == 0) {
1360 dev_dbg(&priv->i2c->dev,
1361 "%s(): reg value out of range\n", __func__);
1362 return 0;
1363 }
1364 if (reg > 4996)
1365 reg = 4996;
1366 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1367 return 0;
1368 }
1369
cxd2841er_read_snr_t2(struct cxd2841er_priv * priv,u32 * snr)1370 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1371 {
1372 u32 reg;
1373 u8 data[2];
1374
1375 *snr = 0;
1376 if (priv->state != STATE_ACTIVE_TC) {
1377 dev_dbg(&priv->i2c->dev,
1378 "%s(): invalid state %d\n", __func__, priv->state);
1379 return -EINVAL;
1380 }
1381 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1382 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1383 reg = ((u32)data[0] << 8) | (u32)data[1];
1384 if (reg == 0) {
1385 dev_dbg(&priv->i2c->dev,
1386 "%s(): reg value out of range\n", __func__);
1387 return 0;
1388 }
1389 if (reg > 10876)
1390 reg = 10876;
1391 *snr = 10000 * ((intlog10(reg) -
1392 intlog10(12600 - reg)) >> 24) + 32000;
1393 return 0;
1394 }
1395
cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv * priv,u8 delsys)1396 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1397 u8 delsys)
1398 {
1399 u8 data[2];
1400
1401 cxd2841er_write_reg(
1402 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1403 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1404 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1405 }
1406
cxd2841er_read_agc_gain_s(struct cxd2841er_priv * priv)1407 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1408 {
1409 u8 data[2];
1410
1411 /* Set SLV-T Bank : 0xA0 */
1412 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1413 /*
1414 * slave Bank Addr Bit Signal name
1415 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1416 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1417 */
1418 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1419 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1420 }
1421
cxd2841er_read_ber(struct dvb_frontend * fe,u32 * ber)1422 static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1423 {
1424 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1425 struct cxd2841er_priv *priv = fe->demodulator_priv;
1426
1427 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1428 *ber = 0;
1429 switch (p->delivery_system) {
1430 case SYS_DVBS:
1431 *ber = cxd2841er_mon_read_ber_s(priv);
1432 break;
1433 case SYS_DVBS2:
1434 *ber = cxd2841er_mon_read_ber_s2(priv);
1435 break;
1436 case SYS_DVBT:
1437 return cxd2841er_read_ber_t(priv, ber);
1438 case SYS_DVBT2:
1439 return cxd2841er_read_ber_t2(priv, ber);
1440 default:
1441 *ber = 0;
1442 break;
1443 }
1444 return 0;
1445 }
1446
cxd2841er_read_signal_strength(struct dvb_frontend * fe,u16 * strength)1447 static int cxd2841er_read_signal_strength(struct dvb_frontend *fe,
1448 u16 *strength)
1449 {
1450 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1451 struct cxd2841er_priv *priv = fe->demodulator_priv;
1452
1453 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1454 switch (p->delivery_system) {
1455 case SYS_DVBT:
1456 case SYS_DVBT2:
1457 *strength = 65535 - cxd2841er_read_agc_gain_t_t2(
1458 priv, p->delivery_system);
1459 break;
1460 case SYS_DVBS:
1461 case SYS_DVBS2:
1462 *strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1463 break;
1464 default:
1465 *strength = 0;
1466 break;
1467 }
1468 return 0;
1469 }
1470
cxd2841er_read_snr(struct dvb_frontend * fe,u16 * snr)1471 static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1472 {
1473 u32 tmp = 0;
1474 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1475 struct cxd2841er_priv *priv = fe->demodulator_priv;
1476
1477 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1478 switch (p->delivery_system) {
1479 case SYS_DVBT:
1480 cxd2841er_read_snr_t(priv, &tmp);
1481 break;
1482 case SYS_DVBT2:
1483 cxd2841er_read_snr_t2(priv, &tmp);
1484 break;
1485 case SYS_DVBS:
1486 case SYS_DVBS2:
1487 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1488 break;
1489 default:
1490 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1491 __func__, p->delivery_system);
1492 break;
1493 }
1494 *snr = tmp & 0xffff;
1495 return 0;
1496 }
1497
cxd2841er_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)1498 static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1499 {
1500 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1501 struct cxd2841er_priv *priv = fe->demodulator_priv;
1502
1503 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1504 switch (p->delivery_system) {
1505 case SYS_DVBT:
1506 cxd2841er_read_packet_errors_t(priv, ucblocks);
1507 break;
1508 case SYS_DVBT2:
1509 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1510 break;
1511 default:
1512 *ucblocks = 0;
1513 break;
1514 }
1515 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1516 return 0;
1517 }
1518
cxd2841er_dvbt2_set_profile(struct cxd2841er_priv * priv,enum cxd2841er_dvbt2_profile_t profile)1519 static int cxd2841er_dvbt2_set_profile(
1520 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1521 {
1522 u8 tune_mode;
1523 u8 seq_not2d_time;
1524
1525 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1526 switch (profile) {
1527 case DVBT2_PROFILE_BASE:
1528 tune_mode = 0x01;
1529 seq_not2d_time = 12;
1530 break;
1531 case DVBT2_PROFILE_LITE:
1532 tune_mode = 0x05;
1533 seq_not2d_time = 40;
1534 break;
1535 case DVBT2_PROFILE_ANY:
1536 tune_mode = 0x00;
1537 seq_not2d_time = 40;
1538 break;
1539 default:
1540 return -EINVAL;
1541 }
1542 /* Set SLV-T Bank : 0x2E */
1543 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1544 /* Set profile and tune mode */
1545 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1546 /* Set SLV-T Bank : 0x2B */
1547 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1548 /* Set early unlock detection time */
1549 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1550 return 0;
1551 }
1552
cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv * priv,u8 is_auto,u8 plp_id)1553 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1554 u8 is_auto, u8 plp_id)
1555 {
1556 if (is_auto) {
1557 dev_dbg(&priv->i2c->dev,
1558 "%s() using auto PLP selection\n", __func__);
1559 } else {
1560 dev_dbg(&priv->i2c->dev,
1561 "%s() using manual PLP selection, ID %d\n",
1562 __func__, plp_id);
1563 }
1564 /* Set SLV-T Bank : 0x23 */
1565 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1566 if (!is_auto) {
1567 /* Manual PLP selection mode. Set the data PLP Id. */
1568 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1569 }
1570 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1571 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1572 return 0;
1573 }
1574
cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv * priv,u32 bandwidth)1575 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1576 u32 bandwidth)
1577 {
1578 u32 iffreq;
1579 u8 b20_9f[5];
1580 u8 b10_a6[14];
1581 u8 b10_b6[3];
1582 u8 b10_d7;
1583
1584 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1585 switch (bandwidth) {
1586 case 8000000:
1587 /* bank 0x20, reg 0x9f */
1588 b20_9f[0] = 0x11;
1589 b20_9f[1] = 0xf0;
1590 b20_9f[2] = 0x00;
1591 b20_9f[3] = 0x00;
1592 b20_9f[4] = 0x00;
1593 /* bank 0x10, reg 0xa6 */
1594 b10_a6[0] = 0x26;
1595 b10_a6[1] = 0xaf;
1596 b10_a6[2] = 0x06;
1597 b10_a6[3] = 0xcd;
1598 b10_a6[4] = 0x13;
1599 b10_a6[5] = 0xbb;
1600 b10_a6[6] = 0x28;
1601 b10_a6[7] = 0xba;
1602 b10_a6[8] = 0x23;
1603 b10_a6[9] = 0xa9;
1604 b10_a6[10] = 0x1f;
1605 b10_a6[11] = 0xa8;
1606 b10_a6[12] = 0x2c;
1607 b10_a6[13] = 0xc8;
1608 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1609 b10_d7 = 0x00;
1610 break;
1611 case 7000000:
1612 /* bank 0x20, reg 0x9f */
1613 b20_9f[0] = 0x14;
1614 b20_9f[1] = 0x80;
1615 b20_9f[2] = 0x00;
1616 b20_9f[3] = 0x00;
1617 b20_9f[4] = 0x00;
1618 /* bank 0x10, reg 0xa6 */
1619 b10_a6[0] = 0x2C;
1620 b10_a6[1] = 0xBD;
1621 b10_a6[2] = 0x02;
1622 b10_a6[3] = 0xCF;
1623 b10_a6[4] = 0x04;
1624 b10_a6[5] = 0xF8;
1625 b10_a6[6] = 0x23;
1626 b10_a6[7] = 0xA6;
1627 b10_a6[8] = 0x29;
1628 b10_a6[9] = 0xB0;
1629 b10_a6[10] = 0x26;
1630 b10_a6[11] = 0xA9;
1631 b10_a6[12] = 0x21;
1632 b10_a6[13] = 0xA5;
1633 iffreq = MAKE_IFFREQ_CONFIG(4.2);
1634 b10_d7 = 0x02;
1635 break;
1636 case 6000000:
1637 /* bank 0x20, reg 0x9f */
1638 b20_9f[0] = 0x17;
1639 b20_9f[1] = 0xEA;
1640 b20_9f[2] = 0xAA;
1641 b20_9f[3] = 0xAA;
1642 b20_9f[4] = 0xAA;
1643 /* bank 0x10, reg 0xa6 */
1644 b10_a6[0] = 0x27;
1645 b10_a6[1] = 0xA7;
1646 b10_a6[2] = 0x28;
1647 b10_a6[3] = 0xB3;
1648 b10_a6[4] = 0x02;
1649 b10_a6[5] = 0xF0;
1650 b10_a6[6] = 0x01;
1651 b10_a6[7] = 0xE8;
1652 b10_a6[8] = 0x00;
1653 b10_a6[9] = 0xCF;
1654 b10_a6[10] = 0x00;
1655 b10_a6[11] = 0xE6;
1656 b10_a6[12] = 0x23;
1657 b10_a6[13] = 0xA4;
1658 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1659 b10_d7 = 0x04;
1660 break;
1661 case 5000000:
1662 /* bank 0x20, reg 0x9f */
1663 b20_9f[0] = 0x1C;
1664 b20_9f[1] = 0xB3;
1665 b20_9f[2] = 0x33;
1666 b20_9f[3] = 0x33;
1667 b20_9f[4] = 0x33;
1668 /* bank 0x10, reg 0xa6 */
1669 b10_a6[0] = 0x27;
1670 b10_a6[1] = 0xA7;
1671 b10_a6[2] = 0x28;
1672 b10_a6[3] = 0xB3;
1673 b10_a6[4] = 0x02;
1674 b10_a6[5] = 0xF0;
1675 b10_a6[6] = 0x01;
1676 b10_a6[7] = 0xE8;
1677 b10_a6[8] = 0x00;
1678 b10_a6[9] = 0xCF;
1679 b10_a6[10] = 0x00;
1680 b10_a6[11] = 0xE6;
1681 b10_a6[12] = 0x23;
1682 b10_a6[13] = 0xA4;
1683 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1684 b10_d7 = 0x06;
1685 break;
1686 case 1712000:
1687 /* bank 0x20, reg 0x9f */
1688 b20_9f[0] = 0x58;
1689 b20_9f[1] = 0xE2;
1690 b20_9f[2] = 0xAF;
1691 b20_9f[3] = 0xE0;
1692 b20_9f[4] = 0xBC;
1693 /* bank 0x10, reg 0xa6 */
1694 b10_a6[0] = 0x25;
1695 b10_a6[1] = 0xA0;
1696 b10_a6[2] = 0x36;
1697 b10_a6[3] = 0x8D;
1698 b10_a6[4] = 0x2E;
1699 b10_a6[5] = 0x94;
1700 b10_a6[6] = 0x28;
1701 b10_a6[7] = 0x9B;
1702 b10_a6[8] = 0x32;
1703 b10_a6[9] = 0x90;
1704 b10_a6[10] = 0x2C;
1705 b10_a6[11] = 0x9D;
1706 b10_a6[12] = 0x29;
1707 b10_a6[13] = 0x99;
1708 iffreq = MAKE_IFFREQ_CONFIG(3.5);
1709 b10_d7 = 0x03;
1710 break;
1711 default:
1712 return -EINVAL;
1713 }
1714 /* Set SLV-T Bank : 0x20 */
1715 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x20);
1716 cxd2841er_write_regs(priv, I2C_SLVT, 0x9f, b20_9f, sizeof(b20_9f));
1717 /* Set SLV-T Bank : 0x27 */
1718 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1719 cxd2841er_set_reg_bits(
1720 priv, I2C_SLVT, 0x7a,
1721 (bandwidth == 1712000 ? 0x03 : 0x00), 0x0f);
1722 /* Set SLV-T Bank : 0x10 */
1723 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1724 /* Group delay equaliser sett. for ASCOT2E */
1725 cxd2841er_write_regs(priv, I2C_SLVT, 0xa6, b10_a6, sizeof(b10_a6));
1726 /* <IF freq setting> */
1727 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1728 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1729 b10_b6[2] = (u8)(iffreq & 0xff);
1730 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1731 /* System bandwidth setting */
1732 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, b10_d7, 0x07);
1733 return 0;
1734 }
1735
cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv * priv,u32 bandwidth)1736 static int cxd2841er_sleep_tc_to_active_t_band(
1737 struct cxd2841er_priv *priv, u32 bandwidth)
1738 {
1739 u8 b13_9c[2] = { 0x01, 0x14 };
1740 u8 bw8mhz_b10_9f[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 };
1741 u8 bw8mhz_b10_a6[] = { 0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB,
1742 0x28, 0xBA, 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8 };
1743 u8 bw8mhz_b10_d9[] = { 0x01, 0xE0 };
1744 u8 bw8mhz_b17_38[] = { 0x01, 0x02 };
1745 u8 bw7mhz_b10_9f[] = { 0x14, 0x80, 0x00, 0x00, 0x00 };
1746 u8 bw7mhz_b10_a6[] = { 0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8,
1747 0x23, 0xA6, 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5 };
1748 u8 bw7mhz_b10_d9[] = { 0x12, 0xF8 };
1749 u8 bw7mhz_b17_38[] = { 0x00, 0x03 };
1750 u8 bw6mhz_b10_9f[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA };
1751 u8 bw6mhz_b10_a6[] = { 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0,
1752 0x01, 0xE8, 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
1753 u8 bw6mhz_b10_d9[] = { 0x1F, 0xDC };
1754 u8 bw6mhz_b17_38[] = { 0x00, 0x03 };
1755 u8 bw5mhz_b10_9f[] = { 0x1C, 0xB3, 0x33, 0x33, 0x33 };
1756 u8 bw5mhz_b10_a6[] = { 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0,
1757 0x01, 0xE8, 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
1758 u8 bw5mhz_b10_d9[] = { 0x26, 0x3C };
1759 u8 bw5mhz_b17_38[] = { 0x00, 0x03 };
1760 u8 b10_b6[3];
1761 u8 d7val;
1762 u32 iffreq;
1763 u8 *b10_9f;
1764 u8 *b10_a6;
1765 u8 *b10_d9;
1766 u8 *b17_38;
1767
1768 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1769 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
1770 /* Echo performance optimization setting */
1771 cxd2841er_write_regs(priv, I2C_SLVT, 0x9c, b13_9c, sizeof(b13_9c));
1772 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1773
1774 switch (bandwidth) {
1775 case 8000000:
1776 b10_9f = bw8mhz_b10_9f;
1777 b10_a6 = bw8mhz_b10_a6;
1778 b10_d9 = bw8mhz_b10_d9;
1779 b17_38 = bw8mhz_b17_38;
1780 d7val = 0;
1781 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1782 break;
1783 case 7000000:
1784 b10_9f = bw7mhz_b10_9f;
1785 b10_a6 = bw7mhz_b10_a6;
1786 b10_d9 = bw7mhz_b10_d9;
1787 b17_38 = bw7mhz_b17_38;
1788 d7val = 2;
1789 iffreq = MAKE_IFFREQ_CONFIG(4.20);
1790 break;
1791 case 6000000:
1792 b10_9f = bw6mhz_b10_9f;
1793 b10_a6 = bw6mhz_b10_a6;
1794 b10_d9 = bw6mhz_b10_d9;
1795 b17_38 = bw6mhz_b17_38;
1796 d7val = 4;
1797 iffreq = MAKE_IFFREQ_CONFIG(3.60);
1798 break;
1799 case 5000000:
1800 b10_9f = bw5mhz_b10_9f;
1801 b10_a6 = bw5mhz_b10_a6;
1802 b10_d9 = bw5mhz_b10_d9;
1803 b17_38 = bw5mhz_b17_38;
1804 d7val = 6;
1805 iffreq = MAKE_IFFREQ_CONFIG(3.60);
1806 break;
1807 default:
1808 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1809 __func__, bandwidth);
1810 return -EINVAL;
1811 }
1812 /* <IF freq setting> */
1813 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1814 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1815 b10_b6[2] = (u8)(iffreq & 0xff);
1816 cxd2841er_write_regs(
1817 priv, I2C_SLVT, 0x9f, b10_9f, sizeof(bw8mhz_b10_9f));
1818 cxd2841er_write_regs(
1819 priv, I2C_SLVT, 0xa6, b10_a6, sizeof(bw8mhz_b10_a6));
1820 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1821 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, d7val, 0x7);
1822 cxd2841er_write_regs(
1823 priv, I2C_SLVT, 0xd9, b10_d9, sizeof(bw8mhz_b10_d9));
1824 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
1825 cxd2841er_write_regs(
1826 priv, I2C_SLVT, 0x38, b17_38, sizeof(bw8mhz_b17_38));
1827 return 0;
1828 }
1829
cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv * priv,u32 bandwidth)1830 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
1831 u32 bandwidth)
1832 {
1833 u8 bw7_8mhz_b10_a6[] = {
1834 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
1835 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
1836 u8 bw6mhz_b10_a6[] = {
1837 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1838 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
1839 u8 b10_b6[3];
1840 u32 iffreq;
1841
1842 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1843 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1844 switch (bandwidth) {
1845 case 8000000:
1846 case 7000000:
1847 cxd2841er_write_regs(
1848 priv, I2C_SLVT, 0xa6,
1849 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
1850 iffreq = MAKE_IFFREQ_CONFIG(4.9);
1851 break;
1852 case 6000000:
1853 cxd2841er_write_regs(
1854 priv, I2C_SLVT, 0xa6,
1855 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
1856 iffreq = MAKE_IFFREQ_CONFIG(3.7);
1857 break;
1858 default:
1859 dev_dbg(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
1860 __func__, bandwidth);
1861 return -EINVAL;
1862 }
1863 /* <IF freq setting> */
1864 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1865 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1866 b10_b6[2] = (u8)(iffreq & 0xff);
1867 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1868 /* Set SLV-T Bank : 0x11 */
1869 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
1870 switch (bandwidth) {
1871 case 8000000:
1872 case 7000000:
1873 cxd2841er_set_reg_bits(
1874 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
1875 break;
1876 case 6000000:
1877 cxd2841er_set_reg_bits(
1878 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
1879 break;
1880 }
1881 /* Set SLV-T Bank : 0x40 */
1882 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1883 switch (bandwidth) {
1884 case 8000000:
1885 cxd2841er_set_reg_bits(
1886 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
1887 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
1888 break;
1889 case 7000000:
1890 cxd2841er_set_reg_bits(
1891 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
1892 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
1893 break;
1894 case 6000000:
1895 cxd2841er_set_reg_bits(
1896 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
1897 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
1898 break;
1899 }
1900 return 0;
1901 }
1902
cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv * priv,u32 bandwidth)1903 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
1904 u32 bandwidth)
1905 {
1906 u8 data[2] = { 0x09, 0x54 };
1907
1908 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1909 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
1910 /* Set SLV-X Bank : 0x00 */
1911 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
1912 /* Set demod mode */
1913 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
1914 /* Set SLV-T Bank : 0x00 */
1915 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1916 /* Enable demod clock */
1917 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
1918 /* Disable RF level monitor */
1919 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
1920 /* Enable ADC clock */
1921 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
1922 /* Enable ADC 1 */
1923 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
1924 /* xtal freq 20.5MHz */
1925 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
1926 /* Enable ADC 4 */
1927 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
1928 /* Set SLV-T Bank : 0x10 */
1929 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1930 /* IFAGC gain settings */
1931 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
1932 /* Set SLV-T Bank : 0x11 */
1933 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
1934 /* BBAGC TARGET level setting */
1935 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
1936 /* Set SLV-T Bank : 0x10 */
1937 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1938 /* ASCOT setting ON */
1939 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
1940 /* Set SLV-T Bank : 0x18 */
1941 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
1942 /* Pre-RS BER moniter setting */
1943 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
1944 /* FEC Auto Recovery setting */
1945 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
1946 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
1947 /* Set SLV-T Bank : 0x00 */
1948 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1949 /* TSIF setting */
1950 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
1951 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
1952 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
1953 /* Set SLV-T Bank : 0x00 */
1954 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1955 /* Disable HiZ Setting 1 */
1956 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
1957 /* Disable HiZ Setting 2 */
1958 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
1959 priv->state = STATE_ACTIVE_TC;
1960 return 0;
1961 }
1962
cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv * priv,u32 bandwidth)1963 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
1964 u32 bandwidth)
1965 {
1966 u8 data[2] = { 0x09, 0x54 };
1967
1968 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1969 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
1970 /* Set SLV-X Bank : 0x00 */
1971 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
1972 /* Set demod mode */
1973 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
1974 /* Set SLV-T Bank : 0x00 */
1975 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1976 /* Enable demod clock */
1977 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
1978 /* Disable RF level monitor */
1979 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
1980 /* Enable ADC clock */
1981 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
1982 /* Enable ADC 1 */
1983 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
1984 /* xtal freq 20.5MHz */
1985 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
1986 /* Enable ADC 4 */
1987 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
1988 /* Set SLV-T Bank : 0x10 */
1989 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1990 /* IFAGC gain settings */
1991 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
1992 /* Set SLV-T Bank : 0x11 */
1993 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
1994 /* BBAGC TARGET level setting */
1995 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
1996 /* Set SLV-T Bank : 0x10 */
1997 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1998 /* ASCOT setting ON */
1999 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2000 /* Set SLV-T Bank : 0x20 */
2001 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2002 /* Acquisition optimization setting */
2003 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2004 /* Set SLV-T Bank : 0x2b */
2005 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2006 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2007 /* Set SLV-T Bank : 0x00 */
2008 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2009 /* TSIF setting */
2010 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2011 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2012 /* DVB-T2 initial setting */
2013 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2014 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2015 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2016 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2017 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2018 /* Set SLV-T Bank : 0x2a */
2019 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2020 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2021 /* Set SLV-T Bank : 0x2b */
2022 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2023 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2024
2025 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2026
2027 /* Set SLV-T Bank : 0x00 */
2028 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2029 /* Disable HiZ Setting 1 */
2030 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2031 /* Disable HiZ Setting 2 */
2032 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2033 priv->state = STATE_ACTIVE_TC;
2034 return 0;
2035 }
2036
cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv * priv,u32 bandwidth)2037 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2038 u32 bandwidth)
2039 {
2040 u8 data[2] = { 0x09, 0x54 };
2041
2042 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2043 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2044 /* Set SLV-X Bank : 0x00 */
2045 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2046 /* Set demod mode */
2047 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2048 /* Set SLV-T Bank : 0x00 */
2049 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2050 /* Enable demod clock */
2051 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2052 /* Disable RF level monitor */
2053 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2054 /* Enable ADC clock */
2055 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2056 /* Enable ADC 1 */
2057 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2058 /* xtal freq 20.5MHz */
2059 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2060 /* Enable ADC 4 */
2061 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2062 /* Set SLV-T Bank : 0x10 */
2063 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2064 /* IFAGC gain settings */
2065 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2066 /* Set SLV-T Bank : 0x11 */
2067 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2068 /* BBAGC TARGET level setting */
2069 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2070 /* Set SLV-T Bank : 0x10 */
2071 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2072 /* ASCOT setting ON */
2073 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2074 /* Set SLV-T Bank : 0x40 */
2075 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2076 /* Demod setting */
2077 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2078 /* Set SLV-T Bank : 0x00 */
2079 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2080 /* TSIF setting */
2081 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2082 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2083
2084 cxd2841er_sleep_tc_to_active_c_band(priv, 8000000);
2085 /* Set SLV-T Bank : 0x00 */
2086 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2087 /* Disable HiZ Setting 1 */
2088 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2089 /* Disable HiZ Setting 2 */
2090 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2091 priv->state = STATE_ACTIVE_TC;
2092 return 0;
2093 }
2094
cxd2841er_get_frontend(struct dvb_frontend * fe)2095 static int cxd2841er_get_frontend(struct dvb_frontend *fe)
2096 {
2097 enum fe_status status = 0;
2098 u16 strength = 0, snr = 0;
2099 u32 errors = 0, ber = 0;
2100 struct cxd2841er_priv *priv = fe->demodulator_priv;
2101 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2102
2103 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2104 if (priv->state == STATE_ACTIVE_S)
2105 cxd2841er_read_status_s(fe, &status);
2106 else if (priv->state == STATE_ACTIVE_TC)
2107 cxd2841er_read_status_tc(fe, &status);
2108
2109 if (status & FE_HAS_LOCK) {
2110 cxd2841er_read_signal_strength(fe, &strength);
2111 p->strength.len = 1;
2112 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2113 p->strength.stat[0].uvalue = strength;
2114 cxd2841er_read_snr(fe, &snr);
2115 p->cnr.len = 1;
2116 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2117 p->cnr.stat[0].svalue = snr;
2118 cxd2841er_read_ucblocks(fe, &errors);
2119 p->block_error.len = 1;
2120 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2121 p->block_error.stat[0].uvalue = errors;
2122 cxd2841er_read_ber(fe, &ber);
2123 p->post_bit_error.len = 1;
2124 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2125 p->post_bit_error.stat[0].uvalue = ber;
2126 } else {
2127 p->strength.len = 1;
2128 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2129 p->cnr.len = 1;
2130 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2131 p->block_error.len = 1;
2132 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2133 p->post_bit_error.len = 1;
2134 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2135 }
2136 return 0;
2137 }
2138
cxd2841er_set_frontend_s(struct dvb_frontend * fe)2139 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2140 {
2141 int ret = 0, i, timeout, carr_offset;
2142 enum fe_status status;
2143 struct cxd2841er_priv *priv = fe->demodulator_priv;
2144 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2145 u32 symbol_rate = p->symbol_rate/1000;
2146
2147 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d\n",
2148 __func__,
2149 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
2150 p->frequency, symbol_rate);
2151 switch (priv->state) {
2152 case STATE_SLEEP_S:
2153 ret = cxd2841er_sleep_s_to_active_s(
2154 priv, p->delivery_system, symbol_rate);
2155 break;
2156 case STATE_ACTIVE_S:
2157 ret = cxd2841er_retune_active(priv, p);
2158 break;
2159 default:
2160 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2161 __func__, priv->state);
2162 ret = -EINVAL;
2163 goto done;
2164 }
2165 if (ret) {
2166 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2167 goto done;
2168 }
2169 if (fe->ops.i2c_gate_ctrl)
2170 fe->ops.i2c_gate_ctrl(fe, 1);
2171 if (fe->ops.tuner_ops.set_params)
2172 fe->ops.tuner_ops.set_params(fe);
2173 if (fe->ops.i2c_gate_ctrl)
2174 fe->ops.i2c_gate_ctrl(fe, 0);
2175 cxd2841er_tune_done(priv);
2176 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
2177 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
2178 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
2179 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
2180 cxd2841er_read_status_s(fe, &status);
2181 if (status & FE_HAS_LOCK)
2182 break;
2183 }
2184 if (status & FE_HAS_LOCK) {
2185 if (cxd2841er_get_carrier_offset_s_s2(
2186 priv, &carr_offset)) {
2187 ret = -EINVAL;
2188 goto done;
2189 }
2190 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
2191 __func__, carr_offset);
2192 }
2193 done:
2194 return ret;
2195 }
2196
cxd2841er_set_frontend_tc(struct dvb_frontend * fe)2197 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
2198 {
2199 int ret = 0, timeout;
2200 enum fe_status status;
2201 struct cxd2841er_priv *priv = fe->demodulator_priv;
2202 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2203
2204 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2205 if (p->delivery_system == SYS_DVBT) {
2206 priv->system = SYS_DVBT;
2207 switch (priv->state) {
2208 case STATE_SLEEP_TC:
2209 ret = cxd2841er_sleep_tc_to_active_t(
2210 priv, p->bandwidth_hz);
2211 break;
2212 case STATE_ACTIVE_TC:
2213 ret = cxd2841er_retune_active(priv, p);
2214 break;
2215 default:
2216 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2217 __func__, priv->state);
2218 ret = -EINVAL;
2219 }
2220 } else if (p->delivery_system == SYS_DVBT2) {
2221 priv->system = SYS_DVBT2;
2222 cxd2841er_dvbt2_set_plp_config(priv,
2223 (int)(p->stream_id > 255), p->stream_id);
2224 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
2225 switch (priv->state) {
2226 case STATE_SLEEP_TC:
2227 ret = cxd2841er_sleep_tc_to_active_t2(priv,
2228 p->bandwidth_hz);
2229 break;
2230 case STATE_ACTIVE_TC:
2231 ret = cxd2841er_retune_active(priv, p);
2232 break;
2233 default:
2234 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2235 __func__, priv->state);
2236 ret = -EINVAL;
2237 }
2238 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
2239 p->delivery_system == SYS_DVBC_ANNEX_C) {
2240 priv->system = SYS_DVBC_ANNEX_A;
2241 switch (priv->state) {
2242 case STATE_SLEEP_TC:
2243 ret = cxd2841er_sleep_tc_to_active_c(
2244 priv, p->bandwidth_hz);
2245 break;
2246 case STATE_ACTIVE_TC:
2247 ret = cxd2841er_retune_active(priv, p);
2248 break;
2249 default:
2250 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2251 __func__, priv->state);
2252 ret = -EINVAL;
2253 }
2254 } else {
2255 dev_dbg(&priv->i2c->dev,
2256 "%s(): invalid delivery system %d\n",
2257 __func__, p->delivery_system);
2258 ret = -EINVAL;
2259 }
2260 if (ret)
2261 goto done;
2262 if (fe->ops.i2c_gate_ctrl)
2263 fe->ops.i2c_gate_ctrl(fe, 1);
2264 if (fe->ops.tuner_ops.set_params)
2265 fe->ops.tuner_ops.set_params(fe);
2266 if (fe->ops.i2c_gate_ctrl)
2267 fe->ops.i2c_gate_ctrl(fe, 0);
2268 cxd2841er_tune_done(priv);
2269 timeout = 2500;
2270 while (timeout > 0) {
2271 ret = cxd2841er_read_status_tc(fe, &status);
2272 if (ret)
2273 goto done;
2274 if (status & FE_HAS_LOCK)
2275 break;
2276 msleep(20);
2277 timeout -= 20;
2278 }
2279 if (timeout < 0)
2280 dev_dbg(&priv->i2c->dev,
2281 "%s(): LOCK wait timeout\n", __func__);
2282 done:
2283 return ret;
2284 }
2285
cxd2841er_tune_s(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)2286 static int cxd2841er_tune_s(struct dvb_frontend *fe,
2287 bool re_tune,
2288 unsigned int mode_flags,
2289 unsigned int *delay,
2290 enum fe_status *status)
2291 {
2292 int ret, carrier_offset;
2293 struct cxd2841er_priv *priv = fe->demodulator_priv;
2294 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2295
2296 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
2297 if (re_tune) {
2298 ret = cxd2841er_set_frontend_s(fe);
2299 if (ret)
2300 return ret;
2301 cxd2841er_read_status_s(fe, status);
2302 if (*status & FE_HAS_LOCK) {
2303 if (cxd2841er_get_carrier_offset_s_s2(
2304 priv, &carrier_offset))
2305 return -EINVAL;
2306 p->frequency += carrier_offset;
2307 ret = cxd2841er_set_frontend_s(fe);
2308 if (ret)
2309 return ret;
2310 }
2311 }
2312 *delay = HZ / 5;
2313 return cxd2841er_read_status_s(fe, status);
2314 }
2315
cxd2841er_tune_tc(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)2316 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
2317 bool re_tune,
2318 unsigned int mode_flags,
2319 unsigned int *delay,
2320 enum fe_status *status)
2321 {
2322 int ret, carrier_offset;
2323 struct cxd2841er_priv *priv = fe->demodulator_priv;
2324 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2325
2326 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d\n", __func__, re_tune);
2327 if (re_tune) {
2328 ret = cxd2841er_set_frontend_tc(fe);
2329 if (ret)
2330 return ret;
2331 cxd2841er_read_status_tc(fe, status);
2332 if (*status & FE_HAS_LOCK) {
2333 switch (priv->system) {
2334 case SYS_DVBT:
2335 case SYS_DVBT2:
2336 ret = cxd2841er_get_carrier_offset_t2(
2337 priv, p->bandwidth_hz,
2338 &carrier_offset);
2339 break;
2340 case SYS_DVBC_ANNEX_A:
2341 ret = cxd2841er_get_carrier_offset_c(
2342 priv, &carrier_offset);
2343 break;
2344 default:
2345 dev_dbg(&priv->i2c->dev,
2346 "%s(): invalid delivery system %d\n",
2347 __func__, priv->system);
2348 return -EINVAL;
2349 }
2350 if (ret)
2351 return ret;
2352 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
2353 __func__, carrier_offset);
2354 p->frequency += carrier_offset;
2355 ret = cxd2841er_set_frontend_tc(fe);
2356 if (ret)
2357 return ret;
2358 }
2359 }
2360 *delay = HZ / 5;
2361 return cxd2841er_read_status_tc(fe, status);
2362 }
2363
cxd2841er_sleep_s(struct dvb_frontend * fe)2364 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
2365 {
2366 struct cxd2841er_priv *priv = fe->demodulator_priv;
2367
2368 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2369 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
2370 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
2371 return 0;
2372 }
2373
cxd2841er_sleep_tc(struct dvb_frontend * fe)2374 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
2375 {
2376 struct cxd2841er_priv *priv = fe->demodulator_priv;
2377
2378 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2379 if (priv->state == STATE_ACTIVE_TC) {
2380 switch (priv->system) {
2381 case SYS_DVBT:
2382 cxd2841er_active_t_to_sleep_tc(priv);
2383 break;
2384 case SYS_DVBT2:
2385 cxd2841er_active_t2_to_sleep_tc(priv);
2386 break;
2387 case SYS_DVBC_ANNEX_A:
2388 cxd2841er_active_c_to_sleep_tc(priv);
2389 break;
2390 default:
2391 dev_warn(&priv->i2c->dev,
2392 "%s(): unknown delivery system %d\n",
2393 __func__, priv->system);
2394 }
2395 }
2396 if (priv->state != STATE_SLEEP_TC) {
2397 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
2398 __func__, priv->state);
2399 return -EINVAL;
2400 }
2401 cxd2841er_sleep_tc_to_shutdown(priv);
2402 return 0;
2403 }
2404
cxd2841er_send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd burst)2405 static int cxd2841er_send_burst(struct dvb_frontend *fe,
2406 enum fe_sec_mini_cmd burst)
2407 {
2408 u8 data;
2409 struct cxd2841er_priv *priv = fe->demodulator_priv;
2410
2411 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
2412 (burst == SEC_MINI_A ? "A" : "B"));
2413 if (priv->state != STATE_SLEEP_S &&
2414 priv->state != STATE_ACTIVE_S) {
2415 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2416 __func__, priv->state);
2417 return -EINVAL;
2418 }
2419 data = (burst == SEC_MINI_A ? 0 : 1);
2420 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
2421 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
2422 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
2423 return 0;
2424 }
2425
cxd2841er_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)2426 static int cxd2841er_set_tone(struct dvb_frontend *fe,
2427 enum fe_sec_tone_mode tone)
2428 {
2429 u8 data;
2430 struct cxd2841er_priv *priv = fe->demodulator_priv;
2431
2432 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
2433 (tone == SEC_TONE_ON ? "On" : "Off"));
2434 if (priv->state != STATE_SLEEP_S &&
2435 priv->state != STATE_ACTIVE_S) {
2436 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2437 __func__, priv->state);
2438 return -EINVAL;
2439 }
2440 data = (tone == SEC_TONE_ON ? 1 : 0);
2441 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
2442 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
2443 return 0;
2444 }
2445
cxd2841er_send_diseqc_msg(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)2446 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
2447 struct dvb_diseqc_master_cmd *cmd)
2448 {
2449 int i;
2450 u8 data[12];
2451 struct cxd2841er_priv *priv = fe->demodulator_priv;
2452
2453 if (priv->state != STATE_SLEEP_S &&
2454 priv->state != STATE_ACTIVE_S) {
2455 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2456 __func__, priv->state);
2457 return -EINVAL;
2458 }
2459 dev_dbg(&priv->i2c->dev,
2460 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
2461 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
2462 /* DiDEqC enable */
2463 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
2464 /* cmd1 length & data */
2465 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
2466 memset(data, 0, sizeof(data));
2467 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
2468 data[i] = cmd->msg[i];
2469 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
2470 /* repeat count for cmd1 */
2471 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
2472 /* repeat count for cmd2: always 0 */
2473 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
2474 /* start transmit */
2475 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
2476 /* wait for 1 sec timeout */
2477 for (i = 0; i < 50; i++) {
2478 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
2479 if (!data[0]) {
2480 dev_dbg(&priv->i2c->dev,
2481 "%s(): DiSEqC cmd has been sent\n", __func__);
2482 return 0;
2483 }
2484 msleep(20);
2485 }
2486 dev_dbg(&priv->i2c->dev,
2487 "%s(): DiSEqC cmd transmit timeout\n", __func__);
2488 return -ETIMEDOUT;
2489 }
2490
cxd2841er_release(struct dvb_frontend * fe)2491 static void cxd2841er_release(struct dvb_frontend *fe)
2492 {
2493 struct cxd2841er_priv *priv = fe->demodulator_priv;
2494
2495 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2496 kfree(priv);
2497 }
2498
cxd2841er_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)2499 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2500 {
2501 struct cxd2841er_priv *priv = fe->demodulator_priv;
2502
2503 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
2504 cxd2841er_set_reg_bits(
2505 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
2506 return 0;
2507 }
2508
cxd2841er_get_algo(struct dvb_frontend * fe)2509 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
2510 {
2511 struct cxd2841er_priv *priv = fe->demodulator_priv;
2512
2513 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2514 return DVBFE_ALGO_HW;
2515 }
2516
cxd2841er_init_s(struct dvb_frontend * fe)2517 static int cxd2841er_init_s(struct dvb_frontend *fe)
2518 {
2519 struct cxd2841er_priv *priv = fe->demodulator_priv;
2520
2521 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2522 cxd2841er_shutdown_to_sleep_s(priv);
2523 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
2524 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
2525 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
2526 return 0;
2527 }
2528
cxd2841er_init_tc(struct dvb_frontend * fe)2529 static int cxd2841er_init_tc(struct dvb_frontend *fe)
2530 {
2531 struct cxd2841er_priv *priv = fe->demodulator_priv;
2532
2533 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2534 cxd2841er_shutdown_to_sleep_tc(priv);
2535 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
2536 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2537 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
2538 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
2539 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
2540 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
2541 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2542 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
2543 return 0;
2544 }
2545
2546 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
2547 static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops;
2548 static struct dvb_frontend_ops cxd2841er_dvbc_ops;
2549
cxd2841er_attach(struct cxd2841er_config * cfg,struct i2c_adapter * i2c,u8 system)2550 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
2551 struct i2c_adapter *i2c,
2552 u8 system)
2553 {
2554 u8 chip_id = 0;
2555 const char *type;
2556 struct cxd2841er_priv *priv = NULL;
2557
2558 /* allocate memory for the internal state */
2559 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
2560 if (!priv)
2561 return NULL;
2562 priv->i2c = i2c;
2563 priv->config = cfg;
2564 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
2565 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
2566 /* create dvb_frontend */
2567 switch (system) {
2568 case SYS_DVBS:
2569 memcpy(&priv->frontend.ops,
2570 &cxd2841er_dvbs_s2_ops,
2571 sizeof(struct dvb_frontend_ops));
2572 type = "S/S2";
2573 break;
2574 case SYS_DVBT:
2575 memcpy(&priv->frontend.ops,
2576 &cxd2841er_dvbt_t2_ops,
2577 sizeof(struct dvb_frontend_ops));
2578 type = "T/T2";
2579 break;
2580 case SYS_DVBC_ANNEX_A:
2581 memcpy(&priv->frontend.ops,
2582 &cxd2841er_dvbc_ops,
2583 sizeof(struct dvb_frontend_ops));
2584 type = "C/C2";
2585 break;
2586 default:
2587 kfree(priv);
2588 return NULL;
2589 }
2590 priv->frontend.demodulator_priv = priv;
2591 dev_info(&priv->i2c->dev,
2592 "%s(): attaching CXD2841ER DVB-%s frontend\n",
2593 __func__, type);
2594 dev_info(&priv->i2c->dev,
2595 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
2596 __func__, priv->i2c,
2597 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
2598 chip_id = cxd2841er_chip_id(priv);
2599 if (chip_id != CXD2841ER_CHIP_ID) {
2600 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
2601 __func__, chip_id);
2602 priv->frontend.demodulator_priv = NULL;
2603 kfree(priv);
2604 return NULL;
2605 }
2606 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
2607 __func__, chip_id);
2608 return &priv->frontend;
2609 }
2610
cxd2841er_attach_s(struct cxd2841er_config * cfg,struct i2c_adapter * i2c)2611 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
2612 struct i2c_adapter *i2c)
2613 {
2614 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
2615 }
2616 EXPORT_SYMBOL(cxd2841er_attach_s);
2617
cxd2841er_attach_t(struct cxd2841er_config * cfg,struct i2c_adapter * i2c)2618 struct dvb_frontend *cxd2841er_attach_t(struct cxd2841er_config *cfg,
2619 struct i2c_adapter *i2c)
2620 {
2621 return cxd2841er_attach(cfg, i2c, SYS_DVBT);
2622 }
2623 EXPORT_SYMBOL(cxd2841er_attach_t);
2624
cxd2841er_attach_c(struct cxd2841er_config * cfg,struct i2c_adapter * i2c)2625 struct dvb_frontend *cxd2841er_attach_c(struct cxd2841er_config *cfg,
2626 struct i2c_adapter *i2c)
2627 {
2628 return cxd2841er_attach(cfg, i2c, SYS_DVBC_ANNEX_A);
2629 }
2630 EXPORT_SYMBOL(cxd2841er_attach_c);
2631
2632 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
2633 .delsys = { SYS_DVBS, SYS_DVBS2 },
2634 .info = {
2635 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
2636 .frequency_min = 500000,
2637 .frequency_max = 2500000,
2638 .frequency_stepsize = 0,
2639 .symbol_rate_min = 1000000,
2640 .symbol_rate_max = 45000000,
2641 .symbol_rate_tolerance = 500,
2642 .caps = FE_CAN_INVERSION_AUTO |
2643 FE_CAN_FEC_AUTO |
2644 FE_CAN_QPSK,
2645 },
2646 .init = cxd2841er_init_s,
2647 .sleep = cxd2841er_sleep_s,
2648 .release = cxd2841er_release,
2649 .set_frontend = cxd2841er_set_frontend_s,
2650 .get_frontend = cxd2841er_get_frontend,
2651 .read_status = cxd2841er_read_status_s,
2652 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
2653 .get_frontend_algo = cxd2841er_get_algo,
2654 .set_tone = cxd2841er_set_tone,
2655 .diseqc_send_burst = cxd2841er_send_burst,
2656 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
2657 .tune = cxd2841er_tune_s
2658 };
2659
2660 static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops = {
2661 .delsys = { SYS_DVBT, SYS_DVBT2 },
2662 .info = {
2663 .name = "Sony CXD2841ER DVB-T/T2 demodulator",
2664 .caps = FE_CAN_FEC_1_2 |
2665 FE_CAN_FEC_2_3 |
2666 FE_CAN_FEC_3_4 |
2667 FE_CAN_FEC_5_6 |
2668 FE_CAN_FEC_7_8 |
2669 FE_CAN_FEC_AUTO |
2670 FE_CAN_QPSK |
2671 FE_CAN_QAM_16 |
2672 FE_CAN_QAM_32 |
2673 FE_CAN_QAM_64 |
2674 FE_CAN_QAM_128 |
2675 FE_CAN_QAM_256 |
2676 FE_CAN_QAM_AUTO |
2677 FE_CAN_TRANSMISSION_MODE_AUTO |
2678 FE_CAN_GUARD_INTERVAL_AUTO |
2679 FE_CAN_HIERARCHY_AUTO |
2680 FE_CAN_MUTE_TS |
2681 FE_CAN_2G_MODULATION,
2682 .frequency_min = 42000000,
2683 .frequency_max = 1002000000,
2684 .symbol_rate_min = 870000,
2685 .symbol_rate_max = 11700000
2686 },
2687 .init = cxd2841er_init_tc,
2688 .sleep = cxd2841er_sleep_tc,
2689 .release = cxd2841er_release,
2690 .set_frontend = cxd2841er_set_frontend_tc,
2691 .get_frontend = cxd2841er_get_frontend,
2692 .read_status = cxd2841er_read_status_tc,
2693 .tune = cxd2841er_tune_tc,
2694 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
2695 .get_frontend_algo = cxd2841er_get_algo
2696 };
2697
2698 static struct dvb_frontend_ops cxd2841er_dvbc_ops = {
2699 .delsys = { SYS_DVBC_ANNEX_A },
2700 .info = {
2701 .name = "Sony CXD2841ER DVB-C demodulator",
2702 .caps = FE_CAN_FEC_1_2 |
2703 FE_CAN_FEC_2_3 |
2704 FE_CAN_FEC_3_4 |
2705 FE_CAN_FEC_5_6 |
2706 FE_CAN_FEC_7_8 |
2707 FE_CAN_FEC_AUTO |
2708 FE_CAN_QAM_16 |
2709 FE_CAN_QAM_32 |
2710 FE_CAN_QAM_64 |
2711 FE_CAN_QAM_128 |
2712 FE_CAN_QAM_256 |
2713 FE_CAN_QAM_AUTO |
2714 FE_CAN_INVERSION_AUTO,
2715 .frequency_min = 42000000,
2716 .frequency_max = 1002000000
2717 },
2718 .init = cxd2841er_init_tc,
2719 .sleep = cxd2841er_sleep_tc,
2720 .release = cxd2841er_release,
2721 .set_frontend = cxd2841er_set_frontend_tc,
2722 .get_frontend = cxd2841er_get_frontend,
2723 .read_status = cxd2841er_read_status_tc,
2724 .tune = cxd2841er_tune_tc,
2725 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
2726 .get_frontend_algo = cxd2841er_get_algo,
2727 };
2728
2729 MODULE_DESCRIPTION("Sony CXD2841ER DVB-C/C2/T/T2/S/S2 demodulator driver");
2730 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>");
2731 MODULE_LICENSE("GPL");
2732