1 /* 2 * Copyright (C) 2008 Nokia Corporation 3 * 4 * Based on lirc_serial.c 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 #include <linux/module.h> 23 #include <linux/interrupt.h> 24 #include <linux/uaccess.h> 25 #include <linux/platform_device.h> 26 #include <linux/sched.h> 27 #include <linux/wait.h> 28 29 #include <plat/dmtimer.h> 30 #include <plat/clock.h> 31 32 #include <media/lirc.h> 33 #include <media/lirc_dev.h> 34 #include <media/ir-rx51.h> 35 36 #define LIRC_RX51_DRIVER_FEATURES (LIRC_CAN_SET_SEND_DUTY_CYCLE | \ 37 LIRC_CAN_SET_SEND_CARRIER | \ 38 LIRC_CAN_SEND_PULSE) 39 40 #define DRIVER_NAME "lirc_rx51" 41 42 #define WBUF_LEN 256 43 44 #define TIMER_MAX_VALUE 0xffffffff 45 46 struct lirc_rx51 { 47 struct omap_dm_timer *pwm_timer; 48 struct omap_dm_timer *pulse_timer; 49 struct device *dev; 50 struct lirc_rx51_platform_data *pdata; 51 wait_queue_head_t wqueue; 52 53 unsigned long fclk_khz; 54 unsigned int freq; /* carrier frequency */ 55 unsigned int duty_cycle; /* carrier duty cycle */ 56 unsigned int irq_num; 57 unsigned int match; 58 int wbuf[WBUF_LEN]; 59 int wbuf_index; 60 unsigned long device_is_open; 61 int pwm_timer_num; 62 }; 63 lirc_rx51_on(struct lirc_rx51 * lirc_rx51)64 static void lirc_rx51_on(struct lirc_rx51 *lirc_rx51) 65 { 66 omap_dm_timer_set_pwm(lirc_rx51->pwm_timer, 0, 1, 67 OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE); 68 } 69 lirc_rx51_off(struct lirc_rx51 * lirc_rx51)70 static void lirc_rx51_off(struct lirc_rx51 *lirc_rx51) 71 { 72 omap_dm_timer_set_pwm(lirc_rx51->pwm_timer, 0, 1, 73 OMAP_TIMER_TRIGGER_NONE); 74 } 75 init_timing_params(struct lirc_rx51 * lirc_rx51)76 static int init_timing_params(struct lirc_rx51 *lirc_rx51) 77 { 78 u32 load, match; 79 80 load = -(lirc_rx51->fclk_khz * 1000 / lirc_rx51->freq); 81 match = -(lirc_rx51->duty_cycle * -load / 100); 82 omap_dm_timer_set_load(lirc_rx51->pwm_timer, 1, load); 83 omap_dm_timer_set_match(lirc_rx51->pwm_timer, 1, match); 84 omap_dm_timer_write_counter(lirc_rx51->pwm_timer, TIMER_MAX_VALUE - 2); 85 omap_dm_timer_start(lirc_rx51->pwm_timer); 86 omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0); 87 omap_dm_timer_start(lirc_rx51->pulse_timer); 88 89 lirc_rx51->match = 0; 90 91 return 0; 92 } 93 94 #define tics_after(a, b) ((long)(b) - (long)(a) < 0) 95 pulse_timer_set_timeout(struct lirc_rx51 * lirc_rx51,int usec)96 static int pulse_timer_set_timeout(struct lirc_rx51 *lirc_rx51, int usec) 97 { 98 int counter; 99 100 BUG_ON(usec < 0); 101 102 if (lirc_rx51->match == 0) 103 counter = omap_dm_timer_read_counter(lirc_rx51->pulse_timer); 104 else 105 counter = lirc_rx51->match; 106 107 counter += (u32)(lirc_rx51->fclk_khz * usec / (1000)); 108 omap_dm_timer_set_match(lirc_rx51->pulse_timer, 1, counter); 109 omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 110 OMAP_TIMER_INT_MATCH); 111 if (tics_after(omap_dm_timer_read_counter(lirc_rx51->pulse_timer), 112 counter)) { 113 return 1; 114 } 115 return 0; 116 } 117 lirc_rx51_interrupt_handler(int irq,void * ptr)118 static irqreturn_t lirc_rx51_interrupt_handler(int irq, void *ptr) 119 { 120 unsigned int retval; 121 struct lirc_rx51 *lirc_rx51 = ptr; 122 123 retval = omap_dm_timer_read_status(lirc_rx51->pulse_timer); 124 if (!retval) 125 return IRQ_NONE; 126 127 if (retval & ~OMAP_TIMER_INT_MATCH) 128 dev_err_ratelimited(lirc_rx51->dev, 129 ": Unexpected interrupt source: %x\n", retval); 130 131 omap_dm_timer_write_status(lirc_rx51->pulse_timer, 132 OMAP_TIMER_INT_MATCH | 133 OMAP_TIMER_INT_OVERFLOW | 134 OMAP_TIMER_INT_CAPTURE); 135 if (lirc_rx51->wbuf_index < 0) { 136 dev_err_ratelimited(lirc_rx51->dev, 137 ": BUG wbuf_index has value of %i\n", 138 lirc_rx51->wbuf_index); 139 goto end; 140 } 141 142 /* 143 * If we happen to hit an odd latency spike, loop through the 144 * pulses until we catch up. 145 */ 146 do { 147 if (lirc_rx51->wbuf_index >= WBUF_LEN) 148 goto end; 149 if (lirc_rx51->wbuf[lirc_rx51->wbuf_index] == -1) 150 goto end; 151 152 if (lirc_rx51->wbuf_index % 2) 153 lirc_rx51_off(lirc_rx51); 154 else 155 lirc_rx51_on(lirc_rx51); 156 157 retval = pulse_timer_set_timeout(lirc_rx51, 158 lirc_rx51->wbuf[lirc_rx51->wbuf_index]); 159 lirc_rx51->wbuf_index++; 160 161 } while (retval); 162 163 return IRQ_HANDLED; 164 end: 165 /* Stop TX here */ 166 lirc_rx51_off(lirc_rx51); 167 lirc_rx51->wbuf_index = -1; 168 omap_dm_timer_stop(lirc_rx51->pwm_timer); 169 omap_dm_timer_stop(lirc_rx51->pulse_timer); 170 omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0); 171 wake_up_interruptible(&lirc_rx51->wqueue); 172 173 return IRQ_HANDLED; 174 } 175 lirc_rx51_init_port(struct lirc_rx51 * lirc_rx51)176 static int lirc_rx51_init_port(struct lirc_rx51 *lirc_rx51) 177 { 178 struct clk *clk_fclk; 179 int retval, pwm_timer = lirc_rx51->pwm_timer_num; 180 181 lirc_rx51->pwm_timer = omap_dm_timer_request_specific(pwm_timer); 182 if (lirc_rx51->pwm_timer == NULL) { 183 dev_err(lirc_rx51->dev, ": Error requesting GPT%d timer\n", 184 pwm_timer); 185 return -EBUSY; 186 } 187 188 lirc_rx51->pulse_timer = omap_dm_timer_request(); 189 if (lirc_rx51->pulse_timer == NULL) { 190 dev_err(lirc_rx51->dev, ": Error requesting pulse timer\n"); 191 retval = -EBUSY; 192 goto err1; 193 } 194 195 omap_dm_timer_set_source(lirc_rx51->pwm_timer, OMAP_TIMER_SRC_SYS_CLK); 196 omap_dm_timer_set_source(lirc_rx51->pulse_timer, 197 OMAP_TIMER_SRC_SYS_CLK); 198 199 omap_dm_timer_enable(lirc_rx51->pwm_timer); 200 omap_dm_timer_enable(lirc_rx51->pulse_timer); 201 202 lirc_rx51->irq_num = omap_dm_timer_get_irq(lirc_rx51->pulse_timer); 203 retval = request_irq(lirc_rx51->irq_num, lirc_rx51_interrupt_handler, 204 IRQF_SHARED, "lirc_pulse_timer", lirc_rx51); 205 if (retval) { 206 dev_err(lirc_rx51->dev, ": Failed to request interrupt line\n"); 207 goto err2; 208 } 209 210 clk_fclk = omap_dm_timer_get_fclk(lirc_rx51->pwm_timer); 211 lirc_rx51->fclk_khz = clk_fclk->rate / 1000; 212 213 return 0; 214 215 err2: 216 omap_dm_timer_free(lirc_rx51->pulse_timer); 217 err1: 218 omap_dm_timer_free(lirc_rx51->pwm_timer); 219 220 return retval; 221 } 222 lirc_rx51_free_port(struct lirc_rx51 * lirc_rx51)223 static int lirc_rx51_free_port(struct lirc_rx51 *lirc_rx51) 224 { 225 omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0); 226 free_irq(lirc_rx51->irq_num, lirc_rx51); 227 lirc_rx51_off(lirc_rx51); 228 omap_dm_timer_disable(lirc_rx51->pwm_timer); 229 omap_dm_timer_disable(lirc_rx51->pulse_timer); 230 omap_dm_timer_free(lirc_rx51->pwm_timer); 231 omap_dm_timer_free(lirc_rx51->pulse_timer); 232 lirc_rx51->wbuf_index = -1; 233 234 return 0; 235 } 236 lirc_rx51_write(struct file * file,const char * buf,size_t n,loff_t * ppos)237 static ssize_t lirc_rx51_write(struct file *file, const char *buf, 238 size_t n, loff_t *ppos) 239 { 240 int count, i; 241 struct lirc_rx51 *lirc_rx51 = file->private_data; 242 243 if (n % sizeof(int)) 244 return -EINVAL; 245 246 count = n / sizeof(int); 247 if ((count > WBUF_LEN) || (count % 2 == 0)) 248 return -EINVAL; 249 250 /* Wait any pending transfers to finish */ 251 wait_event_interruptible(lirc_rx51->wqueue, lirc_rx51->wbuf_index < 0); 252 253 if (copy_from_user(lirc_rx51->wbuf, buf, n)) 254 return -EFAULT; 255 256 /* Sanity check the input pulses */ 257 for (i = 0; i < count; i++) 258 if (lirc_rx51->wbuf[i] < 0) 259 return -EINVAL; 260 261 init_timing_params(lirc_rx51); 262 if (count < WBUF_LEN) 263 lirc_rx51->wbuf[count] = -1; /* Insert termination mark */ 264 265 /* 266 * Adjust latency requirements so the device doesn't go in too 267 * deep sleep states 268 */ 269 lirc_rx51->pdata->set_max_mpu_wakeup_lat(lirc_rx51->dev, 50); 270 271 lirc_rx51_on(lirc_rx51); 272 lirc_rx51->wbuf_index = 1; 273 pulse_timer_set_timeout(lirc_rx51, lirc_rx51->wbuf[0]); 274 275 /* 276 * Don't return back to the userspace until the transfer has 277 * finished 278 */ 279 wait_event_interruptible(lirc_rx51->wqueue, lirc_rx51->wbuf_index < 0); 280 281 /* We can sleep again */ 282 lirc_rx51->pdata->set_max_mpu_wakeup_lat(lirc_rx51->dev, -1); 283 284 return n; 285 } 286 lirc_rx51_ioctl(struct file * filep,unsigned int cmd,unsigned long arg)287 static long lirc_rx51_ioctl(struct file *filep, 288 unsigned int cmd, unsigned long arg) 289 { 290 int result; 291 unsigned long value; 292 unsigned int ivalue; 293 struct lirc_rx51 *lirc_rx51 = filep->private_data; 294 295 switch (cmd) { 296 case LIRC_GET_SEND_MODE: 297 result = put_user(LIRC_MODE_PULSE, (unsigned long *)arg); 298 if (result) 299 return result; 300 break; 301 302 case LIRC_SET_SEND_MODE: 303 result = get_user(value, (unsigned long *)arg); 304 if (result) 305 return result; 306 307 /* only LIRC_MODE_PULSE supported */ 308 if (value != LIRC_MODE_PULSE) 309 return -ENOSYS; 310 break; 311 312 case LIRC_GET_REC_MODE: 313 result = put_user(0, (unsigned long *) arg); 314 if (result) 315 return result; 316 break; 317 318 case LIRC_GET_LENGTH: 319 return -ENOSYS; 320 break; 321 322 case LIRC_SET_SEND_DUTY_CYCLE: 323 result = get_user(ivalue, (unsigned int *) arg); 324 if (result) 325 return result; 326 327 if (ivalue <= 0 || ivalue > 100) { 328 dev_err(lirc_rx51->dev, ": invalid duty cycle %d\n", 329 ivalue); 330 return -EINVAL; 331 } 332 333 lirc_rx51->duty_cycle = ivalue; 334 break; 335 336 case LIRC_SET_SEND_CARRIER: 337 result = get_user(ivalue, (unsigned int *) arg); 338 if (result) 339 return result; 340 341 if (ivalue > 500000 || ivalue < 20000) { 342 dev_err(lirc_rx51->dev, ": invalid carrier freq %d\n", 343 ivalue); 344 return -EINVAL; 345 } 346 347 lirc_rx51->freq = ivalue; 348 break; 349 350 case LIRC_GET_FEATURES: 351 result = put_user(LIRC_RX51_DRIVER_FEATURES, 352 (unsigned long *) arg); 353 if (result) 354 return result; 355 break; 356 357 default: 358 return -ENOIOCTLCMD; 359 } 360 361 return 0; 362 } 363 lirc_rx51_open(struct inode * inode,struct file * file)364 static int lirc_rx51_open(struct inode *inode, struct file *file) 365 { 366 struct lirc_rx51 *lirc_rx51 = lirc_get_pdata(file); 367 BUG_ON(!lirc_rx51); 368 369 file->private_data = lirc_rx51; 370 371 if (test_and_set_bit(1, &lirc_rx51->device_is_open)) 372 return -EBUSY; 373 374 return lirc_rx51_init_port(lirc_rx51); 375 } 376 lirc_rx51_release(struct inode * inode,struct file * file)377 static int lirc_rx51_release(struct inode *inode, struct file *file) 378 { 379 struct lirc_rx51 *lirc_rx51 = file->private_data; 380 381 lirc_rx51_free_port(lirc_rx51); 382 383 clear_bit(1, &lirc_rx51->device_is_open); 384 385 return 0; 386 } 387 388 static struct lirc_rx51 lirc_rx51 = { 389 .freq = 38000, 390 .duty_cycle = 50, 391 .wbuf_index = -1, 392 }; 393 394 static const struct file_operations lirc_fops = { 395 .owner = THIS_MODULE, 396 .write = lirc_rx51_write, 397 .unlocked_ioctl = lirc_rx51_ioctl, 398 .read = lirc_dev_fop_read, 399 .poll = lirc_dev_fop_poll, 400 .open = lirc_rx51_open, 401 .release = lirc_rx51_release, 402 }; 403 404 static struct lirc_driver lirc_rx51_driver = { 405 .name = DRIVER_NAME, 406 .minor = -1, 407 .code_length = 1, 408 .data = &lirc_rx51, 409 .fops = &lirc_fops, 410 .owner = THIS_MODULE, 411 }; 412 413 #ifdef CONFIG_PM 414 lirc_rx51_suspend(struct platform_device * dev,pm_message_t state)415 static int lirc_rx51_suspend(struct platform_device *dev, pm_message_t state) 416 { 417 /* 418 * In case the device is still open, do not suspend. Normally 419 * this should not be a problem as lircd only keeps the device 420 * open only for short periods of time. We also don't want to 421 * get involved with race conditions that might happen if we 422 * were in a middle of a transmit. Thus, we defer any suspend 423 * actions until transmit has completed. 424 */ 425 if (test_and_set_bit(1, &lirc_rx51.device_is_open)) 426 return -EAGAIN; 427 428 clear_bit(1, &lirc_rx51.device_is_open); 429 430 return 0; 431 } 432 lirc_rx51_resume(struct platform_device * dev)433 static int lirc_rx51_resume(struct platform_device *dev) 434 { 435 return 0; 436 } 437 438 #else 439 440 #define lirc_rx51_suspend NULL 441 #define lirc_rx51_resume NULL 442 443 #endif /* CONFIG_PM */ 444 lirc_rx51_probe(struct platform_device * dev)445 static int lirc_rx51_probe(struct platform_device *dev) 446 { 447 lirc_rx51_driver.features = LIRC_RX51_DRIVER_FEATURES; 448 lirc_rx51.pdata = dev->dev.platform_data; 449 lirc_rx51.pwm_timer_num = lirc_rx51.pdata->pwm_timer; 450 lirc_rx51.dev = &dev->dev; 451 lirc_rx51_driver.dev = &dev->dev; 452 lirc_rx51_driver.minor = lirc_register_driver(&lirc_rx51_driver); 453 init_waitqueue_head(&lirc_rx51.wqueue); 454 455 if (lirc_rx51_driver.minor < 0) { 456 dev_err(lirc_rx51.dev, ": lirc_register_driver failed: %d\n", 457 lirc_rx51_driver.minor); 458 return lirc_rx51_driver.minor; 459 } 460 dev_info(lirc_rx51.dev, "registration ok, minor: %d, pwm: %d\n", 461 lirc_rx51_driver.minor, lirc_rx51.pwm_timer_num); 462 463 return 0; 464 } 465 lirc_rx51_remove(struct platform_device * dev)466 static int lirc_rx51_remove(struct platform_device *dev) 467 { 468 return lirc_unregister_driver(lirc_rx51_driver.minor); 469 } 470 471 struct platform_driver lirc_rx51_platform_driver = { 472 .probe = lirc_rx51_probe, 473 .remove = lirc_rx51_remove, 474 .suspend = lirc_rx51_suspend, 475 .resume = lirc_rx51_resume, 476 .driver = { 477 .name = DRIVER_NAME, 478 .owner = THIS_MODULE, 479 }, 480 }; 481 module_platform_driver(lirc_rx51_platform_driver); 482 483 MODULE_DESCRIPTION("LIRC TX driver for Nokia RX51"); 484 MODULE_AUTHOR("Nokia Corporation"); 485 MODULE_LICENSE("GPL"); 486