1 /*
2 * Driver for Allwinner sunXi IR controller
3 *
4 * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
5 * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
6 *
7 * Based on sun5i-ir.c:
8 * Copyright (C) 2007-2012 Daniel Wang
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22 #include <linux/clk.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/of_platform.h>
26 #include <linux/reset.h>
27 #include <media/rc-core.h>
28
29 #define SUNXI_IR_DEV "sunxi-ir"
30
31 /* Registers */
32 /* IR Control */
33 #define SUNXI_IR_CTL_REG 0x00
34 /* Global Enable */
35 #define REG_CTL_GEN BIT(0)
36 /* RX block enable */
37 #define REG_CTL_RXEN BIT(1)
38 /* CIR mode */
39 #define REG_CTL_MD (BIT(4) | BIT(5))
40
41 /* Rx Config */
42 #define SUNXI_IR_RXCTL_REG 0x10
43 /* Pulse Polarity Invert flag */
44 #define REG_RXCTL_RPPI BIT(2)
45
46 /* Rx Data */
47 #define SUNXI_IR_RXFIFO_REG 0x20
48
49 /* Rx Interrupt Enable */
50 #define SUNXI_IR_RXINT_REG 0x2C
51 /* Rx FIFO Overflow */
52 #define REG_RXINT_ROI_EN BIT(0)
53 /* Rx Packet End */
54 #define REG_RXINT_RPEI_EN BIT(1)
55 /* Rx FIFO Data Available */
56 #define REG_RXINT_RAI_EN BIT(4)
57
58 /* Rx FIFO available byte level */
59 #define REG_RXINT_RAL(val) ((val) << 8)
60
61 /* Rx Interrupt Status */
62 #define SUNXI_IR_RXSTA_REG 0x30
63 /* RX FIFO Get Available Counter */
64 #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
65 /* Clear all interrupt status value */
66 #define REG_RXSTA_CLEARALL 0xff
67
68 /* IR Sample Config */
69 #define SUNXI_IR_CIR_REG 0x34
70 /* CIR_REG register noise threshold */
71 #define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2)))
72 /* CIR_REG register idle threshold */
73 #define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
74
75 /* Required frequency for IR0 or IR1 clock in CIR mode */
76 #define SUNXI_IR_BASE_CLK 8000000
77 /* Frequency after IR internal divider */
78 #define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
79 /* Sample period in ns */
80 #define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK)
81 /* Noise threshold in samples */
82 #define SUNXI_IR_RXNOISE 1
83 /* Idle Threshold in samples */
84 #define SUNXI_IR_RXIDLE 20
85 /* Time after which device stops sending data in ms */
86 #define SUNXI_IR_TIMEOUT 120
87
88 struct sunxi_ir {
89 spinlock_t ir_lock;
90 struct rc_dev *rc;
91 void __iomem *base;
92 int irq;
93 int fifo_size;
94 struct clk *clk;
95 struct clk *apb_clk;
96 struct reset_control *rst;
97 const char *map_name;
98 };
99
sunxi_ir_irq(int irqno,void * dev_id)100 static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
101 {
102 unsigned long status;
103 unsigned char dt;
104 unsigned int cnt, rc;
105 struct sunxi_ir *ir = dev_id;
106 DEFINE_IR_RAW_EVENT(rawir);
107
108 spin_lock(&ir->ir_lock);
109
110 status = readl(ir->base + SUNXI_IR_RXSTA_REG);
111
112 /* clean all pending statuses */
113 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
114
115 if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
116 /* How many messages in fifo */
117 rc = REG_RXSTA_GET_AC(status);
118 /* Sanity check */
119 rc = rc > ir->fifo_size ? ir->fifo_size : rc;
120 /* If we have data */
121 for (cnt = 0; cnt < rc; cnt++) {
122 /* for each bit in fifo */
123 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
124 rawir.pulse = (dt & 0x80) != 0;
125 rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
126 ir_raw_event_store_with_filter(ir->rc, &rawir);
127 }
128 }
129
130 if (status & REG_RXINT_ROI_EN) {
131 ir_raw_event_reset(ir->rc);
132 } else if (status & REG_RXINT_RPEI_EN) {
133 ir_raw_event_set_idle(ir->rc, true);
134 ir_raw_event_handle(ir->rc);
135 } else {
136 ir_raw_event_handle(ir->rc);
137 }
138
139 spin_unlock(&ir->ir_lock);
140
141 return IRQ_HANDLED;
142 }
143
sunxi_ir_probe(struct platform_device * pdev)144 static int sunxi_ir_probe(struct platform_device *pdev)
145 {
146 int ret = 0;
147 unsigned long tmp = 0;
148
149 struct device *dev = &pdev->dev;
150 struct device_node *dn = dev->of_node;
151 struct resource *res;
152 struct sunxi_ir *ir;
153
154 ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
155 if (!ir)
156 return -ENOMEM;
157
158 spin_lock_init(&ir->ir_lock);
159
160 if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
161 ir->fifo_size = 64;
162 else
163 ir->fifo_size = 16;
164
165 /* Clock */
166 ir->apb_clk = devm_clk_get(dev, "apb");
167 if (IS_ERR(ir->apb_clk)) {
168 dev_err(dev, "failed to get a apb clock.\n");
169 return PTR_ERR(ir->apb_clk);
170 }
171 ir->clk = devm_clk_get(dev, "ir");
172 if (IS_ERR(ir->clk)) {
173 dev_err(dev, "failed to get a ir clock.\n");
174 return PTR_ERR(ir->clk);
175 }
176
177 /* Reset (optional) */
178 ir->rst = devm_reset_control_get_optional(dev, NULL);
179 if (IS_ERR(ir->rst)) {
180 ret = PTR_ERR(ir->rst);
181 if (ret == -EPROBE_DEFER)
182 return ret;
183 ir->rst = NULL;
184 } else {
185 ret = reset_control_deassert(ir->rst);
186 if (ret)
187 return ret;
188 }
189
190 ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
191 if (ret) {
192 dev_err(dev, "set ir base clock failed!\n");
193 goto exit_reset_assert;
194 }
195
196 if (clk_prepare_enable(ir->apb_clk)) {
197 dev_err(dev, "try to enable apb_ir_clk failed\n");
198 ret = -EINVAL;
199 goto exit_reset_assert;
200 }
201
202 if (clk_prepare_enable(ir->clk)) {
203 dev_err(dev, "try to enable ir_clk failed\n");
204 ret = -EINVAL;
205 goto exit_clkdisable_apb_clk;
206 }
207
208 /* IO */
209 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
210 ir->base = devm_ioremap_resource(dev, res);
211 if (IS_ERR(ir->base)) {
212 dev_err(dev, "failed to map registers\n");
213 ret = PTR_ERR(ir->base);
214 goto exit_clkdisable_clk;
215 }
216
217 ir->rc = rc_allocate_device();
218 if (!ir->rc) {
219 dev_err(dev, "failed to allocate device\n");
220 ret = -ENOMEM;
221 goto exit_clkdisable_clk;
222 }
223
224 ir->rc->priv = ir;
225 ir->rc->input_name = SUNXI_IR_DEV;
226 ir->rc->input_phys = "sunxi-ir/input0";
227 ir->rc->input_id.bustype = BUS_HOST;
228 ir->rc->input_id.vendor = 0x0001;
229 ir->rc->input_id.product = 0x0001;
230 ir->rc->input_id.version = 0x0100;
231 ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
232 ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
233 ir->rc->dev.parent = dev;
234 ir->rc->driver_type = RC_DRIVER_IR_RAW;
235 ir->rc->allowed_protocols = RC_BIT_ALL;
236 ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
237 ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
238 ir->rc->driver_name = SUNXI_IR_DEV;
239
240 ret = rc_register_device(ir->rc);
241 if (ret) {
242 dev_err(dev, "failed to register rc device\n");
243 goto exit_free_dev;
244 }
245
246 platform_set_drvdata(pdev, ir);
247
248 /* IRQ */
249 ir->irq = platform_get_irq(pdev, 0);
250 if (ir->irq < 0) {
251 dev_err(dev, "no irq resource\n");
252 ret = ir->irq;
253 goto exit_free_dev;
254 }
255
256 ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
257 if (ret) {
258 dev_err(dev, "failed request irq\n");
259 goto exit_free_dev;
260 }
261
262 /* Enable CIR Mode */
263 writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
264
265 /* Set noise threshold and idle threshold */
266 writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE),
267 ir->base + SUNXI_IR_CIR_REG);
268
269 /* Invert Input Signal */
270 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
271
272 /* Clear All Rx Interrupt Status */
273 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
274
275 /*
276 * Enable IRQ on overflow, packet end, FIFO available with trigger
277 * level
278 */
279 writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
280 REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
281 ir->base + SUNXI_IR_RXINT_REG);
282
283 /* Enable IR Module */
284 tmp = readl(ir->base + SUNXI_IR_CTL_REG);
285 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
286
287 dev_info(dev, "initialized sunXi IR driver\n");
288 return 0;
289
290 exit_free_dev:
291 rc_free_device(ir->rc);
292 exit_clkdisable_clk:
293 clk_disable_unprepare(ir->clk);
294 exit_clkdisable_apb_clk:
295 clk_disable_unprepare(ir->apb_clk);
296 exit_reset_assert:
297 if (ir->rst)
298 reset_control_assert(ir->rst);
299
300 return ret;
301 }
302
sunxi_ir_remove(struct platform_device * pdev)303 static int sunxi_ir_remove(struct platform_device *pdev)
304 {
305 unsigned long flags;
306 struct sunxi_ir *ir = platform_get_drvdata(pdev);
307
308 clk_disable_unprepare(ir->clk);
309 clk_disable_unprepare(ir->apb_clk);
310 if (ir->rst)
311 reset_control_assert(ir->rst);
312
313 spin_lock_irqsave(&ir->ir_lock, flags);
314 /* disable IR IRQ */
315 writel(0, ir->base + SUNXI_IR_RXINT_REG);
316 /* clear All Rx Interrupt Status */
317 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
318 /* disable IR */
319 writel(0, ir->base + SUNXI_IR_CTL_REG);
320 spin_unlock_irqrestore(&ir->ir_lock, flags);
321
322 rc_unregister_device(ir->rc);
323 return 0;
324 }
325
326 static const struct of_device_id sunxi_ir_match[] = {
327 { .compatible = "allwinner,sun4i-a10-ir", },
328 { .compatible = "allwinner,sun5i-a13-ir", },
329 {},
330 };
331
332 static struct platform_driver sunxi_ir_driver = {
333 .probe = sunxi_ir_probe,
334 .remove = sunxi_ir_remove,
335 .driver = {
336 .name = SUNXI_IR_DEV,
337 .of_match_table = sunxi_ir_match,
338 },
339 };
340
341 module_platform_driver(sunxi_ir_driver);
342
343 MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
344 MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
345 MODULE_LICENSE("GPL");
346