1 /*
2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/sort.h>
17
18 #include <soc/tegra/fuse.h>
19
20 #include "mc.h"
21
22 #define MC_INTSTATUS 0x000
23
24 #define MC_INTMASK 0x004
25
26 #define MC_ERR_STATUS 0x08
27 #define MC_ERR_STATUS_TYPE_SHIFT 28
28 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
29 #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
30 #define MC_ERR_STATUS_READABLE (1 << 27)
31 #define MC_ERR_STATUS_WRITABLE (1 << 26)
32 #define MC_ERR_STATUS_NONSECURE (1 << 25)
33 #define MC_ERR_STATUS_ADR_HI_SHIFT 20
34 #define MC_ERR_STATUS_ADR_HI_MASK 0x3
35 #define MC_ERR_STATUS_SECURITY (1 << 17)
36 #define MC_ERR_STATUS_RW (1 << 16)
37
38 #define MC_ERR_ADR 0x0c
39
40 #define MC_EMEM_ARB_CFG 0x90
41 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
42 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
43 #define MC_EMEM_ARB_MISC0 0xd8
44
45 #define MC_EMEM_ADR_CFG 0x54
46 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
47
48 static const struct of_device_id tegra_mc_of_match[] = {
49 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
50 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
51 #endif
52 #ifdef CONFIG_ARCH_TEGRA_114_SOC
53 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
54 #endif
55 #ifdef CONFIG_ARCH_TEGRA_124_SOC
56 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
57 #endif
58 #ifdef CONFIG_ARCH_TEGRA_132_SOC
59 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
60 #endif
61 #ifdef CONFIG_ARCH_TEGRA_210_SOC
62 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
63 #endif
64 { }
65 };
66 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
67
tegra_mc_setup_latency_allowance(struct tegra_mc * mc)68 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
69 {
70 unsigned long long tick;
71 unsigned int i;
72 u32 value;
73
74 /* compute the number of MC clock cycles per tick */
75 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
76 do_div(tick, NSEC_PER_SEC);
77
78 value = readl(mc->regs + MC_EMEM_ARB_CFG);
79 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
80 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
81 writel(value, mc->regs + MC_EMEM_ARB_CFG);
82
83 /* write latency allowance defaults */
84 for (i = 0; i < mc->soc->num_clients; i++) {
85 const struct tegra_mc_la *la = &mc->soc->clients[i].la;
86 u32 value;
87
88 value = readl(mc->regs + la->reg);
89 value &= ~(la->mask << la->shift);
90 value |= (la->def & la->mask) << la->shift;
91 writel(value, mc->regs + la->reg);
92 }
93
94 return 0;
95 }
96
tegra_mc_write_emem_configuration(struct tegra_mc * mc,unsigned long rate)97 void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
98 {
99 unsigned int i;
100 struct tegra_mc_timing *timing = NULL;
101
102 for (i = 0; i < mc->num_timings; i++) {
103 if (mc->timings[i].rate == rate) {
104 timing = &mc->timings[i];
105 break;
106 }
107 }
108
109 if (!timing) {
110 dev_err(mc->dev, "no memory timing registered for rate %lu\n",
111 rate);
112 return;
113 }
114
115 for (i = 0; i < mc->soc->num_emem_regs; ++i)
116 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
117 }
118
tegra_mc_get_emem_device_count(struct tegra_mc * mc)119 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
120 {
121 u8 dram_count;
122
123 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
124 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
125 dram_count++;
126
127 return dram_count;
128 }
129
load_one_timing(struct tegra_mc * mc,struct tegra_mc_timing * timing,struct device_node * node)130 static int load_one_timing(struct tegra_mc *mc,
131 struct tegra_mc_timing *timing,
132 struct device_node *node)
133 {
134 int err;
135 u32 tmp;
136
137 err = of_property_read_u32(node, "clock-frequency", &tmp);
138 if (err) {
139 dev_err(mc->dev,
140 "timing %s: failed to read rate\n", node->name);
141 return err;
142 }
143
144 timing->rate = tmp;
145 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
146 sizeof(u32), GFP_KERNEL);
147 if (!timing->emem_data)
148 return -ENOMEM;
149
150 err = of_property_read_u32_array(node, "nvidia,emem-configuration",
151 timing->emem_data,
152 mc->soc->num_emem_regs);
153 if (err) {
154 dev_err(mc->dev,
155 "timing %s: failed to read EMEM configuration\n",
156 node->name);
157 return err;
158 }
159
160 return 0;
161 }
162
load_timings(struct tegra_mc * mc,struct device_node * node)163 static int load_timings(struct tegra_mc *mc, struct device_node *node)
164 {
165 struct device_node *child;
166 struct tegra_mc_timing *timing;
167 int child_count = of_get_child_count(node);
168 int i = 0, err;
169
170 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
171 GFP_KERNEL);
172 if (!mc->timings)
173 return -ENOMEM;
174
175 mc->num_timings = child_count;
176
177 for_each_child_of_node(node, child) {
178 timing = &mc->timings[i++];
179
180 err = load_one_timing(mc, timing, child);
181 if (err)
182 return err;
183 }
184
185 return 0;
186 }
187
tegra_mc_setup_timings(struct tegra_mc * mc)188 static int tegra_mc_setup_timings(struct tegra_mc *mc)
189 {
190 struct device_node *node;
191 u32 ram_code, node_ram_code;
192 int err;
193
194 ram_code = tegra_read_ram_code();
195
196 mc->num_timings = 0;
197
198 for_each_child_of_node(mc->dev->of_node, node) {
199 err = of_property_read_u32(node, "nvidia,ram-code",
200 &node_ram_code);
201 if (err || (node_ram_code != ram_code)) {
202 of_node_put(node);
203 continue;
204 }
205
206 err = load_timings(mc, node);
207 if (err)
208 return err;
209 of_node_put(node);
210 break;
211 }
212
213 if (mc->num_timings == 0)
214 dev_warn(mc->dev,
215 "no memory timings for RAM code %u registered\n",
216 ram_code);
217
218 return 0;
219 }
220
221 static const char *const status_names[32] = {
222 [ 1] = "External interrupt",
223 [ 6] = "EMEM address decode error",
224 [ 8] = "Security violation",
225 [ 9] = "EMEM arbitration error",
226 [10] = "Page fault",
227 [11] = "Invalid APB ASID update",
228 [12] = "VPR violation",
229 [13] = "Secure carveout violation",
230 [16] = "MTS carveout violation",
231 };
232
233 static const char *const error_names[8] = {
234 [2] = "EMEM decode error",
235 [3] = "TrustZone violation",
236 [4] = "Carveout violation",
237 [6] = "SMMU translation error",
238 };
239
tegra_mc_irq(int irq,void * data)240 static irqreturn_t tegra_mc_irq(int irq, void *data)
241 {
242 struct tegra_mc *mc = data;
243 unsigned long status;
244 unsigned int bit;
245
246 /* mask all interrupts to avoid flooding */
247 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
248 if (!status)
249 return IRQ_NONE;
250
251 for_each_set_bit(bit, &status, 32) {
252 const char *error = status_names[bit] ?: "unknown";
253 const char *client = "unknown", *desc;
254 const char *direction, *secure;
255 phys_addr_t addr = 0;
256 unsigned int i;
257 char perm[7];
258 u8 id, type;
259 u32 value;
260
261 value = mc_readl(mc, MC_ERR_STATUS);
262
263 #ifdef CONFIG_PHYS_ADDR_T_64BIT
264 if (mc->soc->num_address_bits > 32) {
265 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
266 MC_ERR_STATUS_ADR_HI_MASK);
267 addr <<= 32;
268 }
269 #endif
270
271 if (value & MC_ERR_STATUS_RW)
272 direction = "write";
273 else
274 direction = "read";
275
276 if (value & MC_ERR_STATUS_SECURITY)
277 secure = "secure ";
278 else
279 secure = "";
280
281 id = value & mc->soc->client_id_mask;
282
283 for (i = 0; i < mc->soc->num_clients; i++) {
284 if (mc->soc->clients[i].id == id) {
285 client = mc->soc->clients[i].name;
286 break;
287 }
288 }
289
290 type = (value & MC_ERR_STATUS_TYPE_MASK) >>
291 MC_ERR_STATUS_TYPE_SHIFT;
292 desc = error_names[type];
293
294 switch (value & MC_ERR_STATUS_TYPE_MASK) {
295 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
296 perm[0] = ' ';
297 perm[1] = '[';
298
299 if (value & MC_ERR_STATUS_READABLE)
300 perm[2] = 'R';
301 else
302 perm[2] = '-';
303
304 if (value & MC_ERR_STATUS_WRITABLE)
305 perm[3] = 'W';
306 else
307 perm[3] = '-';
308
309 if (value & MC_ERR_STATUS_NONSECURE)
310 perm[4] = '-';
311 else
312 perm[4] = 'S';
313
314 perm[5] = ']';
315 perm[6] = '\0';
316 break;
317
318 default:
319 perm[0] = '\0';
320 break;
321 }
322
323 value = mc_readl(mc, MC_ERR_ADR);
324 addr |= value;
325
326 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
327 client, secure, direction, &addr, error,
328 desc, perm);
329 }
330
331 /* clear interrupts */
332 mc_writel(mc, status, MC_INTSTATUS);
333
334 return IRQ_HANDLED;
335 }
336
tegra_mc_probe(struct platform_device * pdev)337 static int tegra_mc_probe(struct platform_device *pdev)
338 {
339 const struct of_device_id *match;
340 struct resource *res;
341 struct tegra_mc *mc;
342 int err;
343
344 match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
345 if (!match)
346 return -ENODEV;
347
348 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
349 if (!mc)
350 return -ENOMEM;
351
352 platform_set_drvdata(pdev, mc);
353 mc->soc = match->data;
354 mc->dev = &pdev->dev;
355
356 /* length of MC tick in nanoseconds */
357 mc->tick = 30;
358
359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 mc->regs = devm_ioremap_resource(&pdev->dev, res);
361 if (IS_ERR(mc->regs))
362 return PTR_ERR(mc->regs);
363
364 mc->clk = devm_clk_get(&pdev->dev, "mc");
365 if (IS_ERR(mc->clk)) {
366 dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
367 PTR_ERR(mc->clk));
368 return PTR_ERR(mc->clk);
369 }
370
371 err = tegra_mc_setup_latency_allowance(mc);
372 if (err < 0) {
373 dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
374 err);
375 return err;
376 }
377
378 err = tegra_mc_setup_timings(mc);
379 if (err < 0) {
380 dev_err(&pdev->dev, "failed to setup timings: %d\n", err);
381 return err;
382 }
383
384 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
385 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
386 if (IS_ERR(mc->smmu)) {
387 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
388 PTR_ERR(mc->smmu));
389 return PTR_ERR(mc->smmu);
390 }
391 }
392
393 mc->irq = platform_get_irq(pdev, 0);
394 if (mc->irq < 0) {
395 dev_err(&pdev->dev, "interrupt not specified\n");
396 return mc->irq;
397 }
398
399 err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED,
400 dev_name(&pdev->dev), mc);
401 if (err < 0) {
402 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
403 err);
404 return err;
405 }
406
407 WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
408
409 mc_writel(mc, mc->soc->intmask, MC_INTMASK);
410
411 return 0;
412 }
413
414 static struct platform_driver tegra_mc_driver = {
415 .driver = {
416 .name = "tegra-mc",
417 .of_match_table = tegra_mc_of_match,
418 .suppress_bind_attrs = true,
419 },
420 .prevent_deferred_probe = true,
421 .probe = tegra_mc_probe,
422 };
423
tegra_mc_init(void)424 static int tegra_mc_init(void)
425 {
426 return platform_driver_register(&tegra_mc_driver);
427 }
428 arch_initcall(tegra_mc_init);
429
430 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
431 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
432 MODULE_LICENSE("GPL v2");
433