1 /*
2 *
3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16
17 #include <linux/pci.h>
18
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
21
22 #include "mei_dev.h"
23 #include "hbm.h"
24
25 #include "hw-me.h"
26 #include "hw-me-regs.h"
27
28 #include "mei-trace.h"
29
30 /**
31 * mei_me_reg_read - Reads 32bit data from the mei device
32 *
33 * @hw: the me hardware structure
34 * @offset: offset from which to read the data
35 *
36 * Return: register value (u32)
37 */
mei_me_reg_read(const struct mei_me_hw * hw,unsigned long offset)38 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
39 unsigned long offset)
40 {
41 return ioread32(hw->mem_addr + offset);
42 }
43
44
45 /**
46 * mei_me_reg_write - Writes 32bit data to the mei device
47 *
48 * @hw: the me hardware structure
49 * @offset: offset from which to write the data
50 * @value: register value to write (u32)
51 */
mei_me_reg_write(const struct mei_me_hw * hw,unsigned long offset,u32 value)52 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
53 unsigned long offset, u32 value)
54 {
55 iowrite32(value, hw->mem_addr + offset);
56 }
57
58 /**
59 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
60 * read window register
61 *
62 * @dev: the device structure
63 *
64 * Return: ME_CB_RW register value (u32)
65 */
mei_me_mecbrw_read(const struct mei_device * dev)66 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
67 {
68 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
69 }
70
71 /**
72 * mei_me_hcbww_write - write 32bit data to the host circular buffer
73 *
74 * @dev: the device structure
75 * @data: 32bit data to be written to the host circular buffer
76 */
mei_me_hcbww_write(struct mei_device * dev,u32 data)77 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
78 {
79 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);
80 }
81
82 /**
83 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
84 *
85 * @dev: the device structure
86 *
87 * Return: ME_CSR_HA register value (u32)
88 */
mei_me_mecsr_read(const struct mei_device * dev)89 static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
90 {
91 u32 reg;
92
93 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
94 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg);
95
96 return reg;
97 }
98
99 /**
100 * mei_hcsr_read - Reads 32bit data from the host CSR
101 *
102 * @dev: the device structure
103 *
104 * Return: H_CSR register value (u32)
105 */
mei_hcsr_read(const struct mei_device * dev)106 static inline u32 mei_hcsr_read(const struct mei_device *dev)
107 {
108 u32 reg;
109
110 reg = mei_me_reg_read(to_me_hw(dev), H_CSR);
111 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg);
112
113 return reg;
114 }
115
116 /**
117 * mei_hcsr_write - writes H_CSR register to the mei device
118 *
119 * @dev: the device structure
120 * @reg: new register value
121 */
mei_hcsr_write(struct mei_device * dev,u32 reg)122 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
123 {
124 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg);
125 mei_me_reg_write(to_me_hw(dev), H_CSR, reg);
126 }
127
128 /**
129 * mei_hcsr_set - writes H_CSR register to the mei device,
130 * and ignores the H_IS bit for it is write-one-to-zero.
131 *
132 * @dev: the device structure
133 * @reg: new register value
134 */
mei_hcsr_set(struct mei_device * dev,u32 reg)135 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
136 {
137 reg &= ~H_CSR_IS_MASK;
138 mei_hcsr_write(dev, reg);
139 }
140
141 /**
142 * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register
143 *
144 * @dev: the device structure
145 *
146 * Return: H_D0I3C register value (u32)
147 */
mei_me_d0i3c_read(const struct mei_device * dev)148 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev)
149 {
150 u32 reg;
151
152 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C);
153 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg);
154
155 return reg;
156 }
157
158 /**
159 * mei_me_d0i3c_write - writes H_D0I3C register to device
160 *
161 * @dev: the device structure
162 * @reg: new register value
163 */
mei_me_d0i3c_write(struct mei_device * dev,u32 reg)164 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg)
165 {
166 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg);
167 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg);
168 }
169
170 /**
171 * mei_me_fw_status - read fw status register from pci config space
172 *
173 * @dev: mei device
174 * @fw_status: fw status register values
175 *
176 * Return: 0 on success, error otherwise
177 */
mei_me_fw_status(struct mei_device * dev,struct mei_fw_status * fw_status)178 static int mei_me_fw_status(struct mei_device *dev,
179 struct mei_fw_status *fw_status)
180 {
181 struct pci_dev *pdev = to_pci_dev(dev->dev);
182 struct mei_me_hw *hw = to_me_hw(dev);
183 const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
184 int ret;
185 int i;
186
187 if (!fw_status)
188 return -EINVAL;
189
190 fw_status->count = fw_src->count;
191 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
192 ret = pci_read_config_dword(pdev,
193 fw_src->status[i], &fw_status->status[i]);
194 if (ret)
195 return ret;
196 }
197
198 return 0;
199 }
200
201 /**
202 * mei_me_hw_config - configure hw dependent settings
203 *
204 * @dev: mei device
205 */
mei_me_hw_config(struct mei_device * dev)206 static void mei_me_hw_config(struct mei_device *dev)
207 {
208 struct pci_dev *pdev = to_pci_dev(dev->dev);
209 struct mei_me_hw *hw = to_me_hw(dev);
210 u32 hcsr, reg;
211
212 /* Doesn't change in runtime */
213 hcsr = mei_hcsr_read(dev);
214 dev->hbuf_depth = (hcsr & H_CBD) >> 24;
215
216 reg = 0;
217 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
218 hw->d0i3_supported =
219 ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
220
221 hw->pg_state = MEI_PG_OFF;
222 if (hw->d0i3_supported) {
223 reg = mei_me_d0i3c_read(dev);
224 if (reg & H_D0I3C_I3)
225 hw->pg_state = MEI_PG_ON;
226 }
227 }
228
229 /**
230 * mei_me_pg_state - translate internal pg state
231 * to the mei power gating state
232 *
233 * @dev: mei device
234 *
235 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
236 */
mei_me_pg_state(struct mei_device * dev)237 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
238 {
239 struct mei_me_hw *hw = to_me_hw(dev);
240
241 return hw->pg_state;
242 }
243
244 /**
245 * mei_me_intr_clear - clear and stop interrupts
246 *
247 * @dev: the device structure
248 */
mei_me_intr_clear(struct mei_device * dev)249 static void mei_me_intr_clear(struct mei_device *dev)
250 {
251 u32 hcsr = mei_hcsr_read(dev);
252
253 if (hcsr & H_CSR_IS_MASK)
254 mei_hcsr_write(dev, hcsr);
255 }
256 /**
257 * mei_me_intr_enable - enables mei device interrupts
258 *
259 * @dev: the device structure
260 */
mei_me_intr_enable(struct mei_device * dev)261 static void mei_me_intr_enable(struct mei_device *dev)
262 {
263 u32 hcsr = mei_hcsr_read(dev);
264
265 hcsr |= H_CSR_IE_MASK;
266 mei_hcsr_set(dev, hcsr);
267 }
268
269 /**
270 * mei_me_intr_disable - disables mei device interrupts
271 *
272 * @dev: the device structure
273 */
mei_me_intr_disable(struct mei_device * dev)274 static void mei_me_intr_disable(struct mei_device *dev)
275 {
276 u32 hcsr = mei_hcsr_read(dev);
277
278 hcsr &= ~H_CSR_IE_MASK;
279 mei_hcsr_set(dev, hcsr);
280 }
281
282 /**
283 * mei_me_hw_reset_release - release device from the reset
284 *
285 * @dev: the device structure
286 */
mei_me_hw_reset_release(struct mei_device * dev)287 static void mei_me_hw_reset_release(struct mei_device *dev)
288 {
289 u32 hcsr = mei_hcsr_read(dev);
290
291 hcsr |= H_IG;
292 hcsr &= ~H_RST;
293 mei_hcsr_set(dev, hcsr);
294
295 /* complete this write before we set host ready on another CPU */
296 mmiowb();
297 }
298
299 /**
300 * mei_me_host_set_ready - enable device
301 *
302 * @dev: mei device
303 */
mei_me_host_set_ready(struct mei_device * dev)304 static void mei_me_host_set_ready(struct mei_device *dev)
305 {
306 u32 hcsr = mei_hcsr_read(dev);
307
308 hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
309 mei_hcsr_set(dev, hcsr);
310 }
311
312 /**
313 * mei_me_host_is_ready - check whether the host has turned ready
314 *
315 * @dev: mei device
316 * Return: bool
317 */
mei_me_host_is_ready(struct mei_device * dev)318 static bool mei_me_host_is_ready(struct mei_device *dev)
319 {
320 u32 hcsr = mei_hcsr_read(dev);
321
322 return (hcsr & H_RDY) == H_RDY;
323 }
324
325 /**
326 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
327 *
328 * @dev: mei device
329 * Return: bool
330 */
mei_me_hw_is_ready(struct mei_device * dev)331 static bool mei_me_hw_is_ready(struct mei_device *dev)
332 {
333 u32 mecsr = mei_me_mecsr_read(dev);
334
335 return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
336 }
337
338 /**
339 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
340 * or timeout is reached
341 *
342 * @dev: mei device
343 * Return: 0 on success, error otherwise
344 */
mei_me_hw_ready_wait(struct mei_device * dev)345 static int mei_me_hw_ready_wait(struct mei_device *dev)
346 {
347 mutex_unlock(&dev->device_lock);
348 wait_event_timeout(dev->wait_hw_ready,
349 dev->recvd_hw_ready,
350 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
351 mutex_lock(&dev->device_lock);
352 if (!dev->recvd_hw_ready) {
353 dev_err(dev->dev, "wait hw ready failed\n");
354 return -ETIME;
355 }
356
357 mei_me_hw_reset_release(dev);
358 dev->recvd_hw_ready = false;
359 return 0;
360 }
361
362 /**
363 * mei_me_hw_start - hw start routine
364 *
365 * @dev: mei device
366 * Return: 0 on success, error otherwise
367 */
mei_me_hw_start(struct mei_device * dev)368 static int mei_me_hw_start(struct mei_device *dev)
369 {
370 int ret = mei_me_hw_ready_wait(dev);
371
372 if (ret)
373 return ret;
374 dev_dbg(dev->dev, "hw is ready\n");
375
376 mei_me_host_set_ready(dev);
377 return ret;
378 }
379
380
381 /**
382 * mei_hbuf_filled_slots - gets number of device filled buffer slots
383 *
384 * @dev: the device structure
385 *
386 * Return: number of filled slots
387 */
mei_hbuf_filled_slots(struct mei_device * dev)388 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
389 {
390 u32 hcsr;
391 char read_ptr, write_ptr;
392
393 hcsr = mei_hcsr_read(dev);
394
395 read_ptr = (char) ((hcsr & H_CBRP) >> 8);
396 write_ptr = (char) ((hcsr & H_CBWP) >> 16);
397
398 return (unsigned char) (write_ptr - read_ptr);
399 }
400
401 /**
402 * mei_me_hbuf_is_empty - checks if host buffer is empty.
403 *
404 * @dev: the device structure
405 *
406 * Return: true if empty, false - otherwise.
407 */
mei_me_hbuf_is_empty(struct mei_device * dev)408 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
409 {
410 return mei_hbuf_filled_slots(dev) == 0;
411 }
412
413 /**
414 * mei_me_hbuf_empty_slots - counts write empty slots.
415 *
416 * @dev: the device structure
417 *
418 * Return: -EOVERFLOW if overflow, otherwise empty slots count
419 */
mei_me_hbuf_empty_slots(struct mei_device * dev)420 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
421 {
422 unsigned char filled_slots, empty_slots;
423
424 filled_slots = mei_hbuf_filled_slots(dev);
425 empty_slots = dev->hbuf_depth - filled_slots;
426
427 /* check for overflow */
428 if (filled_slots > dev->hbuf_depth)
429 return -EOVERFLOW;
430
431 return empty_slots;
432 }
433
434 /**
435 * mei_me_hbuf_max_len - returns size of hw buffer.
436 *
437 * @dev: the device structure
438 *
439 * Return: size of hw buffer in bytes
440 */
mei_me_hbuf_max_len(const struct mei_device * dev)441 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
442 {
443 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
444 }
445
446
447 /**
448 * mei_me_write_message - writes a message to mei device.
449 *
450 * @dev: the device structure
451 * @header: mei HECI header of message
452 * @buf: message payload will be written
453 *
454 * Return: -EIO if write has failed
455 */
mei_me_write_message(struct mei_device * dev,struct mei_msg_hdr * header,unsigned char * buf)456 static int mei_me_write_message(struct mei_device *dev,
457 struct mei_msg_hdr *header,
458 unsigned char *buf)
459 {
460 unsigned long rem;
461 unsigned long length = header->length;
462 u32 *reg_buf = (u32 *)buf;
463 u32 hcsr;
464 u32 dw_cnt;
465 int i;
466 int empty_slots;
467
468 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
469
470 empty_slots = mei_hbuf_empty_slots(dev);
471 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);
472
473 dw_cnt = mei_data2slots(length);
474 if (empty_slots < 0 || dw_cnt > empty_slots)
475 return -EMSGSIZE;
476
477 mei_me_hcbww_write(dev, *((u32 *) header));
478
479 for (i = 0; i < length / 4; i++)
480 mei_me_hcbww_write(dev, reg_buf[i]);
481
482 rem = length & 0x3;
483 if (rem > 0) {
484 u32 reg = 0;
485
486 memcpy(®, &buf[length - rem], rem);
487 mei_me_hcbww_write(dev, reg);
488 }
489
490 hcsr = mei_hcsr_read(dev) | H_IG;
491 mei_hcsr_set(dev, hcsr);
492 if (!mei_me_hw_is_ready(dev))
493 return -EIO;
494
495 return 0;
496 }
497
498 /**
499 * mei_me_count_full_read_slots - counts read full slots.
500 *
501 * @dev: the device structure
502 *
503 * Return: -EOVERFLOW if overflow, otherwise filled slots count
504 */
mei_me_count_full_read_slots(struct mei_device * dev)505 static int mei_me_count_full_read_slots(struct mei_device *dev)
506 {
507 u32 me_csr;
508 char read_ptr, write_ptr;
509 unsigned char buffer_depth, filled_slots;
510
511 me_csr = mei_me_mecsr_read(dev);
512 buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
513 read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
514 write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
515 filled_slots = (unsigned char) (write_ptr - read_ptr);
516
517 /* check for overflow */
518 if (filled_slots > buffer_depth)
519 return -EOVERFLOW;
520
521 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
522 return (int)filled_slots;
523 }
524
525 /**
526 * mei_me_read_slots - reads a message from mei device.
527 *
528 * @dev: the device structure
529 * @buffer: message buffer will be written
530 * @buffer_length: message size will be read
531 *
532 * Return: always 0
533 */
mei_me_read_slots(struct mei_device * dev,unsigned char * buffer,unsigned long buffer_length)534 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
535 unsigned long buffer_length)
536 {
537 u32 *reg_buf = (u32 *)buffer;
538 u32 hcsr;
539
540 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
541 *reg_buf++ = mei_me_mecbrw_read(dev);
542
543 if (buffer_length > 0) {
544 u32 reg = mei_me_mecbrw_read(dev);
545
546 memcpy(reg_buf, ®, buffer_length);
547 }
548
549 hcsr = mei_hcsr_read(dev) | H_IG;
550 mei_hcsr_set(dev, hcsr);
551 return 0;
552 }
553
554 /**
555 * mei_me_pg_set - write pg enter register
556 *
557 * @dev: the device structure
558 */
mei_me_pg_set(struct mei_device * dev)559 static void mei_me_pg_set(struct mei_device *dev)
560 {
561 struct mei_me_hw *hw = to_me_hw(dev);
562 u32 reg;
563
564 reg = mei_me_reg_read(hw, H_HPG_CSR);
565 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
566
567 reg |= H_HPG_CSR_PGI;
568
569 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
570 mei_me_reg_write(hw, H_HPG_CSR, reg);
571 }
572
573 /**
574 * mei_me_pg_unset - write pg exit register
575 *
576 * @dev: the device structure
577 */
mei_me_pg_unset(struct mei_device * dev)578 static void mei_me_pg_unset(struct mei_device *dev)
579 {
580 struct mei_me_hw *hw = to_me_hw(dev);
581 u32 reg;
582
583 reg = mei_me_reg_read(hw, H_HPG_CSR);
584 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
585
586 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
587
588 reg |= H_HPG_CSR_PGIHEXR;
589
590 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
591 mei_me_reg_write(hw, H_HPG_CSR, reg);
592 }
593
594 /**
595 * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure
596 *
597 * @dev: the device structure
598 *
599 * Return: 0 on success an error code otherwise
600 */
mei_me_pg_legacy_enter_sync(struct mei_device * dev)601 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
602 {
603 struct mei_me_hw *hw = to_me_hw(dev);
604 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
605 int ret;
606
607 dev->pg_event = MEI_PG_EVENT_WAIT;
608
609 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
610 if (ret)
611 return ret;
612
613 mutex_unlock(&dev->device_lock);
614 wait_event_timeout(dev->wait_pg,
615 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
616 mutex_lock(&dev->device_lock);
617
618 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
619 mei_me_pg_set(dev);
620 ret = 0;
621 } else {
622 ret = -ETIME;
623 }
624
625 dev->pg_event = MEI_PG_EVENT_IDLE;
626 hw->pg_state = MEI_PG_ON;
627
628 return ret;
629 }
630
631 /**
632 * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure
633 *
634 * @dev: the device structure
635 *
636 * Return: 0 on success an error code otherwise
637 */
mei_me_pg_legacy_exit_sync(struct mei_device * dev)638 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
639 {
640 struct mei_me_hw *hw = to_me_hw(dev);
641 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
642 int ret;
643
644 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
645 goto reply;
646
647 dev->pg_event = MEI_PG_EVENT_WAIT;
648
649 mei_me_pg_unset(dev);
650
651 mutex_unlock(&dev->device_lock);
652 wait_event_timeout(dev->wait_pg,
653 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
654 mutex_lock(&dev->device_lock);
655
656 reply:
657 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
658 ret = -ETIME;
659 goto out;
660 }
661
662 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
663 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
664 if (ret)
665 return ret;
666
667 mutex_unlock(&dev->device_lock);
668 wait_event_timeout(dev->wait_pg,
669 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
670 mutex_lock(&dev->device_lock);
671
672 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
673 ret = 0;
674 else
675 ret = -ETIME;
676
677 out:
678 dev->pg_event = MEI_PG_EVENT_IDLE;
679 hw->pg_state = MEI_PG_OFF;
680
681 return ret;
682 }
683
684 /**
685 * mei_me_pg_in_transition - is device now in pg transition
686 *
687 * @dev: the device structure
688 *
689 * Return: true if in pg transition, false otherwise
690 */
mei_me_pg_in_transition(struct mei_device * dev)691 static bool mei_me_pg_in_transition(struct mei_device *dev)
692 {
693 return dev->pg_event >= MEI_PG_EVENT_WAIT &&
694 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;
695 }
696
697 /**
698 * mei_me_pg_is_enabled - detect if PG is supported by HW
699 *
700 * @dev: the device structure
701 *
702 * Return: true is pg supported, false otherwise
703 */
mei_me_pg_is_enabled(struct mei_device * dev)704 static bool mei_me_pg_is_enabled(struct mei_device *dev)
705 {
706 struct mei_me_hw *hw = to_me_hw(dev);
707 u32 reg = mei_me_mecsr_read(dev);
708
709 if (hw->d0i3_supported)
710 return true;
711
712 if ((reg & ME_PGIC_HRA) == 0)
713 goto notsupported;
714
715 if (!dev->hbm_f_pg_supported)
716 goto notsupported;
717
718 return true;
719
720 notsupported:
721 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n",
722 hw->d0i3_supported,
723 !!(reg & ME_PGIC_HRA),
724 dev->version.major_version,
725 dev->version.minor_version,
726 HBM_MAJOR_VERSION_PGI,
727 HBM_MINOR_VERSION_PGI);
728
729 return false;
730 }
731
732 /**
733 * mei_me_d0i3_set - write d0i3 register bit on mei device.
734 *
735 * @dev: the device structure
736 * @intr: ask for interrupt
737 *
738 * Return: D0I3C register value
739 */
mei_me_d0i3_set(struct mei_device * dev,bool intr)740 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr)
741 {
742 u32 reg = mei_me_d0i3c_read(dev);
743
744 reg |= H_D0I3C_I3;
745 if (intr)
746 reg |= H_D0I3C_IR;
747 else
748 reg &= ~H_D0I3C_IR;
749 mei_me_d0i3c_write(dev, reg);
750 /* read it to ensure HW consistency */
751 reg = mei_me_d0i3c_read(dev);
752 return reg;
753 }
754
755 /**
756 * mei_me_d0i3_unset - clean d0i3 register bit on mei device.
757 *
758 * @dev: the device structure
759 *
760 * Return: D0I3C register value
761 */
mei_me_d0i3_unset(struct mei_device * dev)762 static u32 mei_me_d0i3_unset(struct mei_device *dev)
763 {
764 u32 reg = mei_me_d0i3c_read(dev);
765
766 reg &= ~H_D0I3C_I3;
767 reg |= H_D0I3C_IR;
768 mei_me_d0i3c_write(dev, reg);
769 /* read it to ensure HW consistency */
770 reg = mei_me_d0i3c_read(dev);
771 return reg;
772 }
773
774 /**
775 * mei_me_d0i3_enter_sync - perform d0i3 entry procedure
776 *
777 * @dev: the device structure
778 *
779 * Return: 0 on success an error code otherwise
780 */
mei_me_d0i3_enter_sync(struct mei_device * dev)781 static int mei_me_d0i3_enter_sync(struct mei_device *dev)
782 {
783 struct mei_me_hw *hw = to_me_hw(dev);
784 unsigned long d0i3_timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
785 unsigned long pgi_timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
786 int ret;
787 u32 reg;
788
789 reg = mei_me_d0i3c_read(dev);
790 if (reg & H_D0I3C_I3) {
791 /* we are in d0i3, nothing to do */
792 dev_dbg(dev->dev, "d0i3 set not needed\n");
793 ret = 0;
794 goto on;
795 }
796
797 /* PGI entry procedure */
798 dev->pg_event = MEI_PG_EVENT_WAIT;
799
800 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
801 if (ret)
802 /* FIXME: should we reset here? */
803 goto out;
804
805 mutex_unlock(&dev->device_lock);
806 wait_event_timeout(dev->wait_pg,
807 dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout);
808 mutex_lock(&dev->device_lock);
809
810 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
811 ret = -ETIME;
812 goto out;
813 }
814 /* end PGI entry procedure */
815
816 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
817
818 reg = mei_me_d0i3_set(dev, true);
819 if (!(reg & H_D0I3C_CIP)) {
820 dev_dbg(dev->dev, "d0i3 enter wait not needed\n");
821 ret = 0;
822 goto on;
823 }
824
825 mutex_unlock(&dev->device_lock);
826 wait_event_timeout(dev->wait_pg,
827 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout);
828 mutex_lock(&dev->device_lock);
829
830 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
831 reg = mei_me_d0i3c_read(dev);
832 if (!(reg & H_D0I3C_I3)) {
833 ret = -ETIME;
834 goto out;
835 }
836 }
837
838 ret = 0;
839 on:
840 hw->pg_state = MEI_PG_ON;
841 out:
842 dev->pg_event = MEI_PG_EVENT_IDLE;
843 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret);
844 return ret;
845 }
846
847 /**
848 * mei_me_d0i3_enter - perform d0i3 entry procedure
849 * no hbm PG handshake
850 * no waiting for confirmation; runs with interrupts
851 * disabled
852 *
853 * @dev: the device structure
854 *
855 * Return: 0 on success an error code otherwise
856 */
mei_me_d0i3_enter(struct mei_device * dev)857 static int mei_me_d0i3_enter(struct mei_device *dev)
858 {
859 struct mei_me_hw *hw = to_me_hw(dev);
860 u32 reg;
861
862 reg = mei_me_d0i3c_read(dev);
863 if (reg & H_D0I3C_I3) {
864 /* we are in d0i3, nothing to do */
865 dev_dbg(dev->dev, "already d0i3 : set not needed\n");
866 goto on;
867 }
868
869 mei_me_d0i3_set(dev, false);
870 on:
871 hw->pg_state = MEI_PG_ON;
872 dev->pg_event = MEI_PG_EVENT_IDLE;
873 dev_dbg(dev->dev, "d0i3 enter\n");
874 return 0;
875 }
876
877 /**
878 * mei_me_d0i3_exit_sync - perform d0i3 exit procedure
879 *
880 * @dev: the device structure
881 *
882 * Return: 0 on success an error code otherwise
883 */
mei_me_d0i3_exit_sync(struct mei_device * dev)884 static int mei_me_d0i3_exit_sync(struct mei_device *dev)
885 {
886 struct mei_me_hw *hw = to_me_hw(dev);
887 unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
888 int ret;
889 u32 reg;
890
891 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
892
893 reg = mei_me_d0i3c_read(dev);
894 if (!(reg & H_D0I3C_I3)) {
895 /* we are not in d0i3, nothing to do */
896 dev_dbg(dev->dev, "d0i3 exit not needed\n");
897 ret = 0;
898 goto off;
899 }
900
901 reg = mei_me_d0i3_unset(dev);
902 if (!(reg & H_D0I3C_CIP)) {
903 dev_dbg(dev->dev, "d0i3 exit wait not needed\n");
904 ret = 0;
905 goto off;
906 }
907
908 mutex_unlock(&dev->device_lock);
909 wait_event_timeout(dev->wait_pg,
910 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
911 mutex_lock(&dev->device_lock);
912
913 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
914 reg = mei_me_d0i3c_read(dev);
915 if (reg & H_D0I3C_I3) {
916 ret = -ETIME;
917 goto out;
918 }
919 }
920
921 ret = 0;
922 off:
923 hw->pg_state = MEI_PG_OFF;
924 out:
925 dev->pg_event = MEI_PG_EVENT_IDLE;
926
927 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret);
928 return ret;
929 }
930
931 /**
932 * mei_me_pg_legacy_intr - perform legacy pg processing
933 * in interrupt thread handler
934 *
935 * @dev: the device structure
936 */
mei_me_pg_legacy_intr(struct mei_device * dev)937 static void mei_me_pg_legacy_intr(struct mei_device *dev)
938 {
939 struct mei_me_hw *hw = to_me_hw(dev);
940
941 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)
942 return;
943
944 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
945 hw->pg_state = MEI_PG_OFF;
946 if (waitqueue_active(&dev->wait_pg))
947 wake_up(&dev->wait_pg);
948 }
949
950 /**
951 * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler
952 *
953 * @dev: the device structure
954 */
mei_me_d0i3_intr(struct mei_device * dev)955 static void mei_me_d0i3_intr(struct mei_device *dev)
956 {
957 struct mei_me_hw *hw = to_me_hw(dev);
958
959 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT &&
960 (hw->intr_source & H_D0I3C_IS)) {
961 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
962 if (hw->pg_state == MEI_PG_ON) {
963 hw->pg_state = MEI_PG_OFF;
964 if (dev->hbm_state != MEI_HBM_IDLE) {
965 /*
966 * force H_RDY because it could be
967 * wiped off during PG
968 */
969 dev_dbg(dev->dev, "d0i3 set host ready\n");
970 mei_me_host_set_ready(dev);
971 }
972 } else {
973 hw->pg_state = MEI_PG_ON;
974 }
975
976 wake_up(&dev->wait_pg);
977 }
978
979 if (hw->pg_state == MEI_PG_ON && (hw->intr_source & H_IS)) {
980 /*
981 * HW sent some data and we are in D0i3, so
982 * we got here because of HW initiated exit from D0i3.
983 * Start runtime pm resume sequence to exit low power state.
984 */
985 dev_dbg(dev->dev, "d0i3 want resume\n");
986 mei_hbm_pg_resume(dev);
987 }
988 }
989
990 /**
991 * mei_me_pg_intr - perform pg processing in interrupt thread handler
992 *
993 * @dev: the device structure
994 */
mei_me_pg_intr(struct mei_device * dev)995 static void mei_me_pg_intr(struct mei_device *dev)
996 {
997 struct mei_me_hw *hw = to_me_hw(dev);
998
999 if (hw->d0i3_supported)
1000 mei_me_d0i3_intr(dev);
1001 else
1002 mei_me_pg_legacy_intr(dev);
1003 }
1004
1005 /**
1006 * mei_me_pg_enter_sync - perform runtime pm entry procedure
1007 *
1008 * @dev: the device structure
1009 *
1010 * Return: 0 on success an error code otherwise
1011 */
mei_me_pg_enter_sync(struct mei_device * dev)1012 int mei_me_pg_enter_sync(struct mei_device *dev)
1013 {
1014 struct mei_me_hw *hw = to_me_hw(dev);
1015
1016 if (hw->d0i3_supported)
1017 return mei_me_d0i3_enter_sync(dev);
1018 else
1019 return mei_me_pg_legacy_enter_sync(dev);
1020 }
1021
1022 /**
1023 * mei_me_pg_exit_sync - perform runtime pm exit procedure
1024 *
1025 * @dev: the device structure
1026 *
1027 * Return: 0 on success an error code otherwise
1028 */
mei_me_pg_exit_sync(struct mei_device * dev)1029 int mei_me_pg_exit_sync(struct mei_device *dev)
1030 {
1031 struct mei_me_hw *hw = to_me_hw(dev);
1032
1033 if (hw->d0i3_supported)
1034 return mei_me_d0i3_exit_sync(dev);
1035 else
1036 return mei_me_pg_legacy_exit_sync(dev);
1037 }
1038
1039 /**
1040 * mei_me_hw_reset - resets fw via mei csr register.
1041 *
1042 * @dev: the device structure
1043 * @intr_enable: if interrupt should be enabled after reset.
1044 *
1045 * Return: 0 on success an error code otherwise
1046 */
mei_me_hw_reset(struct mei_device * dev,bool intr_enable)1047 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
1048 {
1049 struct mei_me_hw *hw = to_me_hw(dev);
1050 int ret;
1051 u32 hcsr;
1052
1053 if (intr_enable) {
1054 mei_me_intr_enable(dev);
1055 if (hw->d0i3_supported) {
1056 ret = mei_me_d0i3_exit_sync(dev);
1057 if (ret)
1058 return ret;
1059 }
1060 }
1061
1062 hcsr = mei_hcsr_read(dev);
1063 /* H_RST may be found lit before reset is started,
1064 * for example if preceding reset flow hasn't completed.
1065 * In that case asserting H_RST will be ignored, therefore
1066 * we need to clean H_RST bit to start a successful reset sequence.
1067 */
1068 if ((hcsr & H_RST) == H_RST) {
1069 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
1070 hcsr &= ~H_RST;
1071 mei_hcsr_set(dev, hcsr);
1072 hcsr = mei_hcsr_read(dev);
1073 }
1074
1075 hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
1076
1077 if (!intr_enable)
1078 hcsr &= ~H_CSR_IE_MASK;
1079
1080 dev->recvd_hw_ready = false;
1081 mei_hcsr_write(dev, hcsr);
1082
1083 /*
1084 * Host reads the H_CSR once to ensure that the
1085 * posted write to H_CSR completes.
1086 */
1087 hcsr = mei_hcsr_read(dev);
1088
1089 if ((hcsr & H_RST) == 0)
1090 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
1091
1092 if ((hcsr & H_RDY) == H_RDY)
1093 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
1094
1095 if (!intr_enable) {
1096 mei_me_hw_reset_release(dev);
1097 if (hw->d0i3_supported) {
1098 ret = mei_me_d0i3_enter(dev);
1099 if (ret)
1100 return ret;
1101 }
1102 }
1103 return 0;
1104 }
1105
1106 /**
1107 * mei_me_irq_quick_handler - The ISR of the MEI device
1108 *
1109 * @irq: The irq number
1110 * @dev_id: pointer to the device structure
1111 *
1112 * Return: irqreturn_t
1113 */
mei_me_irq_quick_handler(int irq,void * dev_id)1114 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
1115 {
1116 struct mei_device *dev = (struct mei_device *)dev_id;
1117 struct mei_me_hw *hw = to_me_hw(dev);
1118 u32 hcsr;
1119
1120 hcsr = mei_hcsr_read(dev);
1121 if (!(hcsr & H_CSR_IS_MASK))
1122 return IRQ_NONE;
1123
1124 hw->intr_source = hcsr & H_CSR_IS_MASK;
1125 dev_dbg(dev->dev, "interrupt source 0x%08X.\n", hw->intr_source);
1126
1127 /* clear H_IS and H_D0I3C_IS bits in H_CSR to clear the interrupts */
1128 mei_hcsr_write(dev, hcsr);
1129
1130 return IRQ_WAKE_THREAD;
1131 }
1132
1133 /**
1134 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
1135 * processing.
1136 *
1137 * @irq: The irq number
1138 * @dev_id: pointer to the device structure
1139 *
1140 * Return: irqreturn_t
1141 *
1142 */
mei_me_irq_thread_handler(int irq,void * dev_id)1143 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
1144 {
1145 struct mei_device *dev = (struct mei_device *) dev_id;
1146 struct mei_cl_cb complete_list;
1147 s32 slots;
1148 int rets = 0;
1149
1150 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
1151 /* initialize our complete list */
1152 mutex_lock(&dev->device_lock);
1153 mei_io_list_init(&complete_list);
1154
1155 /* check if ME wants a reset */
1156 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
1157 dev_warn(dev->dev, "FW not ready: resetting.\n");
1158 schedule_work(&dev->reset_work);
1159 goto end;
1160 }
1161
1162 mei_me_pg_intr(dev);
1163
1164 /* check if we need to start the dev */
1165 if (!mei_host_is_ready(dev)) {
1166 if (mei_hw_is_ready(dev)) {
1167 dev_dbg(dev->dev, "we need to start the dev.\n");
1168 dev->recvd_hw_ready = true;
1169 wake_up(&dev->wait_hw_ready);
1170 } else {
1171 dev_dbg(dev->dev, "Spurious Interrupt\n");
1172 }
1173 goto end;
1174 }
1175 /* check slots available for reading */
1176 slots = mei_count_full_read_slots(dev);
1177 while (slots > 0) {
1178 dev_dbg(dev->dev, "slots to read = %08x\n", slots);
1179 rets = mei_irq_read_handler(dev, &complete_list, &slots);
1180 /* There is a race between ME write and interrupt delivery:
1181 * Not all data is always available immediately after the
1182 * interrupt, so try to read again on the next interrupt.
1183 */
1184 if (rets == -ENODATA)
1185 break;
1186
1187 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
1188 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n",
1189 rets);
1190 schedule_work(&dev->reset_work);
1191 goto end;
1192 }
1193 }
1194
1195 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1196
1197 /*
1198 * During PG handshake only allowed write is the replay to the
1199 * PG exit message, so block calling write function
1200 * if the pg event is in PG handshake
1201 */
1202 if (dev->pg_event != MEI_PG_EVENT_WAIT &&
1203 dev->pg_event != MEI_PG_EVENT_RECEIVED) {
1204 rets = mei_irq_write_handler(dev, &complete_list);
1205 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1206 }
1207
1208 mei_irq_compl_handler(dev, &complete_list);
1209
1210 end:
1211 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1212 mutex_unlock(&dev->device_lock);
1213 return IRQ_HANDLED;
1214 }
1215
1216 static const struct mei_hw_ops mei_me_hw_ops = {
1217
1218 .fw_status = mei_me_fw_status,
1219 .pg_state = mei_me_pg_state,
1220
1221 .host_is_ready = mei_me_host_is_ready,
1222
1223 .hw_is_ready = mei_me_hw_is_ready,
1224 .hw_reset = mei_me_hw_reset,
1225 .hw_config = mei_me_hw_config,
1226 .hw_start = mei_me_hw_start,
1227
1228 .pg_in_transition = mei_me_pg_in_transition,
1229 .pg_is_enabled = mei_me_pg_is_enabled,
1230
1231 .intr_clear = mei_me_intr_clear,
1232 .intr_enable = mei_me_intr_enable,
1233 .intr_disable = mei_me_intr_disable,
1234
1235 .hbuf_free_slots = mei_me_hbuf_empty_slots,
1236 .hbuf_is_ready = mei_me_hbuf_is_empty,
1237 .hbuf_max_len = mei_me_hbuf_max_len,
1238
1239 .write = mei_me_write_message,
1240
1241 .rdbuf_full_slots = mei_me_count_full_read_slots,
1242 .read_hdr = mei_me_mecbrw_read,
1243 .read = mei_me_read_slots
1244 };
1245
mei_me_fw_type_nm(struct pci_dev * pdev)1246 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
1247 {
1248 u32 reg;
1249
1250 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®);
1251 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
1252 return (reg & 0x600) == 0x200;
1253 }
1254
1255 #define MEI_CFG_FW_NM \
1256 .quirk_probe = mei_me_fw_type_nm
1257
mei_me_fw_type_sps(struct pci_dev * pdev)1258 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
1259 {
1260 u32 reg;
1261 unsigned int devfn;
1262
1263 /*
1264 * Read ME FW Status register to check for SPS Firmware
1265 * The SPS FW is only signaled in pci function 0
1266 */
1267 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1268 pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, ®);
1269 /* if bits [19:16] = 15, running SPS Firmware */
1270 return (reg & 0xf0000) == 0xf0000;
1271 }
1272
1273 #define MEI_CFG_FW_SPS \
1274 .quirk_probe = mei_me_fw_type_sps
1275
1276
1277 #define MEI_CFG_LEGACY_HFS \
1278 .fw_status.count = 0
1279
1280 #define MEI_CFG_ICH_HFS \
1281 .fw_status.count = 1, \
1282 .fw_status.status[0] = PCI_CFG_HFS_1
1283
1284 #define MEI_CFG_PCH_HFS \
1285 .fw_status.count = 2, \
1286 .fw_status.status[0] = PCI_CFG_HFS_1, \
1287 .fw_status.status[1] = PCI_CFG_HFS_2
1288
1289 #define MEI_CFG_PCH8_HFS \
1290 .fw_status.count = 6, \
1291 .fw_status.status[0] = PCI_CFG_HFS_1, \
1292 .fw_status.status[1] = PCI_CFG_HFS_2, \
1293 .fw_status.status[2] = PCI_CFG_HFS_3, \
1294 .fw_status.status[3] = PCI_CFG_HFS_4, \
1295 .fw_status.status[4] = PCI_CFG_HFS_5, \
1296 .fw_status.status[5] = PCI_CFG_HFS_6
1297
1298 /* ICH Legacy devices */
1299 const struct mei_cfg mei_me_legacy_cfg = {
1300 MEI_CFG_LEGACY_HFS,
1301 };
1302
1303 /* ICH devices */
1304 const struct mei_cfg mei_me_ich_cfg = {
1305 MEI_CFG_ICH_HFS,
1306 };
1307
1308 /* PCH devices */
1309 const struct mei_cfg mei_me_pch_cfg = {
1310 MEI_CFG_PCH_HFS,
1311 };
1312
1313
1314 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
1315 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
1316 MEI_CFG_PCH_HFS,
1317 MEI_CFG_FW_NM,
1318 };
1319
1320 /* PCH8 Lynx Point and newer devices */
1321 const struct mei_cfg mei_me_pch8_cfg = {
1322 MEI_CFG_PCH8_HFS,
1323 };
1324
1325 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
1326 const struct mei_cfg mei_me_pch8_sps_cfg = {
1327 MEI_CFG_PCH8_HFS,
1328 MEI_CFG_FW_SPS,
1329 };
1330
1331 /**
1332 * mei_me_dev_init - allocates and initializes the mei device structure
1333 *
1334 * @pdev: The pci device structure
1335 * @cfg: per device generation config
1336 *
1337 * Return: The mei_device_device pointer on success, NULL on failure.
1338 */
mei_me_dev_init(struct pci_dev * pdev,const struct mei_cfg * cfg)1339 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
1340 const struct mei_cfg *cfg)
1341 {
1342 struct mei_device *dev;
1343 struct mei_me_hw *hw;
1344
1345 dev = kzalloc(sizeof(struct mei_device) +
1346 sizeof(struct mei_me_hw), GFP_KERNEL);
1347 if (!dev)
1348 return NULL;
1349 hw = to_me_hw(dev);
1350
1351 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);
1352 hw->cfg = cfg;
1353 return dev;
1354 }
1355
1356