1 /*
2 *
3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/fs.h>
21 #include <linux/errno.h>
22 #include <linux/types.h>
23 #include <linux/fcntl.h>
24 #include <linux/pci.h>
25 #include <linux/poll.h>
26 #include <linux/ioctl.h>
27 #include <linux/cdev.h>
28 #include <linux/sched.h>
29 #include <linux/uuid.h>
30 #include <linux/compat.h>
31 #include <linux/jiffies.h>
32 #include <linux/interrupt.h>
33
34 #include <linux/pm_runtime.h>
35
36 #include <linux/mei.h>
37
38 #include "mei_dev.h"
39 #include "client.h"
40 #include "hw-me-regs.h"
41 #include "hw-me.h"
42
43 /* mei_pci_tbl - PCI Device ID Table */
44 static const struct pci_device_id mei_me_pci_tbl[] = {
45 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
50 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},
56
57 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
58 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
69 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},
70
71 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
76 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
77 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
79 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
80 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
81 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
82 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
83 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},
84
85 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
86 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
87 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_sps_cfg)},
88 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_sps_cfg)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, mei_me_pch8_cfg)},
90
91 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, mei_me_pch8_cfg)},
92 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, mei_me_pch8_cfg)},
93
94 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, mei_me_pch8_cfg)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, mei_me_pch8_cfg)},
96
97 /* required last entry */
98 {0, }
99 };
100
101 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
102
103 #ifdef CONFIG_PM
104 static inline void mei_me_set_pm_domain(struct mei_device *dev);
105 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
106 #else
mei_me_set_pm_domain(struct mei_device * dev)107 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
mei_me_unset_pm_domain(struct mei_device * dev)108 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
109 #endif /* CONFIG_PM */
110
111 /**
112 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
113 *
114 * @pdev: PCI device structure
115 * @cfg: per generation config
116 *
117 * Return: true if ME Interface is valid, false otherwise
118 */
mei_me_quirk_probe(struct pci_dev * pdev,const struct mei_cfg * cfg)119 static bool mei_me_quirk_probe(struct pci_dev *pdev,
120 const struct mei_cfg *cfg)
121 {
122 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
123 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
124 return false;
125 }
126
127 return true;
128 }
129
130 /**
131 * mei_me_probe - Device Initialization Routine
132 *
133 * @pdev: PCI device structure
134 * @ent: entry in kcs_pci_tbl
135 *
136 * Return: 0 on success, <0 on failure.
137 */
mei_me_probe(struct pci_dev * pdev,const struct pci_device_id * ent)138 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
139 {
140 const struct mei_cfg *cfg = (struct mei_cfg *)(ent->driver_data);
141 struct mei_device *dev;
142 struct mei_me_hw *hw;
143 unsigned int irqflags;
144 int err;
145
146
147 if (!mei_me_quirk_probe(pdev, cfg))
148 return -ENODEV;
149
150 /* enable pci dev */
151 err = pci_enable_device(pdev);
152 if (err) {
153 dev_err(&pdev->dev, "failed to enable pci device.\n");
154 goto end;
155 }
156 /* set PCI host mastering */
157 pci_set_master(pdev);
158 /* pci request regions for mei driver */
159 err = pci_request_regions(pdev, KBUILD_MODNAME);
160 if (err) {
161 dev_err(&pdev->dev, "failed to get pci regions.\n");
162 goto disable_device;
163 }
164
165 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
166 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
167
168 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
169 if (err)
170 err = dma_set_coherent_mask(&pdev->dev,
171 DMA_BIT_MASK(32));
172 }
173 if (err) {
174 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
175 goto release_regions;
176 }
177
178
179 /* allocates and initializes the mei dev structure */
180 dev = mei_me_dev_init(pdev, cfg);
181 if (!dev) {
182 err = -ENOMEM;
183 goto release_regions;
184 }
185 hw = to_me_hw(dev);
186 /* mapping IO device memory */
187 hw->mem_addr = pci_iomap(pdev, 0, 0);
188 if (!hw->mem_addr) {
189 dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
190 err = -ENOMEM;
191 goto free_device;
192 }
193 pci_enable_msi(pdev);
194
195 /* request and enable interrupt */
196 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
197
198 err = request_threaded_irq(pdev->irq,
199 mei_me_irq_quick_handler,
200 mei_me_irq_thread_handler,
201 irqflags, KBUILD_MODNAME, dev);
202 if (err) {
203 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
204 pdev->irq);
205 goto disable_msi;
206 }
207
208 if (mei_start(dev)) {
209 dev_err(&pdev->dev, "init hw failure.\n");
210 err = -ENODEV;
211 goto release_irq;
212 }
213
214 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
215 pm_runtime_use_autosuspend(&pdev->dev);
216
217 err = mei_register(dev, &pdev->dev);
218 if (err)
219 goto release_irq;
220
221 pci_set_drvdata(pdev, dev);
222
223 schedule_delayed_work(&dev->timer_work, HZ);
224
225 /*
226 * For not wake-able HW runtime pm framework
227 * can't be used on pci device level.
228 * Use domain runtime pm callbacks instead.
229 */
230 if (!pci_dev_run_wake(pdev))
231 mei_me_set_pm_domain(dev);
232
233 if (mei_pg_is_enabled(dev)) {
234 pm_runtime_put_noidle(&pdev->dev);
235 if (hw->d0i3_supported)
236 pm_runtime_allow(&pdev->dev);
237 }
238
239 dev_dbg(&pdev->dev, "initialization successful.\n");
240
241 return 0;
242
243 release_irq:
244 mei_cancel_work(dev);
245 mei_disable_interrupts(dev);
246 free_irq(pdev->irq, dev);
247 disable_msi:
248 pci_disable_msi(pdev);
249 pci_iounmap(pdev, hw->mem_addr);
250 free_device:
251 kfree(dev);
252 release_regions:
253 pci_release_regions(pdev);
254 disable_device:
255 pci_disable_device(pdev);
256 end:
257 dev_err(&pdev->dev, "initialization failed.\n");
258 return err;
259 }
260
261 /**
262 * mei_me_remove - Device Removal Routine
263 *
264 * @pdev: PCI device structure
265 *
266 * mei_remove is called by the PCI subsystem to alert the driver
267 * that it should release a PCI device.
268 */
mei_me_remove(struct pci_dev * pdev)269 static void mei_me_remove(struct pci_dev *pdev)
270 {
271 struct mei_device *dev;
272 struct mei_me_hw *hw;
273
274 dev = pci_get_drvdata(pdev);
275 if (!dev)
276 return;
277
278 if (mei_pg_is_enabled(dev))
279 pm_runtime_get_noresume(&pdev->dev);
280
281 hw = to_me_hw(dev);
282
283
284 dev_dbg(&pdev->dev, "stop\n");
285 mei_stop(dev);
286
287 if (!pci_dev_run_wake(pdev))
288 mei_me_unset_pm_domain(dev);
289
290 /* disable interrupts */
291 mei_disable_interrupts(dev);
292
293 free_irq(pdev->irq, dev);
294 pci_disable_msi(pdev);
295
296 if (hw->mem_addr)
297 pci_iounmap(pdev, hw->mem_addr);
298
299 mei_deregister(dev);
300
301 kfree(dev);
302
303 pci_release_regions(pdev);
304 pci_disable_device(pdev);
305
306
307 }
308 #ifdef CONFIG_PM_SLEEP
mei_me_pci_suspend(struct device * device)309 static int mei_me_pci_suspend(struct device *device)
310 {
311 struct pci_dev *pdev = to_pci_dev(device);
312 struct mei_device *dev = pci_get_drvdata(pdev);
313
314 if (!dev)
315 return -ENODEV;
316
317 dev_dbg(&pdev->dev, "suspend\n");
318
319 mei_stop(dev);
320
321 mei_disable_interrupts(dev);
322
323 free_irq(pdev->irq, dev);
324 pci_disable_msi(pdev);
325
326 return 0;
327 }
328
mei_me_pci_resume(struct device * device)329 static int mei_me_pci_resume(struct device *device)
330 {
331 struct pci_dev *pdev = to_pci_dev(device);
332 struct mei_device *dev;
333 unsigned int irqflags;
334 int err;
335
336 dev = pci_get_drvdata(pdev);
337 if (!dev)
338 return -ENODEV;
339
340 pci_enable_msi(pdev);
341
342 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
343
344 /* request and enable interrupt */
345 err = request_threaded_irq(pdev->irq,
346 mei_me_irq_quick_handler,
347 mei_me_irq_thread_handler,
348 irqflags, KBUILD_MODNAME, dev);
349
350 if (err) {
351 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
352 pdev->irq);
353 return err;
354 }
355
356 err = mei_restart(dev);
357 if (err)
358 return err;
359
360 /* Start timer if stopped in suspend */
361 schedule_delayed_work(&dev->timer_work, HZ);
362
363 return 0;
364 }
365 #endif /* CONFIG_PM_SLEEP */
366
367 #ifdef CONFIG_PM
mei_me_pm_runtime_idle(struct device * device)368 static int mei_me_pm_runtime_idle(struct device *device)
369 {
370 struct pci_dev *pdev = to_pci_dev(device);
371 struct mei_device *dev;
372
373 dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
374
375 dev = pci_get_drvdata(pdev);
376 if (!dev)
377 return -ENODEV;
378 if (mei_write_is_idle(dev))
379 pm_runtime_autosuspend(device);
380
381 return -EBUSY;
382 }
383
mei_me_pm_runtime_suspend(struct device * device)384 static int mei_me_pm_runtime_suspend(struct device *device)
385 {
386 struct pci_dev *pdev = to_pci_dev(device);
387 struct mei_device *dev;
388 int ret;
389
390 dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
391
392 dev = pci_get_drvdata(pdev);
393 if (!dev)
394 return -ENODEV;
395
396 mutex_lock(&dev->device_lock);
397
398 if (mei_write_is_idle(dev))
399 ret = mei_me_pg_enter_sync(dev);
400 else
401 ret = -EAGAIN;
402
403 mutex_unlock(&dev->device_lock);
404
405 dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
406
407 return ret;
408 }
409
mei_me_pm_runtime_resume(struct device * device)410 static int mei_me_pm_runtime_resume(struct device *device)
411 {
412 struct pci_dev *pdev = to_pci_dev(device);
413 struct mei_device *dev;
414 int ret;
415
416 dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
417
418 dev = pci_get_drvdata(pdev);
419 if (!dev)
420 return -ENODEV;
421
422 mutex_lock(&dev->device_lock);
423
424 ret = mei_me_pg_exit_sync(dev);
425
426 mutex_unlock(&dev->device_lock);
427
428 dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
429
430 return ret;
431 }
432
433 /**
434 * mei_me_set_pm_domain - fill and set pm domain structure for device
435 *
436 * @dev: mei_device
437 */
mei_me_set_pm_domain(struct mei_device * dev)438 static inline void mei_me_set_pm_domain(struct mei_device *dev)
439 {
440 struct pci_dev *pdev = to_pci_dev(dev->dev);
441
442 if (pdev->dev.bus && pdev->dev.bus->pm) {
443 dev->pg_domain.ops = *pdev->dev.bus->pm;
444
445 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
446 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
447 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
448
449 pdev->dev.pm_domain = &dev->pg_domain;
450 }
451 }
452
453 /**
454 * mei_me_unset_pm_domain - clean pm domain structure for device
455 *
456 * @dev: mei_device
457 */
mei_me_unset_pm_domain(struct mei_device * dev)458 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
459 {
460 /* stop using pm callbacks if any */
461 dev->dev->pm_domain = NULL;
462 }
463
464 static const struct dev_pm_ops mei_me_pm_ops = {
465 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
466 mei_me_pci_resume)
467 SET_RUNTIME_PM_OPS(
468 mei_me_pm_runtime_suspend,
469 mei_me_pm_runtime_resume,
470 mei_me_pm_runtime_idle)
471 };
472
473 #define MEI_ME_PM_OPS (&mei_me_pm_ops)
474 #else
475 #define MEI_ME_PM_OPS NULL
476 #endif /* CONFIG_PM */
477 /*
478 * PCI driver structure
479 */
480 static struct pci_driver mei_me_driver = {
481 .name = KBUILD_MODNAME,
482 .id_table = mei_me_pci_tbl,
483 .probe = mei_me_probe,
484 .remove = mei_me_remove,
485 .shutdown = mei_me_remove,
486 .driver.pm = MEI_ME_PM_OPS,
487 };
488
489 module_pci_driver(mei_me_driver);
490
491 MODULE_AUTHOR("Intel Corporation");
492 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
493 MODULE_LICENSE("GPL v2");
494