1 /*
2 * linux/drivers/mmc/host/omap.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/timer.h>
25 #include <linux/of.h>
26 #include <linux/omap-dma.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/clk.h>
31 #include <linux/scatterlist.h>
32 #include <linux/slab.h>
33 #include <linux/platform_data/mmc-omap.h>
34
35
36 #define OMAP_MMC_REG_CMD 0x00
37 #define OMAP_MMC_REG_ARGL 0x01
38 #define OMAP_MMC_REG_ARGH 0x02
39 #define OMAP_MMC_REG_CON 0x03
40 #define OMAP_MMC_REG_STAT 0x04
41 #define OMAP_MMC_REG_IE 0x05
42 #define OMAP_MMC_REG_CTO 0x06
43 #define OMAP_MMC_REG_DTO 0x07
44 #define OMAP_MMC_REG_DATA 0x08
45 #define OMAP_MMC_REG_BLEN 0x09
46 #define OMAP_MMC_REG_NBLK 0x0a
47 #define OMAP_MMC_REG_BUF 0x0b
48 #define OMAP_MMC_REG_SDIO 0x0d
49 #define OMAP_MMC_REG_REV 0x0f
50 #define OMAP_MMC_REG_RSP0 0x10
51 #define OMAP_MMC_REG_RSP1 0x11
52 #define OMAP_MMC_REG_RSP2 0x12
53 #define OMAP_MMC_REG_RSP3 0x13
54 #define OMAP_MMC_REG_RSP4 0x14
55 #define OMAP_MMC_REG_RSP5 0x15
56 #define OMAP_MMC_REG_RSP6 0x16
57 #define OMAP_MMC_REG_RSP7 0x17
58 #define OMAP_MMC_REG_IOSR 0x18
59 #define OMAP_MMC_REG_SYSC 0x19
60 #define OMAP_MMC_REG_SYSS 0x1a
61
62 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
63 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
64 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
65 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
66 #define OMAP_MMC_STAT_A_FULL (1 << 10)
67 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
68 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
69 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
70 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
71 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
72 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
73 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
74 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
75
76 #define mmc_omap7xx() (host->features & MMC_OMAP7XX)
77 #define mmc_omap15xx() (host->features & MMC_OMAP15XX)
78 #define mmc_omap16xx() (host->features & MMC_OMAP16XX)
79 #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
80 #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
81 #define mmc_omap2() (!mmc_omap1())
82
83 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
84 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
85 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
86
87 /*
88 * Command types
89 */
90 #define OMAP_MMC_CMDTYPE_BC 0
91 #define OMAP_MMC_CMDTYPE_BCR 1
92 #define OMAP_MMC_CMDTYPE_AC 2
93 #define OMAP_MMC_CMDTYPE_ADTC 3
94
95 #define DRIVER_NAME "mmci-omap"
96
97 /* Specifies how often in millisecs to poll for card status changes
98 * when the cover switch is open */
99 #define OMAP_MMC_COVER_POLL_DELAY 500
100
101 struct mmc_omap_host;
102
103 struct mmc_omap_slot {
104 int id;
105 unsigned int vdd;
106 u16 saved_con;
107 u16 bus_mode;
108 u16 power_mode;
109 unsigned int fclk_freq;
110
111 struct tasklet_struct cover_tasklet;
112 struct timer_list cover_timer;
113 unsigned cover_open;
114
115 struct mmc_request *mrq;
116 struct mmc_omap_host *host;
117 struct mmc_host *mmc;
118 struct omap_mmc_slot_data *pdata;
119 };
120
121 struct mmc_omap_host {
122 int initialized;
123 struct mmc_request * mrq;
124 struct mmc_command * cmd;
125 struct mmc_data * data;
126 struct mmc_host * mmc;
127 struct device * dev;
128 unsigned char id; /* 16xx chips have 2 MMC blocks */
129 struct clk * iclk;
130 struct clk * fclk;
131 struct dma_chan *dma_rx;
132 u32 dma_rx_burst;
133 struct dma_chan *dma_tx;
134 u32 dma_tx_burst;
135 void __iomem *virt_base;
136 unsigned int phys_base;
137 int irq;
138 unsigned char bus_mode;
139 unsigned int reg_shift;
140
141 struct work_struct cmd_abort_work;
142 unsigned abort:1;
143 struct timer_list cmd_abort_timer;
144
145 struct work_struct slot_release_work;
146 struct mmc_omap_slot *next_slot;
147 struct work_struct send_stop_work;
148 struct mmc_data *stop_data;
149
150 unsigned int sg_len;
151 int sg_idx;
152 u16 * buffer;
153 u32 buffer_bytes_left;
154 u32 total_bytes_left;
155
156 unsigned features;
157 unsigned brs_received:1, dma_done:1;
158 unsigned dma_in_use:1;
159 spinlock_t dma_lock;
160
161 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
162 struct mmc_omap_slot *current_slot;
163 spinlock_t slot_lock;
164 wait_queue_head_t slot_wq;
165 int nr_slots;
166
167 struct timer_list clk_timer;
168 spinlock_t clk_lock; /* for changing enabled state */
169 unsigned int fclk_enabled:1;
170 struct workqueue_struct *mmc_omap_wq;
171
172 struct omap_mmc_platform_data *pdata;
173 };
174
175
mmc_omap_fclk_offdelay(struct mmc_omap_slot * slot)176 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
177 {
178 unsigned long tick_ns;
179
180 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
181 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
182 ndelay(8 * tick_ns);
183 }
184 }
185
mmc_omap_fclk_enable(struct mmc_omap_host * host,unsigned int enable)186 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
187 {
188 unsigned long flags;
189
190 spin_lock_irqsave(&host->clk_lock, flags);
191 if (host->fclk_enabled != enable) {
192 host->fclk_enabled = enable;
193 if (enable)
194 clk_enable(host->fclk);
195 else
196 clk_disable(host->fclk);
197 }
198 spin_unlock_irqrestore(&host->clk_lock, flags);
199 }
200
mmc_omap_select_slot(struct mmc_omap_slot * slot,int claimed)201 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
202 {
203 struct mmc_omap_host *host = slot->host;
204 unsigned long flags;
205
206 if (claimed)
207 goto no_claim;
208 spin_lock_irqsave(&host->slot_lock, flags);
209 while (host->mmc != NULL) {
210 spin_unlock_irqrestore(&host->slot_lock, flags);
211 wait_event(host->slot_wq, host->mmc == NULL);
212 spin_lock_irqsave(&host->slot_lock, flags);
213 }
214 host->mmc = slot->mmc;
215 spin_unlock_irqrestore(&host->slot_lock, flags);
216 no_claim:
217 del_timer(&host->clk_timer);
218 if (host->current_slot != slot || !claimed)
219 mmc_omap_fclk_offdelay(host->current_slot);
220
221 if (host->current_slot != slot) {
222 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
223 if (host->pdata->switch_slot != NULL)
224 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
225 host->current_slot = slot;
226 }
227
228 if (claimed) {
229 mmc_omap_fclk_enable(host, 1);
230
231 /* Doing the dummy read here seems to work around some bug
232 * at least in OMAP24xx silicon where the command would not
233 * start after writing the CMD register. Sigh. */
234 OMAP_MMC_READ(host, CON);
235
236 OMAP_MMC_WRITE(host, CON, slot->saved_con);
237 } else
238 mmc_omap_fclk_enable(host, 0);
239 }
240
241 static void mmc_omap_start_request(struct mmc_omap_host *host,
242 struct mmc_request *req);
243
mmc_omap_slot_release_work(struct work_struct * work)244 static void mmc_omap_slot_release_work(struct work_struct *work)
245 {
246 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
247 slot_release_work);
248 struct mmc_omap_slot *next_slot = host->next_slot;
249 struct mmc_request *rq;
250
251 host->next_slot = NULL;
252 mmc_omap_select_slot(next_slot, 1);
253
254 rq = next_slot->mrq;
255 next_slot->mrq = NULL;
256 mmc_omap_start_request(host, rq);
257 }
258
mmc_omap_release_slot(struct mmc_omap_slot * slot,int clk_enabled)259 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
260 {
261 struct mmc_omap_host *host = slot->host;
262 unsigned long flags;
263 int i;
264
265 BUG_ON(slot == NULL || host->mmc == NULL);
266
267 if (clk_enabled)
268 /* Keeps clock running for at least 8 cycles on valid freq */
269 mod_timer(&host->clk_timer, jiffies + HZ/10);
270 else {
271 del_timer(&host->clk_timer);
272 mmc_omap_fclk_offdelay(slot);
273 mmc_omap_fclk_enable(host, 0);
274 }
275
276 spin_lock_irqsave(&host->slot_lock, flags);
277 /* Check for any pending requests */
278 for (i = 0; i < host->nr_slots; i++) {
279 struct mmc_omap_slot *new_slot;
280
281 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
282 continue;
283
284 BUG_ON(host->next_slot != NULL);
285 new_slot = host->slots[i];
286 /* The current slot should not have a request in queue */
287 BUG_ON(new_slot == host->current_slot);
288
289 host->next_slot = new_slot;
290 host->mmc = new_slot->mmc;
291 spin_unlock_irqrestore(&host->slot_lock, flags);
292 queue_work(host->mmc_omap_wq, &host->slot_release_work);
293 return;
294 }
295
296 host->mmc = NULL;
297 wake_up(&host->slot_wq);
298 spin_unlock_irqrestore(&host->slot_lock, flags);
299 }
300
301 static inline
mmc_omap_cover_is_open(struct mmc_omap_slot * slot)302 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
303 {
304 if (slot->pdata->get_cover_state)
305 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
306 slot->id);
307 return 0;
308 }
309
310 static ssize_t
mmc_omap_show_cover_switch(struct device * dev,struct device_attribute * attr,char * buf)311 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
312 char *buf)
313 {
314 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
315 struct mmc_omap_slot *slot = mmc_priv(mmc);
316
317 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
318 "closed");
319 }
320
321 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
322
323 static ssize_t
mmc_omap_show_slot_name(struct device * dev,struct device_attribute * attr,char * buf)324 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
325 char *buf)
326 {
327 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
328 struct mmc_omap_slot *slot = mmc_priv(mmc);
329
330 return sprintf(buf, "%s\n", slot->pdata->name);
331 }
332
333 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
334
335 static void
mmc_omap_start_command(struct mmc_omap_host * host,struct mmc_command * cmd)336 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
337 {
338 u32 cmdreg;
339 u32 resptype;
340 u32 cmdtype;
341 u16 irq_mask;
342
343 host->cmd = cmd;
344
345 resptype = 0;
346 cmdtype = 0;
347
348 /* Our hardware needs to know exact type */
349 switch (mmc_resp_type(cmd)) {
350 case MMC_RSP_NONE:
351 break;
352 case MMC_RSP_R1:
353 case MMC_RSP_R1B:
354 /* resp 1, 1b, 6, 7 */
355 resptype = 1;
356 break;
357 case MMC_RSP_R2:
358 resptype = 2;
359 break;
360 case MMC_RSP_R3:
361 resptype = 3;
362 break;
363 default:
364 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
365 break;
366 }
367
368 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
369 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
370 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
371 cmdtype = OMAP_MMC_CMDTYPE_BC;
372 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
373 cmdtype = OMAP_MMC_CMDTYPE_BCR;
374 } else {
375 cmdtype = OMAP_MMC_CMDTYPE_AC;
376 }
377
378 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
379
380 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
381 cmdreg |= 1 << 6;
382
383 if (cmd->flags & MMC_RSP_BUSY)
384 cmdreg |= 1 << 11;
385
386 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
387 cmdreg |= 1 << 15;
388
389 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
390
391 OMAP_MMC_WRITE(host, CTO, 200);
392 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
393 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
394 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
395 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
396 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
397 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
398 OMAP_MMC_STAT_END_OF_DATA;
399 if (cmd->opcode == MMC_ERASE)
400 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
401 OMAP_MMC_WRITE(host, IE, irq_mask);
402 OMAP_MMC_WRITE(host, CMD, cmdreg);
403 }
404
405 static void
mmc_omap_release_dma(struct mmc_omap_host * host,struct mmc_data * data,int abort)406 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
407 int abort)
408 {
409 enum dma_data_direction dma_data_dir;
410 struct device *dev = mmc_dev(host->mmc);
411 struct dma_chan *c;
412
413 if (data->flags & MMC_DATA_WRITE) {
414 dma_data_dir = DMA_TO_DEVICE;
415 c = host->dma_tx;
416 } else {
417 dma_data_dir = DMA_FROM_DEVICE;
418 c = host->dma_rx;
419 }
420 if (c) {
421 if (data->error) {
422 dmaengine_terminate_all(c);
423 /* Claim nothing transferred on error... */
424 data->bytes_xfered = 0;
425 }
426 dev = c->device->dev;
427 }
428 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
429 }
430
mmc_omap_send_stop_work(struct work_struct * work)431 static void mmc_omap_send_stop_work(struct work_struct *work)
432 {
433 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
434 send_stop_work);
435 struct mmc_omap_slot *slot = host->current_slot;
436 struct mmc_data *data = host->stop_data;
437 unsigned long tick_ns;
438
439 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
440 ndelay(8*tick_ns);
441
442 mmc_omap_start_command(host, data->stop);
443 }
444
445 static void
mmc_omap_xfer_done(struct mmc_omap_host * host,struct mmc_data * data)446 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
447 {
448 if (host->dma_in_use)
449 mmc_omap_release_dma(host, data, data->error);
450
451 host->data = NULL;
452 host->sg_len = 0;
453
454 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
455 * dozens of requests until the card finishes writing data.
456 * It'd be cheaper to just wait till an EOFB interrupt arrives...
457 */
458
459 if (!data->stop) {
460 struct mmc_host *mmc;
461
462 host->mrq = NULL;
463 mmc = host->mmc;
464 mmc_omap_release_slot(host->current_slot, 1);
465 mmc_request_done(mmc, data->mrq);
466 return;
467 }
468
469 host->stop_data = data;
470 queue_work(host->mmc_omap_wq, &host->send_stop_work);
471 }
472
473 static void
mmc_omap_send_abort(struct mmc_omap_host * host,int maxloops)474 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
475 {
476 struct mmc_omap_slot *slot = host->current_slot;
477 unsigned int restarts, passes, timeout;
478 u16 stat = 0;
479
480 /* Sending abort takes 80 clocks. Have some extra and round up */
481 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
482 restarts = 0;
483 while (restarts < maxloops) {
484 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
485 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
486
487 passes = 0;
488 while (passes < timeout) {
489 stat = OMAP_MMC_READ(host, STAT);
490 if (stat & OMAP_MMC_STAT_END_OF_CMD)
491 goto out;
492 udelay(1);
493 passes++;
494 }
495
496 restarts++;
497 }
498 out:
499 OMAP_MMC_WRITE(host, STAT, stat);
500 }
501
502 static void
mmc_omap_abort_xfer(struct mmc_omap_host * host,struct mmc_data * data)503 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
504 {
505 if (host->dma_in_use)
506 mmc_omap_release_dma(host, data, 1);
507
508 host->data = NULL;
509 host->sg_len = 0;
510
511 mmc_omap_send_abort(host, 10000);
512 }
513
514 static void
mmc_omap_end_of_data(struct mmc_omap_host * host,struct mmc_data * data)515 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
516 {
517 unsigned long flags;
518 int done;
519
520 if (!host->dma_in_use) {
521 mmc_omap_xfer_done(host, data);
522 return;
523 }
524 done = 0;
525 spin_lock_irqsave(&host->dma_lock, flags);
526 if (host->dma_done)
527 done = 1;
528 else
529 host->brs_received = 1;
530 spin_unlock_irqrestore(&host->dma_lock, flags);
531 if (done)
532 mmc_omap_xfer_done(host, data);
533 }
534
535 static void
mmc_omap_dma_done(struct mmc_omap_host * host,struct mmc_data * data)536 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
537 {
538 unsigned long flags;
539 int done;
540
541 done = 0;
542 spin_lock_irqsave(&host->dma_lock, flags);
543 if (host->brs_received)
544 done = 1;
545 else
546 host->dma_done = 1;
547 spin_unlock_irqrestore(&host->dma_lock, flags);
548 if (done)
549 mmc_omap_xfer_done(host, data);
550 }
551
552 static void
mmc_omap_cmd_done(struct mmc_omap_host * host,struct mmc_command * cmd)553 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
554 {
555 host->cmd = NULL;
556
557 del_timer(&host->cmd_abort_timer);
558
559 if (cmd->flags & MMC_RSP_PRESENT) {
560 if (cmd->flags & MMC_RSP_136) {
561 /* response type 2 */
562 cmd->resp[3] =
563 OMAP_MMC_READ(host, RSP0) |
564 (OMAP_MMC_READ(host, RSP1) << 16);
565 cmd->resp[2] =
566 OMAP_MMC_READ(host, RSP2) |
567 (OMAP_MMC_READ(host, RSP3) << 16);
568 cmd->resp[1] =
569 OMAP_MMC_READ(host, RSP4) |
570 (OMAP_MMC_READ(host, RSP5) << 16);
571 cmd->resp[0] =
572 OMAP_MMC_READ(host, RSP6) |
573 (OMAP_MMC_READ(host, RSP7) << 16);
574 } else {
575 /* response types 1, 1b, 3, 4, 5, 6 */
576 cmd->resp[0] =
577 OMAP_MMC_READ(host, RSP6) |
578 (OMAP_MMC_READ(host, RSP7) << 16);
579 }
580 }
581
582 if (host->data == NULL || cmd->error) {
583 struct mmc_host *mmc;
584
585 if (host->data != NULL)
586 mmc_omap_abort_xfer(host, host->data);
587 host->mrq = NULL;
588 mmc = host->mmc;
589 mmc_omap_release_slot(host->current_slot, 1);
590 mmc_request_done(mmc, cmd->mrq);
591 }
592 }
593
594 /*
595 * Abort stuck command. Can occur when card is removed while it is being
596 * read.
597 */
mmc_omap_abort_command(struct work_struct * work)598 static void mmc_omap_abort_command(struct work_struct *work)
599 {
600 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
601 cmd_abort_work);
602 BUG_ON(!host->cmd);
603
604 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
605 host->cmd->opcode);
606
607 if (host->cmd->error == 0)
608 host->cmd->error = -ETIMEDOUT;
609
610 if (host->data == NULL) {
611 struct mmc_command *cmd;
612 struct mmc_host *mmc;
613
614 cmd = host->cmd;
615 host->cmd = NULL;
616 mmc_omap_send_abort(host, 10000);
617
618 host->mrq = NULL;
619 mmc = host->mmc;
620 mmc_omap_release_slot(host->current_slot, 1);
621 mmc_request_done(mmc, cmd->mrq);
622 } else
623 mmc_omap_cmd_done(host, host->cmd);
624
625 host->abort = 0;
626 enable_irq(host->irq);
627 }
628
629 static void
mmc_omap_cmd_timer(unsigned long data)630 mmc_omap_cmd_timer(unsigned long data)
631 {
632 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
633 unsigned long flags;
634
635 spin_lock_irqsave(&host->slot_lock, flags);
636 if (host->cmd != NULL && !host->abort) {
637 OMAP_MMC_WRITE(host, IE, 0);
638 disable_irq(host->irq);
639 host->abort = 1;
640 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
641 }
642 spin_unlock_irqrestore(&host->slot_lock, flags);
643 }
644
645 /* PIO only */
646 static void
mmc_omap_sg_to_buf(struct mmc_omap_host * host)647 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
648 {
649 struct scatterlist *sg;
650
651 sg = host->data->sg + host->sg_idx;
652 host->buffer_bytes_left = sg->length;
653 host->buffer = sg_virt(sg);
654 if (host->buffer_bytes_left > host->total_bytes_left)
655 host->buffer_bytes_left = host->total_bytes_left;
656 }
657
658 static void
mmc_omap_clk_timer(unsigned long data)659 mmc_omap_clk_timer(unsigned long data)
660 {
661 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
662
663 mmc_omap_fclk_enable(host, 0);
664 }
665
666 /* PIO only */
667 static void
mmc_omap_xfer_data(struct mmc_omap_host * host,int write)668 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
669 {
670 int n, nwords;
671
672 if (host->buffer_bytes_left == 0) {
673 host->sg_idx++;
674 BUG_ON(host->sg_idx == host->sg_len);
675 mmc_omap_sg_to_buf(host);
676 }
677 n = 64;
678 if (n > host->buffer_bytes_left)
679 n = host->buffer_bytes_left;
680
681 /* Round up to handle odd number of bytes to transfer */
682 nwords = DIV_ROUND_UP(n, 2);
683
684 host->buffer_bytes_left -= n;
685 host->total_bytes_left -= n;
686 host->data->bytes_xfered += n;
687
688 if (write) {
689 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
690 host->buffer, nwords);
691 } else {
692 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
693 host->buffer, nwords);
694 }
695
696 host->buffer += nwords;
697 }
698
699 #ifdef CONFIG_MMC_DEBUG
mmc_omap_report_irq(struct mmc_omap_host * host,u16 status)700 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
701 {
702 static const char *mmc_omap_status_bits[] = {
703 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
704 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
705 };
706 int i;
707 char res[64], *buf = res;
708
709 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
710
711 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
712 if (status & (1 << i))
713 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
714 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
715 }
716 #else
mmc_omap_report_irq(struct mmc_omap_host * host,u16 status)717 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
718 {
719 }
720 #endif
721
722
mmc_omap_irq(int irq,void * dev_id)723 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
724 {
725 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
726 u16 status;
727 int end_command;
728 int end_transfer;
729 int transfer_error, cmd_error;
730
731 if (host->cmd == NULL && host->data == NULL) {
732 status = OMAP_MMC_READ(host, STAT);
733 dev_info(mmc_dev(host->slots[0]->mmc),
734 "Spurious IRQ 0x%04x\n", status);
735 if (status != 0) {
736 OMAP_MMC_WRITE(host, STAT, status);
737 OMAP_MMC_WRITE(host, IE, 0);
738 }
739 return IRQ_HANDLED;
740 }
741
742 end_command = 0;
743 end_transfer = 0;
744 transfer_error = 0;
745 cmd_error = 0;
746
747 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
748 int cmd;
749
750 OMAP_MMC_WRITE(host, STAT, status);
751 if (host->cmd != NULL)
752 cmd = host->cmd->opcode;
753 else
754 cmd = -1;
755 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
756 status, cmd);
757 mmc_omap_report_irq(host, status);
758
759 if (host->total_bytes_left) {
760 if ((status & OMAP_MMC_STAT_A_FULL) ||
761 (status & OMAP_MMC_STAT_END_OF_DATA))
762 mmc_omap_xfer_data(host, 0);
763 if (status & OMAP_MMC_STAT_A_EMPTY)
764 mmc_omap_xfer_data(host, 1);
765 }
766
767 if (status & OMAP_MMC_STAT_END_OF_DATA)
768 end_transfer = 1;
769
770 if (status & OMAP_MMC_STAT_DATA_TOUT) {
771 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
772 cmd);
773 if (host->data) {
774 host->data->error = -ETIMEDOUT;
775 transfer_error = 1;
776 }
777 }
778
779 if (status & OMAP_MMC_STAT_DATA_CRC) {
780 if (host->data) {
781 host->data->error = -EILSEQ;
782 dev_dbg(mmc_dev(host->mmc),
783 "data CRC error, bytes left %d\n",
784 host->total_bytes_left);
785 transfer_error = 1;
786 } else {
787 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
788 }
789 }
790
791 if (status & OMAP_MMC_STAT_CMD_TOUT) {
792 /* Timeouts are routine with some commands */
793 if (host->cmd) {
794 struct mmc_omap_slot *slot =
795 host->current_slot;
796 if (slot == NULL ||
797 !mmc_omap_cover_is_open(slot))
798 dev_err(mmc_dev(host->mmc),
799 "command timeout (CMD%d)\n",
800 cmd);
801 host->cmd->error = -ETIMEDOUT;
802 end_command = 1;
803 cmd_error = 1;
804 }
805 }
806
807 if (status & OMAP_MMC_STAT_CMD_CRC) {
808 if (host->cmd) {
809 dev_err(mmc_dev(host->mmc),
810 "command CRC error (CMD%d, arg 0x%08x)\n",
811 cmd, host->cmd->arg);
812 host->cmd->error = -EILSEQ;
813 end_command = 1;
814 cmd_error = 1;
815 } else
816 dev_err(mmc_dev(host->mmc),
817 "command CRC error without cmd?\n");
818 }
819
820 if (status & OMAP_MMC_STAT_CARD_ERR) {
821 dev_dbg(mmc_dev(host->mmc),
822 "ignoring card status error (CMD%d)\n",
823 cmd);
824 end_command = 1;
825 }
826
827 /*
828 * NOTE: On 1610 the END_OF_CMD may come too early when
829 * starting a write
830 */
831 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
832 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
833 end_command = 1;
834 }
835 }
836
837 if (cmd_error && host->data) {
838 del_timer(&host->cmd_abort_timer);
839 host->abort = 1;
840 OMAP_MMC_WRITE(host, IE, 0);
841 disable_irq_nosync(host->irq);
842 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
843 return IRQ_HANDLED;
844 }
845
846 if (end_command && host->cmd)
847 mmc_omap_cmd_done(host, host->cmd);
848 if (host->data != NULL) {
849 if (transfer_error)
850 mmc_omap_xfer_done(host, host->data);
851 else if (end_transfer)
852 mmc_omap_end_of_data(host, host->data);
853 }
854
855 return IRQ_HANDLED;
856 }
857
omap_mmc_notify_cover_event(struct device * dev,int num,int is_closed)858 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
859 {
860 int cover_open;
861 struct mmc_omap_host *host = dev_get_drvdata(dev);
862 struct mmc_omap_slot *slot = host->slots[num];
863
864 BUG_ON(num >= host->nr_slots);
865
866 /* Other subsystems can call in here before we're initialised. */
867 if (host->nr_slots == 0 || !host->slots[num])
868 return;
869
870 cover_open = mmc_omap_cover_is_open(slot);
871 if (cover_open != slot->cover_open) {
872 slot->cover_open = cover_open;
873 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
874 }
875
876 tasklet_hi_schedule(&slot->cover_tasklet);
877 }
878
mmc_omap_cover_timer(unsigned long arg)879 static void mmc_omap_cover_timer(unsigned long arg)
880 {
881 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
882 tasklet_schedule(&slot->cover_tasklet);
883 }
884
mmc_omap_cover_handler(unsigned long param)885 static void mmc_omap_cover_handler(unsigned long param)
886 {
887 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
888 int cover_open = mmc_omap_cover_is_open(slot);
889
890 mmc_detect_change(slot->mmc, 0);
891 if (!cover_open)
892 return;
893
894 /*
895 * If no card is inserted, we postpone polling until
896 * the cover has been closed.
897 */
898 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
899 return;
900
901 mod_timer(&slot->cover_timer,
902 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
903 }
904
mmc_omap_dma_callback(void * priv)905 static void mmc_omap_dma_callback(void *priv)
906 {
907 struct mmc_omap_host *host = priv;
908 struct mmc_data *data = host->data;
909
910 /* If we got to the end of DMA, assume everything went well */
911 data->bytes_xfered += data->blocks * data->blksz;
912
913 mmc_omap_dma_done(host, data);
914 }
915
set_cmd_timeout(struct mmc_omap_host * host,struct mmc_request * req)916 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
917 {
918 u16 reg;
919
920 reg = OMAP_MMC_READ(host, SDIO);
921 reg &= ~(1 << 5);
922 OMAP_MMC_WRITE(host, SDIO, reg);
923 /* Set maximum timeout */
924 OMAP_MMC_WRITE(host, CTO, 0xfd);
925 }
926
set_data_timeout(struct mmc_omap_host * host,struct mmc_request * req)927 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
928 {
929 unsigned int timeout, cycle_ns;
930 u16 reg;
931
932 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
933 timeout = req->data->timeout_ns / cycle_ns;
934 timeout += req->data->timeout_clks;
935
936 /* Check if we need to use timeout multiplier register */
937 reg = OMAP_MMC_READ(host, SDIO);
938 if (timeout > 0xffff) {
939 reg |= (1 << 5);
940 timeout /= 1024;
941 } else
942 reg &= ~(1 << 5);
943 OMAP_MMC_WRITE(host, SDIO, reg);
944 OMAP_MMC_WRITE(host, DTO, timeout);
945 }
946
947 static void
mmc_omap_prepare_data(struct mmc_omap_host * host,struct mmc_request * req)948 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
949 {
950 struct mmc_data *data = req->data;
951 int i, use_dma = 1, block_size;
952 struct scatterlist *sg;
953 unsigned sg_len;
954
955 host->data = data;
956 if (data == NULL) {
957 OMAP_MMC_WRITE(host, BLEN, 0);
958 OMAP_MMC_WRITE(host, NBLK, 0);
959 OMAP_MMC_WRITE(host, BUF, 0);
960 host->dma_in_use = 0;
961 set_cmd_timeout(host, req);
962 return;
963 }
964
965 block_size = data->blksz;
966
967 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
968 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
969 set_data_timeout(host, req);
970
971 /* cope with calling layer confusion; it issues "single
972 * block" writes using multi-block scatterlists.
973 */
974 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
975
976 /* Only do DMA for entire blocks */
977 for_each_sg(data->sg, sg, sg_len, i) {
978 if ((sg->length % block_size) != 0) {
979 use_dma = 0;
980 break;
981 }
982 }
983
984 host->sg_idx = 0;
985 if (use_dma) {
986 enum dma_data_direction dma_data_dir;
987 struct dma_async_tx_descriptor *tx;
988 struct dma_chan *c;
989 u32 burst, *bp;
990 u16 buf;
991
992 /*
993 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
994 * and 24xx. Use 16 or 32 word frames when the
995 * blocksize is at least that large. Blocksize is
996 * usually 512 bytes; but not for some SD reads.
997 */
998 burst = mmc_omap15xx() ? 32 : 64;
999 if (burst > data->blksz)
1000 burst = data->blksz;
1001
1002 burst >>= 1;
1003
1004 if (data->flags & MMC_DATA_WRITE) {
1005 c = host->dma_tx;
1006 bp = &host->dma_tx_burst;
1007 buf = 0x0f80 | (burst - 1) << 0;
1008 dma_data_dir = DMA_TO_DEVICE;
1009 } else {
1010 c = host->dma_rx;
1011 bp = &host->dma_rx_burst;
1012 buf = 0x800f | (burst - 1) << 8;
1013 dma_data_dir = DMA_FROM_DEVICE;
1014 }
1015
1016 if (!c)
1017 goto use_pio;
1018
1019 /* Only reconfigure if we have a different burst size */
1020 if (*bp != burst) {
1021 struct dma_slave_config cfg;
1022
1023 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1024 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1025 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1026 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1027 cfg.src_maxburst = burst;
1028 cfg.dst_maxburst = burst;
1029
1030 if (dmaengine_slave_config(c, &cfg))
1031 goto use_pio;
1032
1033 *bp = burst;
1034 }
1035
1036 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1037 dma_data_dir);
1038 if (host->sg_len == 0)
1039 goto use_pio;
1040
1041 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1042 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1043 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1044 if (!tx)
1045 goto use_pio;
1046
1047 OMAP_MMC_WRITE(host, BUF, buf);
1048
1049 tx->callback = mmc_omap_dma_callback;
1050 tx->callback_param = host;
1051 dmaengine_submit(tx);
1052 host->brs_received = 0;
1053 host->dma_done = 0;
1054 host->dma_in_use = 1;
1055 return;
1056 }
1057 use_pio:
1058
1059 /* Revert to PIO? */
1060 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1061 host->total_bytes_left = data->blocks * block_size;
1062 host->sg_len = sg_len;
1063 mmc_omap_sg_to_buf(host);
1064 host->dma_in_use = 0;
1065 }
1066
mmc_omap_start_request(struct mmc_omap_host * host,struct mmc_request * req)1067 static void mmc_omap_start_request(struct mmc_omap_host *host,
1068 struct mmc_request *req)
1069 {
1070 BUG_ON(host->mrq != NULL);
1071
1072 host->mrq = req;
1073
1074 /* only touch fifo AFTER the controller readies it */
1075 mmc_omap_prepare_data(host, req);
1076 mmc_omap_start_command(host, req->cmd);
1077 if (host->dma_in_use) {
1078 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1079 host->dma_tx : host->dma_rx;
1080
1081 dma_async_issue_pending(c);
1082 }
1083 }
1084
mmc_omap_request(struct mmc_host * mmc,struct mmc_request * req)1085 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1086 {
1087 struct mmc_omap_slot *slot = mmc_priv(mmc);
1088 struct mmc_omap_host *host = slot->host;
1089 unsigned long flags;
1090
1091 spin_lock_irqsave(&host->slot_lock, flags);
1092 if (host->mmc != NULL) {
1093 BUG_ON(slot->mrq != NULL);
1094 slot->mrq = req;
1095 spin_unlock_irqrestore(&host->slot_lock, flags);
1096 return;
1097 } else
1098 host->mmc = mmc;
1099 spin_unlock_irqrestore(&host->slot_lock, flags);
1100 mmc_omap_select_slot(slot, 1);
1101 mmc_omap_start_request(host, req);
1102 }
1103
mmc_omap_set_power(struct mmc_omap_slot * slot,int power_on,int vdd)1104 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1105 int vdd)
1106 {
1107 struct mmc_omap_host *host;
1108
1109 host = slot->host;
1110
1111 if (slot->pdata->set_power != NULL)
1112 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1113 vdd);
1114 if (mmc_omap2()) {
1115 u16 w;
1116
1117 if (power_on) {
1118 w = OMAP_MMC_READ(host, CON);
1119 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1120 } else {
1121 w = OMAP_MMC_READ(host, CON);
1122 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1123 }
1124 }
1125 }
1126
mmc_omap_calc_divisor(struct mmc_host * mmc,struct mmc_ios * ios)1127 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1128 {
1129 struct mmc_omap_slot *slot = mmc_priv(mmc);
1130 struct mmc_omap_host *host = slot->host;
1131 int func_clk_rate = clk_get_rate(host->fclk);
1132 int dsor;
1133
1134 if (ios->clock == 0)
1135 return 0;
1136
1137 dsor = func_clk_rate / ios->clock;
1138 if (dsor < 1)
1139 dsor = 1;
1140
1141 if (func_clk_rate / dsor > ios->clock)
1142 dsor++;
1143
1144 if (dsor > 250)
1145 dsor = 250;
1146
1147 slot->fclk_freq = func_clk_rate / dsor;
1148
1149 if (ios->bus_width == MMC_BUS_WIDTH_4)
1150 dsor |= 1 << 15;
1151
1152 return dsor;
1153 }
1154
mmc_omap_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1155 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1156 {
1157 struct mmc_omap_slot *slot = mmc_priv(mmc);
1158 struct mmc_omap_host *host = slot->host;
1159 int i, dsor;
1160 int clk_enabled, init_stream;
1161
1162 mmc_omap_select_slot(slot, 0);
1163
1164 dsor = mmc_omap_calc_divisor(mmc, ios);
1165
1166 if (ios->vdd != slot->vdd)
1167 slot->vdd = ios->vdd;
1168
1169 clk_enabled = 0;
1170 init_stream = 0;
1171 switch (ios->power_mode) {
1172 case MMC_POWER_OFF:
1173 mmc_omap_set_power(slot, 0, ios->vdd);
1174 break;
1175 case MMC_POWER_UP:
1176 /* Cannot touch dsor yet, just power up MMC */
1177 mmc_omap_set_power(slot, 1, ios->vdd);
1178 slot->power_mode = ios->power_mode;
1179 goto exit;
1180 case MMC_POWER_ON:
1181 mmc_omap_fclk_enable(host, 1);
1182 clk_enabled = 1;
1183 dsor |= 1 << 11;
1184 if (slot->power_mode != MMC_POWER_ON)
1185 init_stream = 1;
1186 break;
1187 }
1188 slot->power_mode = ios->power_mode;
1189
1190 if (slot->bus_mode != ios->bus_mode) {
1191 if (slot->pdata->set_bus_mode != NULL)
1192 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1193 ios->bus_mode);
1194 slot->bus_mode = ios->bus_mode;
1195 }
1196
1197 /* On insanely high arm_per frequencies something sometimes
1198 * goes somehow out of sync, and the POW bit is not being set,
1199 * which results in the while loop below getting stuck.
1200 * Writing to the CON register twice seems to do the trick. */
1201 for (i = 0; i < 2; i++)
1202 OMAP_MMC_WRITE(host, CON, dsor);
1203 slot->saved_con = dsor;
1204 if (init_stream) {
1205 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1206 int usecs = 250;
1207
1208 /* Send clock cycles, poll completion */
1209 OMAP_MMC_WRITE(host, IE, 0);
1210 OMAP_MMC_WRITE(host, STAT, 0xffff);
1211 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1212 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1213 udelay(1);
1214 usecs--;
1215 }
1216 OMAP_MMC_WRITE(host, STAT, 1);
1217 }
1218
1219 exit:
1220 mmc_omap_release_slot(slot, clk_enabled);
1221 }
1222
1223 static const struct mmc_host_ops mmc_omap_ops = {
1224 .request = mmc_omap_request,
1225 .set_ios = mmc_omap_set_ios,
1226 };
1227
mmc_omap_new_slot(struct mmc_omap_host * host,int id)1228 static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1229 {
1230 struct mmc_omap_slot *slot = NULL;
1231 struct mmc_host *mmc;
1232 int r;
1233
1234 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1235 if (mmc == NULL)
1236 return -ENOMEM;
1237
1238 slot = mmc_priv(mmc);
1239 slot->host = host;
1240 slot->mmc = mmc;
1241 slot->id = id;
1242 slot->power_mode = MMC_POWER_UNDEFINED;
1243 slot->pdata = &host->pdata->slots[id];
1244
1245 host->slots[id] = slot;
1246
1247 mmc->caps = 0;
1248 if (host->pdata->slots[id].wires >= 4)
1249 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_ERASE;
1250
1251 mmc->ops = &mmc_omap_ops;
1252 mmc->f_min = 400000;
1253
1254 if (mmc_omap2())
1255 mmc->f_max = 48000000;
1256 else
1257 mmc->f_max = 24000000;
1258 if (host->pdata->max_freq)
1259 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1260 mmc->ocr_avail = slot->pdata->ocr_mask;
1261
1262 /* Use scatterlist DMA to reduce per-transfer costs.
1263 * NOTE max_seg_size assumption that small blocks aren't
1264 * normally used (except e.g. for reading SD registers).
1265 */
1266 mmc->max_segs = 32;
1267 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1268 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1269 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1270 mmc->max_seg_size = mmc->max_req_size;
1271
1272 if (slot->pdata->get_cover_state != NULL) {
1273 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1274 (unsigned long)slot);
1275 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1276 (unsigned long)slot);
1277 }
1278
1279 r = mmc_add_host(mmc);
1280 if (r < 0)
1281 goto err_remove_host;
1282
1283 if (slot->pdata->name != NULL) {
1284 r = device_create_file(&mmc->class_dev,
1285 &dev_attr_slot_name);
1286 if (r < 0)
1287 goto err_remove_host;
1288 }
1289
1290 if (slot->pdata->get_cover_state != NULL) {
1291 r = device_create_file(&mmc->class_dev,
1292 &dev_attr_cover_switch);
1293 if (r < 0)
1294 goto err_remove_slot_name;
1295 tasklet_schedule(&slot->cover_tasklet);
1296 }
1297
1298 return 0;
1299
1300 err_remove_slot_name:
1301 if (slot->pdata->name != NULL)
1302 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1303 err_remove_host:
1304 mmc_remove_host(mmc);
1305 mmc_free_host(mmc);
1306 return r;
1307 }
1308
mmc_omap_remove_slot(struct mmc_omap_slot * slot)1309 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1310 {
1311 struct mmc_host *mmc = slot->mmc;
1312
1313 if (slot->pdata->name != NULL)
1314 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1315 if (slot->pdata->get_cover_state != NULL)
1316 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1317
1318 tasklet_kill(&slot->cover_tasklet);
1319 del_timer_sync(&slot->cover_timer);
1320 flush_workqueue(slot->host->mmc_omap_wq);
1321
1322 mmc_remove_host(mmc);
1323 mmc_free_host(mmc);
1324 }
1325
mmc_omap_probe(struct platform_device * pdev)1326 static int mmc_omap_probe(struct platform_device *pdev)
1327 {
1328 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1329 struct mmc_omap_host *host = NULL;
1330 struct resource *res;
1331 dma_cap_mask_t mask;
1332 unsigned sig = 0;
1333 int i, ret = 0;
1334 int irq;
1335
1336 if (pdata == NULL) {
1337 dev_err(&pdev->dev, "platform data missing\n");
1338 return -ENXIO;
1339 }
1340 if (pdata->nr_slots == 0) {
1341 dev_err(&pdev->dev, "no slots\n");
1342 return -EPROBE_DEFER;
1343 }
1344
1345 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1346 GFP_KERNEL);
1347 if (host == NULL)
1348 return -ENOMEM;
1349
1350 irq = platform_get_irq(pdev, 0);
1351 if (irq < 0)
1352 return -ENXIO;
1353
1354 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1355 host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1356 if (IS_ERR(host->virt_base))
1357 return PTR_ERR(host->virt_base);
1358
1359 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1360 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1361
1362 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1363 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1364 (unsigned long) host);
1365
1366 spin_lock_init(&host->clk_lock);
1367 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1368
1369 spin_lock_init(&host->dma_lock);
1370 spin_lock_init(&host->slot_lock);
1371 init_waitqueue_head(&host->slot_wq);
1372
1373 host->pdata = pdata;
1374 host->features = host->pdata->slots[0].features;
1375 host->dev = &pdev->dev;
1376 platform_set_drvdata(pdev, host);
1377
1378 host->id = pdev->id;
1379 host->irq = irq;
1380 host->phys_base = res->start;
1381 host->iclk = clk_get(&pdev->dev, "ick");
1382 if (IS_ERR(host->iclk))
1383 return PTR_ERR(host->iclk);
1384 clk_enable(host->iclk);
1385
1386 host->fclk = clk_get(&pdev->dev, "fck");
1387 if (IS_ERR(host->fclk)) {
1388 ret = PTR_ERR(host->fclk);
1389 goto err_free_iclk;
1390 }
1391
1392 dma_cap_zero(mask);
1393 dma_cap_set(DMA_SLAVE, mask);
1394
1395 host->dma_tx_burst = -1;
1396 host->dma_rx_burst = -1;
1397
1398 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1399 if (res)
1400 sig = res->start;
1401 host->dma_tx = dma_request_slave_channel_compat(mask,
1402 omap_dma_filter_fn, &sig, &pdev->dev, "tx");
1403 if (!host->dma_tx)
1404 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1405 sig);
1406
1407 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1408 if (res)
1409 sig = res->start;
1410 host->dma_rx = dma_request_slave_channel_compat(mask,
1411 omap_dma_filter_fn, &sig, &pdev->dev, "rx");
1412 if (!host->dma_rx)
1413 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1414 sig);
1415
1416 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1417 if (ret)
1418 goto err_free_dma;
1419
1420 if (pdata->init != NULL) {
1421 ret = pdata->init(&pdev->dev);
1422 if (ret < 0)
1423 goto err_free_irq;
1424 }
1425
1426 host->nr_slots = pdata->nr_slots;
1427 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1428
1429 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1430 if (!host->mmc_omap_wq) {
1431 ret = -ENOMEM;
1432 goto err_plat_cleanup;
1433 }
1434
1435 for (i = 0; i < pdata->nr_slots; i++) {
1436 ret = mmc_omap_new_slot(host, i);
1437 if (ret < 0) {
1438 while (--i >= 0)
1439 mmc_omap_remove_slot(host->slots[i]);
1440
1441 goto err_destroy_wq;
1442 }
1443 }
1444
1445 return 0;
1446
1447 err_destroy_wq:
1448 destroy_workqueue(host->mmc_omap_wq);
1449 err_plat_cleanup:
1450 if (pdata->cleanup)
1451 pdata->cleanup(&pdev->dev);
1452 err_free_irq:
1453 free_irq(host->irq, host);
1454 err_free_dma:
1455 if (host->dma_tx)
1456 dma_release_channel(host->dma_tx);
1457 if (host->dma_rx)
1458 dma_release_channel(host->dma_rx);
1459 clk_put(host->fclk);
1460 err_free_iclk:
1461 clk_disable(host->iclk);
1462 clk_put(host->iclk);
1463 return ret;
1464 }
1465
mmc_omap_remove(struct platform_device * pdev)1466 static int mmc_omap_remove(struct platform_device *pdev)
1467 {
1468 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1469 int i;
1470
1471 BUG_ON(host == NULL);
1472
1473 for (i = 0; i < host->nr_slots; i++)
1474 mmc_omap_remove_slot(host->slots[i]);
1475
1476 if (host->pdata->cleanup)
1477 host->pdata->cleanup(&pdev->dev);
1478
1479 mmc_omap_fclk_enable(host, 0);
1480 free_irq(host->irq, host);
1481 clk_put(host->fclk);
1482 clk_disable(host->iclk);
1483 clk_put(host->iclk);
1484
1485 if (host->dma_tx)
1486 dma_release_channel(host->dma_tx);
1487 if (host->dma_rx)
1488 dma_release_channel(host->dma_rx);
1489
1490 destroy_workqueue(host->mmc_omap_wq);
1491
1492 return 0;
1493 }
1494
1495 #if IS_BUILTIN(CONFIG_OF)
1496 static const struct of_device_id mmc_omap_match[] = {
1497 { .compatible = "ti,omap2420-mmc", },
1498 { },
1499 };
1500 MODULE_DEVICE_TABLE(of, mmc_omap_match);
1501 #endif
1502
1503 static struct platform_driver mmc_omap_driver = {
1504 .probe = mmc_omap_probe,
1505 .remove = mmc_omap_remove,
1506 .driver = {
1507 .name = DRIVER_NAME,
1508 .of_match_table = of_match_ptr(mmc_omap_match),
1509 },
1510 };
1511
1512 module_platform_driver(mmc_omap_driver);
1513 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1514 MODULE_LICENSE("GPL");
1515 MODULE_ALIAS("platform:" DRIVER_NAME);
1516 MODULE_AUTHOR("Juha Yrjölä");
1517