1 /* Realtek PCI-Express SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 */
21
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/highmem.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/workqueue.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/sd.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mfd/rtsx_pci.h>
34 #include <asm/unaligned.h>
35
36 struct realtek_pci_sdmmc {
37 struct platform_device *pdev;
38 struct rtsx_pcr *pcr;
39 struct mmc_host *mmc;
40 struct mmc_request *mrq;
41 struct workqueue_struct *workq;
42 #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
43
44 struct work_struct work;
45 struct mutex host_mutex;
46
47 u8 ssc_depth;
48 unsigned int clock;
49 bool vpclk;
50 bool double_clk;
51 bool eject;
52 bool initial_mode;
53 int power_state;
54 #define SDMMC_POWER_ON 1
55 #define SDMMC_POWER_OFF 0
56
57 int sg_count;
58 s32 cookie;
59 int cookie_sg_count;
60 bool using_cookie;
61 };
62
sdmmc_dev(struct realtek_pci_sdmmc * host)63 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
64 {
65 return &(host->pdev->dev);
66 }
67
sd_clear_error(struct realtek_pci_sdmmc * host)68 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
69 {
70 rtsx_pci_write_register(host->pcr, CARD_STOP,
71 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
72 }
73
74 #ifdef DEBUG
dump_reg_range(struct realtek_pci_sdmmc * host,u16 start,u16 end)75 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
76 {
77 u16 len = end - start + 1;
78 int i;
79 u8 data[8];
80
81 for (i = 0; i < len; i += 8) {
82 int j;
83 int n = min(8, len - i);
84
85 memset(&data, 0, sizeof(data));
86 for (j = 0; j < n; j++)
87 rtsx_pci_read_register(host->pcr, start + i + j,
88 data + j);
89 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
90 start + i, n, data);
91 }
92 }
93
sd_print_debug_regs(struct realtek_pci_sdmmc * host)94 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
95 {
96 dump_reg_range(host, 0xFDA0, 0xFDB3);
97 dump_reg_range(host, 0xFD52, 0xFD69);
98 }
99 #else
100 #define sd_print_debug_regs(host)
101 #endif /* DEBUG */
102
sd_get_cd_int(struct realtek_pci_sdmmc * host)103 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
104 {
105 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
106 }
107
sd_cmd_set_sd_cmd(struct rtsx_pcr * pcr,struct mmc_command * cmd)108 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
109 {
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
111 SD_CMD_START | cmd->opcode);
112 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
113 }
114
sd_cmd_set_data_len(struct rtsx_pcr * pcr,u16 blocks,u16 blksz)115 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
116 {
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
121 }
122
sd_response_type(struct mmc_command * cmd)123 static int sd_response_type(struct mmc_command *cmd)
124 {
125 switch (mmc_resp_type(cmd)) {
126 case MMC_RSP_NONE:
127 return SD_RSP_TYPE_R0;
128 case MMC_RSP_R1:
129 return SD_RSP_TYPE_R1;
130 case MMC_RSP_R1 & ~MMC_RSP_CRC:
131 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
132 case MMC_RSP_R1B:
133 return SD_RSP_TYPE_R1b;
134 case MMC_RSP_R2:
135 return SD_RSP_TYPE_R2;
136 case MMC_RSP_R3:
137 return SD_RSP_TYPE_R3;
138 default:
139 return -EINVAL;
140 }
141 }
142
sd_status_index(int resp_type)143 static int sd_status_index(int resp_type)
144 {
145 if (resp_type == SD_RSP_TYPE_R0)
146 return 0;
147 else if (resp_type == SD_RSP_TYPE_R2)
148 return 16;
149
150 return 5;
151 }
152 /*
153 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
154 *
155 * @pre: if called in pre_req()
156 * return:
157 * 0 - do dma_map_sg()
158 * 1 - using cookie
159 */
sd_pre_dma_transfer(struct realtek_pci_sdmmc * host,struct mmc_data * data,bool pre)160 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
161 struct mmc_data *data, bool pre)
162 {
163 struct rtsx_pcr *pcr = host->pcr;
164 int read = data->flags & MMC_DATA_READ;
165 int count = 0;
166 int using_cookie = 0;
167
168 if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
169 dev_err(sdmmc_dev(host),
170 "error: data->host_cookie = %d, host->cookie = %d\n",
171 data->host_cookie, host->cookie);
172 data->host_cookie = 0;
173 }
174
175 if (pre || data->host_cookie != host->cookie) {
176 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
177 } else {
178 count = host->cookie_sg_count;
179 using_cookie = 1;
180 }
181
182 if (pre) {
183 host->cookie_sg_count = count;
184 if (++host->cookie < 0)
185 host->cookie = 1;
186 data->host_cookie = host->cookie;
187 } else {
188 host->sg_count = count;
189 }
190
191 return using_cookie;
192 }
193
sdmmc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq,bool is_first_req)194 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
195 bool is_first_req)
196 {
197 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
198 struct mmc_data *data = mrq->data;
199
200 if (data->host_cookie) {
201 dev_err(sdmmc_dev(host),
202 "error: reset data->host_cookie = %d\n",
203 data->host_cookie);
204 data->host_cookie = 0;
205 }
206
207 sd_pre_dma_transfer(host, data, true);
208 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
209 }
210
sdmmc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)211 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
212 int err)
213 {
214 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
215 struct rtsx_pcr *pcr = host->pcr;
216 struct mmc_data *data = mrq->data;
217 int read = data->flags & MMC_DATA_READ;
218
219 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
220 data->host_cookie = 0;
221 }
222
sd_send_cmd_get_rsp(struct realtek_pci_sdmmc * host,struct mmc_command * cmd)223 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
224 struct mmc_command *cmd)
225 {
226 struct rtsx_pcr *pcr = host->pcr;
227 u8 cmd_idx = (u8)cmd->opcode;
228 u32 arg = cmd->arg;
229 int err = 0;
230 int timeout = 100;
231 int i;
232 u8 *ptr;
233 int rsp_type;
234 int stat_idx;
235 bool clock_toggled = false;
236
237 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
238 __func__, cmd_idx, arg);
239
240 rsp_type = sd_response_type(cmd);
241 if (rsp_type < 0)
242 goto out;
243
244 stat_idx = sd_status_index(rsp_type);
245
246 if (rsp_type == SD_RSP_TYPE_R1b)
247 timeout = 3000;
248
249 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
250 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
251 0xFF, SD_CLK_TOGGLE_EN);
252 if (err < 0)
253 goto out;
254
255 clock_toggled = true;
256 }
257
258 rtsx_pci_init_cmd(pcr);
259 sd_cmd_set_sd_cmd(pcr, cmd);
260 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
261 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
262 0x01, PINGPONG_BUFFER);
263 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
264 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
265 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
266 SD_TRANSFER_END | SD_STAT_IDLE,
267 SD_TRANSFER_END | SD_STAT_IDLE);
268
269 if (rsp_type == SD_RSP_TYPE_R2) {
270 /* Read data from ping-pong buffer */
271 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
272 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
273 } else if (rsp_type != SD_RSP_TYPE_R0) {
274 /* Read data from SD_CMDx registers */
275 for (i = SD_CMD0; i <= SD_CMD4; i++)
276 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
277 }
278
279 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
280
281 err = rtsx_pci_send_cmd(pcr, timeout);
282 if (err < 0) {
283 sd_print_debug_regs(host);
284 sd_clear_error(host);
285 dev_dbg(sdmmc_dev(host),
286 "rtsx_pci_send_cmd error (err = %d)\n", err);
287 goto out;
288 }
289
290 if (rsp_type == SD_RSP_TYPE_R0) {
291 err = 0;
292 goto out;
293 }
294
295 /* Eliminate returned value of CHECK_REG_CMD */
296 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
297
298 /* Check (Start,Transmission) bit of Response */
299 if ((ptr[0] & 0xC0) != 0) {
300 err = -EILSEQ;
301 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
302 goto out;
303 }
304
305 /* Check CRC7 */
306 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
307 if (ptr[stat_idx] & SD_CRC7_ERR) {
308 err = -EILSEQ;
309 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
310 goto out;
311 }
312 }
313
314 if (rsp_type == SD_RSP_TYPE_R2) {
315 /*
316 * The controller offloads the last byte {CRC-7, end bit 1'b1}
317 * of response type R2. Assign dummy CRC, 0, and end bit to the
318 * byte(ptr[16], goes into the LSB of resp[3] later).
319 */
320 ptr[16] = 1;
321
322 for (i = 0; i < 4; i++) {
323 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
324 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
325 i, cmd->resp[i]);
326 }
327 } else {
328 cmd->resp[0] = get_unaligned_be32(ptr + 1);
329 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
330 cmd->resp[0]);
331 }
332
333 out:
334 cmd->error = err;
335
336 if (err && clock_toggled)
337 rtsx_pci_write_register(pcr, SD_BUS_STAT,
338 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
339 }
340
sd_read_data(struct realtek_pci_sdmmc * host,struct mmc_command * cmd,u16 byte_cnt,u8 * buf,int buf_len,int timeout)341 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
342 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
343 {
344 struct rtsx_pcr *pcr = host->pcr;
345 int err;
346 u8 trans_mode;
347
348 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
349 __func__, cmd->opcode, cmd->arg);
350
351 if (!buf)
352 buf_len = 0;
353
354 if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
355 trans_mode = SD_TM_AUTO_TUNING;
356 else
357 trans_mode = SD_TM_NORMAL_READ;
358
359 rtsx_pci_init_cmd(pcr);
360 sd_cmd_set_sd_cmd(pcr, cmd);
361 sd_cmd_set_data_len(pcr, 1, byte_cnt);
362 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
363 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
364 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
365 if (trans_mode != SD_TM_AUTO_TUNING)
366 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
367 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
368
369 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
370 0xFF, trans_mode | SD_TRANSFER_START);
371 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
372 SD_TRANSFER_END, SD_TRANSFER_END);
373
374 err = rtsx_pci_send_cmd(pcr, timeout);
375 if (err < 0) {
376 sd_print_debug_regs(host);
377 dev_dbg(sdmmc_dev(host),
378 "rtsx_pci_send_cmd fail (err = %d)\n", err);
379 return err;
380 }
381
382 if (buf && buf_len) {
383 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
384 if (err < 0) {
385 dev_dbg(sdmmc_dev(host),
386 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
387 return err;
388 }
389 }
390
391 return 0;
392 }
393
sd_write_data(struct realtek_pci_sdmmc * host,struct mmc_command * cmd,u16 byte_cnt,u8 * buf,int buf_len,int timeout)394 static int sd_write_data(struct realtek_pci_sdmmc *host,
395 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
396 int timeout)
397 {
398 struct rtsx_pcr *pcr = host->pcr;
399 int err;
400
401 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
402 __func__, cmd->opcode, cmd->arg);
403
404 if (!buf)
405 buf_len = 0;
406
407 sd_send_cmd_get_rsp(host, cmd);
408 if (cmd->error)
409 return cmd->error;
410
411 if (buf && buf_len) {
412 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
413 if (err < 0) {
414 dev_dbg(sdmmc_dev(host),
415 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
416 return err;
417 }
418 }
419
420 rtsx_pci_init_cmd(pcr);
421 sd_cmd_set_data_len(pcr, 1, byte_cnt);
422 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
423 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
424 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
425 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
426 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
427 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
428 SD_TRANSFER_END, SD_TRANSFER_END);
429
430 err = rtsx_pci_send_cmd(pcr, timeout);
431 if (err < 0) {
432 sd_print_debug_regs(host);
433 dev_dbg(sdmmc_dev(host),
434 "rtsx_pci_send_cmd fail (err = %d)\n", err);
435 return err;
436 }
437
438 return 0;
439 }
440
sd_read_long_data(struct realtek_pci_sdmmc * host,struct mmc_request * mrq)441 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
442 struct mmc_request *mrq)
443 {
444 struct rtsx_pcr *pcr = host->pcr;
445 struct mmc_host *mmc = host->mmc;
446 struct mmc_card *card = mmc->card;
447 struct mmc_command *cmd = mrq->cmd;
448 struct mmc_data *data = mrq->data;
449 int uhs = mmc_card_uhs(card);
450 u8 cfg2 = 0;
451 int err;
452 int resp_type;
453 size_t data_len = data->blksz * data->blocks;
454
455 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
456 __func__, cmd->opcode, cmd->arg);
457
458 resp_type = sd_response_type(cmd);
459 if (resp_type < 0)
460 return resp_type;
461
462 if (!uhs)
463 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
464
465 rtsx_pci_init_cmd(pcr);
466 sd_cmd_set_sd_cmd(pcr, cmd);
467 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
468 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
469 DMA_DONE_INT, DMA_DONE_INT);
470 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
471 0xFF, (u8)(data_len >> 24));
472 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
473 0xFF, (u8)(data_len >> 16));
474 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
475 0xFF, (u8)(data_len >> 8));
476 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
477 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
478 0x03 | DMA_PACK_SIZE_MASK,
479 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
480 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
481 0x01, RING_BUFFER);
482 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
483 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
484 SD_TRANSFER_START | SD_TM_AUTO_READ_2);
485 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
486 SD_TRANSFER_END, SD_TRANSFER_END);
487 rtsx_pci_send_cmd_no_wait(pcr);
488
489 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
490 if (err < 0) {
491 sd_print_debug_regs(host);
492 sd_clear_error(host);
493 return err;
494 }
495
496 return 0;
497 }
498
sd_write_long_data(struct realtek_pci_sdmmc * host,struct mmc_request * mrq)499 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
500 struct mmc_request *mrq)
501 {
502 struct rtsx_pcr *pcr = host->pcr;
503 struct mmc_host *mmc = host->mmc;
504 struct mmc_card *card = mmc->card;
505 struct mmc_command *cmd = mrq->cmd;
506 struct mmc_data *data = mrq->data;
507 int uhs = mmc_card_uhs(card);
508 u8 cfg2;
509 int err;
510 size_t data_len = data->blksz * data->blocks;
511
512 sd_send_cmd_get_rsp(host, cmd);
513 if (cmd->error)
514 return cmd->error;
515
516 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
517 __func__, cmd->opcode, cmd->arg);
518
519 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
520 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
521
522 if (!uhs)
523 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
524
525 rtsx_pci_init_cmd(pcr);
526 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
527 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
528 DMA_DONE_INT, DMA_DONE_INT);
529 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
530 0xFF, (u8)(data_len >> 24));
531 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
532 0xFF, (u8)(data_len >> 16));
533 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
534 0xFF, (u8)(data_len >> 8));
535 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
536 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
537 0x03 | DMA_PACK_SIZE_MASK,
538 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
539 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
540 0x01, RING_BUFFER);
541 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
542 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
543 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
544 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
545 SD_TRANSFER_END, SD_TRANSFER_END);
546 rtsx_pci_send_cmd_no_wait(pcr);
547 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
548 if (err < 0) {
549 sd_clear_error(host);
550 return err;
551 }
552
553 return 0;
554 }
555
sd_enable_initial_mode(struct realtek_pci_sdmmc * host)556 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
557 {
558 rtsx_pci_write_register(host->pcr, SD_CFG1,
559 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
560 }
561
sd_disable_initial_mode(struct realtek_pci_sdmmc * host)562 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
563 {
564 rtsx_pci_write_register(host->pcr, SD_CFG1,
565 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
566 }
567
sd_rw_multi(struct realtek_pci_sdmmc * host,struct mmc_request * mrq)568 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
569 {
570 struct mmc_data *data = mrq->data;
571 int err;
572
573 if (host->sg_count < 0) {
574 data->error = host->sg_count;
575 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
576 __func__, host->sg_count);
577 return data->error;
578 }
579
580 if (data->flags & MMC_DATA_READ) {
581 if (host->initial_mode)
582 sd_disable_initial_mode(host);
583
584 err = sd_read_long_data(host, mrq);
585
586 if (host->initial_mode)
587 sd_enable_initial_mode(host);
588
589 return err;
590 }
591
592 return sd_write_long_data(host, mrq);
593 }
594
sd_normal_rw(struct realtek_pci_sdmmc * host,struct mmc_request * mrq)595 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
596 struct mmc_request *mrq)
597 {
598 struct mmc_command *cmd = mrq->cmd;
599 struct mmc_data *data = mrq->data;
600 u8 *buf;
601
602 buf = kzalloc(data->blksz, GFP_NOIO);
603 if (!buf) {
604 cmd->error = -ENOMEM;
605 return;
606 }
607
608 if (data->flags & MMC_DATA_READ) {
609 if (host->initial_mode)
610 sd_disable_initial_mode(host);
611
612 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
613 data->blksz, 200);
614
615 if (host->initial_mode)
616 sd_enable_initial_mode(host);
617
618 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
619 } else {
620 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
621
622 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
623 data->blksz, 200);
624 }
625
626 kfree(buf);
627 }
628
sd_change_phase(struct realtek_pci_sdmmc * host,u8 sample_point,bool rx)629 static int sd_change_phase(struct realtek_pci_sdmmc *host,
630 u8 sample_point, bool rx)
631 {
632 struct rtsx_pcr *pcr = host->pcr;
633 int err;
634
635 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
636 __func__, rx ? "RX" : "TX", sample_point);
637
638 rtsx_pci_init_cmd(pcr);
639
640 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
641 if (rx)
642 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
643 SD_VPRX_CTL, 0x1F, sample_point);
644 else
645 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
646 SD_VPTX_CTL, 0x1F, sample_point);
647 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
648 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
649 PHASE_NOT_RESET, PHASE_NOT_RESET);
650 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
651 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
652
653 err = rtsx_pci_send_cmd(pcr, 100);
654 if (err < 0)
655 return err;
656
657 return 0;
658 }
659
test_phase_bit(u32 phase_map,unsigned int bit)660 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
661 {
662 bit %= RTSX_PHASE_MAX;
663 return phase_map & (1 << bit);
664 }
665
sd_get_phase_len(u32 phase_map,unsigned int start_bit)666 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
667 {
668 int i;
669
670 for (i = 0; i < RTSX_PHASE_MAX; i++) {
671 if (test_phase_bit(phase_map, start_bit + i) == 0)
672 return i;
673 }
674 return RTSX_PHASE_MAX;
675 }
676
sd_search_final_phase(struct realtek_pci_sdmmc * host,u32 phase_map)677 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
678 {
679 int start = 0, len = 0;
680 int start_final = 0, len_final = 0;
681 u8 final_phase = 0xFF;
682
683 if (phase_map == 0) {
684 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
685 return final_phase;
686 }
687
688 while (start < RTSX_PHASE_MAX) {
689 len = sd_get_phase_len(phase_map, start);
690 if (len_final < len) {
691 start_final = start;
692 len_final = len;
693 }
694 start += len ? len : 1;
695 }
696
697 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
698 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
699 phase_map, len_final, final_phase);
700
701 return final_phase;
702 }
703
sd_wait_data_idle(struct realtek_pci_sdmmc * host)704 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
705 {
706 int err, i;
707 u8 val = 0;
708
709 for (i = 0; i < 100; i++) {
710 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
711 if (val & SD_DATA_IDLE)
712 return;
713
714 udelay(100);
715 }
716 }
717
sd_tuning_rx_cmd(struct realtek_pci_sdmmc * host,u8 opcode,u8 sample_point)718 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
719 u8 opcode, u8 sample_point)
720 {
721 int err;
722 struct mmc_command cmd = {0};
723
724 err = sd_change_phase(host, sample_point, true);
725 if (err < 0)
726 return err;
727
728 cmd.opcode = opcode;
729 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
730 if (err < 0) {
731 /* Wait till SD DATA IDLE */
732 sd_wait_data_idle(host);
733 sd_clear_error(host);
734 return err;
735 }
736
737 return 0;
738 }
739
sd_tuning_phase(struct realtek_pci_sdmmc * host,u8 opcode,u32 * phase_map)740 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
741 u8 opcode, u32 *phase_map)
742 {
743 int err, i;
744 u32 raw_phase_map = 0;
745
746 for (i = 0; i < RTSX_PHASE_MAX; i++) {
747 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
748 if (err == 0)
749 raw_phase_map |= 1 << i;
750 }
751
752 if (phase_map)
753 *phase_map = raw_phase_map;
754
755 return 0;
756 }
757
sd_tuning_rx(struct realtek_pci_sdmmc * host,u8 opcode)758 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
759 {
760 int err, i;
761 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
762 u8 final_phase;
763
764 for (i = 0; i < RX_TUNING_CNT; i++) {
765 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
766 if (err < 0)
767 return err;
768
769 if (raw_phase_map[i] == 0)
770 break;
771 }
772
773 phase_map = 0xFFFFFFFF;
774 for (i = 0; i < RX_TUNING_CNT; i++) {
775 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
776 i, raw_phase_map[i]);
777 phase_map &= raw_phase_map[i];
778 }
779 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
780
781 if (phase_map) {
782 final_phase = sd_search_final_phase(host, phase_map);
783 if (final_phase == 0xFF)
784 return -EINVAL;
785
786 err = sd_change_phase(host, final_phase, true);
787 if (err < 0)
788 return err;
789 } else {
790 return -EINVAL;
791 }
792
793 return 0;
794 }
795
sdio_extblock_cmd(struct mmc_command * cmd,struct mmc_data * data)796 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
797 struct mmc_data *data)
798 {
799 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
800 }
801
sd_rw_cmd(struct mmc_command * cmd)802 static inline int sd_rw_cmd(struct mmc_command *cmd)
803 {
804 return mmc_op_multi(cmd->opcode) ||
805 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
806 (cmd->opcode == MMC_WRITE_BLOCK);
807 }
808
sd_request(struct work_struct * work)809 static void sd_request(struct work_struct *work)
810 {
811 struct realtek_pci_sdmmc *host = container_of(work,
812 struct realtek_pci_sdmmc, work);
813 struct rtsx_pcr *pcr = host->pcr;
814
815 struct mmc_host *mmc = host->mmc;
816 struct mmc_request *mrq = host->mrq;
817 struct mmc_command *cmd = mrq->cmd;
818 struct mmc_data *data = mrq->data;
819
820 unsigned int data_size = 0;
821 int err;
822
823 if (host->eject || !sd_get_cd_int(host)) {
824 cmd->error = -ENOMEDIUM;
825 goto finish;
826 }
827
828 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
829 if (err) {
830 cmd->error = err;
831 goto finish;
832 }
833
834 mutex_lock(&pcr->pcr_mutex);
835
836 rtsx_pci_start_run(pcr);
837
838 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
839 host->initial_mode, host->double_clk, host->vpclk);
840 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
841 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
842 CARD_SHARE_MASK, CARD_SHARE_48_SD);
843
844 mutex_lock(&host->host_mutex);
845 host->mrq = mrq;
846 mutex_unlock(&host->host_mutex);
847
848 if (mrq->data)
849 data_size = data->blocks * data->blksz;
850
851 if (!data_size) {
852 sd_send_cmd_get_rsp(host, cmd);
853 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
854 cmd->error = sd_rw_multi(host, mrq);
855 if (!host->using_cookie)
856 sdmmc_post_req(host->mmc, host->mrq, 0);
857
858 if (mmc_op_multi(cmd->opcode) && mrq->stop)
859 sd_send_cmd_get_rsp(host, mrq->stop);
860 } else {
861 sd_normal_rw(host, mrq);
862 }
863
864 if (mrq->data) {
865 if (cmd->error || data->error)
866 data->bytes_xfered = 0;
867 else
868 data->bytes_xfered = data->blocks * data->blksz;
869 }
870
871 mutex_unlock(&pcr->pcr_mutex);
872
873 finish:
874 if (cmd->error) {
875 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
876 cmd->opcode, cmd->arg, cmd->error);
877 }
878
879 mutex_lock(&host->host_mutex);
880 host->mrq = NULL;
881 mutex_unlock(&host->host_mutex);
882
883 mmc_request_done(mmc, mrq);
884 }
885
sdmmc_request(struct mmc_host * mmc,struct mmc_request * mrq)886 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
887 {
888 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
889 struct mmc_data *data = mrq->data;
890
891 mutex_lock(&host->host_mutex);
892 host->mrq = mrq;
893 mutex_unlock(&host->host_mutex);
894
895 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
896 host->using_cookie = sd_pre_dma_transfer(host, data, false);
897
898 queue_work(host->workq, &host->work);
899 }
900
sd_set_bus_width(struct realtek_pci_sdmmc * host,unsigned char bus_width)901 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
902 unsigned char bus_width)
903 {
904 int err = 0;
905 u8 width[] = {
906 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
907 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
908 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
909 };
910
911 if (bus_width <= MMC_BUS_WIDTH_8)
912 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
913 0x03, width[bus_width]);
914
915 return err;
916 }
917
sd_power_on(struct realtek_pci_sdmmc * host)918 static int sd_power_on(struct realtek_pci_sdmmc *host)
919 {
920 struct rtsx_pcr *pcr = host->pcr;
921 int err;
922
923 if (host->power_state == SDMMC_POWER_ON)
924 return 0;
925
926 rtsx_pci_init_cmd(pcr);
927 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
928 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
929 CARD_SHARE_MASK, CARD_SHARE_48_SD);
930 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
931 SD_CLK_EN, SD_CLK_EN);
932 err = rtsx_pci_send_cmd(pcr, 100);
933 if (err < 0)
934 return err;
935
936 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
937 if (err < 0)
938 return err;
939
940 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
941 if (err < 0)
942 return err;
943
944 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
945 if (err < 0)
946 return err;
947
948 host->power_state = SDMMC_POWER_ON;
949 return 0;
950 }
951
sd_power_off(struct realtek_pci_sdmmc * host)952 static int sd_power_off(struct realtek_pci_sdmmc *host)
953 {
954 struct rtsx_pcr *pcr = host->pcr;
955 int err;
956
957 host->power_state = SDMMC_POWER_OFF;
958
959 rtsx_pci_init_cmd(pcr);
960
961 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
962 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
963
964 err = rtsx_pci_send_cmd(pcr, 100);
965 if (err < 0)
966 return err;
967
968 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
969 if (err < 0)
970 return err;
971
972 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
973 }
974
sd_set_power_mode(struct realtek_pci_sdmmc * host,unsigned char power_mode)975 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
976 unsigned char power_mode)
977 {
978 int err;
979
980 if (power_mode == MMC_POWER_OFF)
981 err = sd_power_off(host);
982 else
983 err = sd_power_on(host);
984
985 return err;
986 }
987
sd_set_timing(struct realtek_pci_sdmmc * host,unsigned char timing)988 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
989 {
990 struct rtsx_pcr *pcr = host->pcr;
991 int err = 0;
992
993 rtsx_pci_init_cmd(pcr);
994
995 switch (timing) {
996 case MMC_TIMING_UHS_SDR104:
997 case MMC_TIMING_UHS_SDR50:
998 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
999 0x0C | SD_ASYNC_FIFO_NOT_RST,
1000 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1001 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1002 CLK_LOW_FREQ, CLK_LOW_FREQ);
1003 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1004 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1005 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1006 break;
1007
1008 case MMC_TIMING_MMC_DDR52:
1009 case MMC_TIMING_UHS_DDR50:
1010 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1011 0x0C | SD_ASYNC_FIFO_NOT_RST,
1012 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1013 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1014 CLK_LOW_FREQ, CLK_LOW_FREQ);
1015 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1016 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1017 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1018 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1019 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1020 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1021 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1022 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1023 break;
1024
1025 case MMC_TIMING_MMC_HS:
1026 case MMC_TIMING_SD_HS:
1027 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1028 0x0C, SD_20_MODE);
1029 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1030 CLK_LOW_FREQ, CLK_LOW_FREQ);
1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1032 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1034 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1035 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1036 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1037 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1038 break;
1039
1040 default:
1041 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1042 SD_CFG1, 0x0C, SD_20_MODE);
1043 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1044 CLK_LOW_FREQ, CLK_LOW_FREQ);
1045 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1046 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1047 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1048 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1049 SD_PUSH_POINT_CTL, 0xFF, 0);
1050 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1051 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1052 break;
1053 }
1054
1055 err = rtsx_pci_send_cmd(pcr, 100);
1056
1057 return err;
1058 }
1059
sdmmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1060 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1061 {
1062 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1063 struct rtsx_pcr *pcr = host->pcr;
1064
1065 if (host->eject)
1066 return;
1067
1068 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1069 return;
1070
1071 mutex_lock(&pcr->pcr_mutex);
1072
1073 rtsx_pci_start_run(pcr);
1074
1075 sd_set_bus_width(host, ios->bus_width);
1076 sd_set_power_mode(host, ios->power_mode);
1077 sd_set_timing(host, ios->timing);
1078
1079 host->vpclk = false;
1080 host->double_clk = true;
1081
1082 switch (ios->timing) {
1083 case MMC_TIMING_UHS_SDR104:
1084 case MMC_TIMING_UHS_SDR50:
1085 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1086 host->vpclk = true;
1087 host->double_clk = false;
1088 break;
1089 case MMC_TIMING_MMC_DDR52:
1090 case MMC_TIMING_UHS_DDR50:
1091 case MMC_TIMING_UHS_SDR25:
1092 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1093 break;
1094 default:
1095 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1096 break;
1097 }
1098
1099 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1100
1101 host->clock = ios->clock;
1102 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1103 host->initial_mode, host->double_clk, host->vpclk);
1104
1105 mutex_unlock(&pcr->pcr_mutex);
1106 }
1107
sdmmc_get_ro(struct mmc_host * mmc)1108 static int sdmmc_get_ro(struct mmc_host *mmc)
1109 {
1110 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1111 struct rtsx_pcr *pcr = host->pcr;
1112 int ro = 0;
1113 u32 val;
1114
1115 if (host->eject)
1116 return -ENOMEDIUM;
1117
1118 mutex_lock(&pcr->pcr_mutex);
1119
1120 rtsx_pci_start_run(pcr);
1121
1122 /* Check SD mechanical write-protect switch */
1123 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1124 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1125 if (val & SD_WRITE_PROTECT)
1126 ro = 1;
1127
1128 mutex_unlock(&pcr->pcr_mutex);
1129
1130 return ro;
1131 }
1132
sdmmc_get_cd(struct mmc_host * mmc)1133 static int sdmmc_get_cd(struct mmc_host *mmc)
1134 {
1135 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1136 struct rtsx_pcr *pcr = host->pcr;
1137 int cd = 0;
1138 u32 val;
1139
1140 if (host->eject)
1141 return cd;
1142
1143 mutex_lock(&pcr->pcr_mutex);
1144
1145 rtsx_pci_start_run(pcr);
1146
1147 /* Check SD card detect */
1148 val = rtsx_pci_card_exist(pcr);
1149 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1150 if (val & SD_EXIST)
1151 cd = 1;
1152
1153 mutex_unlock(&pcr->pcr_mutex);
1154
1155 return cd;
1156 }
1157
sd_wait_voltage_stable_1(struct realtek_pci_sdmmc * host)1158 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1159 {
1160 struct rtsx_pcr *pcr = host->pcr;
1161 int err;
1162 u8 stat;
1163
1164 /* Reference to Signal Voltage Switch Sequence in SD spec.
1165 * Wait for a period of time so that the card can drive SD_CMD and
1166 * SD_DAT[3:0] to low after sending back CMD11 response.
1167 */
1168 mdelay(1);
1169
1170 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1171 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1172 * abort the voltage switch sequence;
1173 */
1174 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1175 if (err < 0)
1176 return err;
1177
1178 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1179 SD_DAT1_STATUS | SD_DAT0_STATUS))
1180 return -EINVAL;
1181
1182 /* Stop toggle SD clock */
1183 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1184 0xFF, SD_CLK_FORCE_STOP);
1185 if (err < 0)
1186 return err;
1187
1188 return 0;
1189 }
1190
sd_wait_voltage_stable_2(struct realtek_pci_sdmmc * host)1191 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1192 {
1193 struct rtsx_pcr *pcr = host->pcr;
1194 int err;
1195 u8 stat, mask, val;
1196
1197 /* Wait 1.8V output of voltage regulator in card stable */
1198 msleep(50);
1199
1200 /* Toggle SD clock again */
1201 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1202 if (err < 0)
1203 return err;
1204
1205 /* Wait for a period of time so that the card can drive
1206 * SD_DAT[3:0] to high at 1.8V
1207 */
1208 msleep(20);
1209
1210 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1211 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1212 if (err < 0)
1213 return err;
1214
1215 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1216 SD_DAT1_STATUS | SD_DAT0_STATUS;
1217 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1218 SD_DAT1_STATUS | SD_DAT0_STATUS;
1219 if ((stat & mask) != val) {
1220 dev_dbg(sdmmc_dev(host),
1221 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1222 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1223 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1224 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1225 return -EINVAL;
1226 }
1227
1228 return 0;
1229 }
1230
sdmmc_switch_voltage(struct mmc_host * mmc,struct mmc_ios * ios)1231 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1232 {
1233 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1234 struct rtsx_pcr *pcr = host->pcr;
1235 int err = 0;
1236 u8 voltage;
1237
1238 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1239 __func__, ios->signal_voltage);
1240
1241 if (host->eject)
1242 return -ENOMEDIUM;
1243
1244 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1245 if (err)
1246 return err;
1247
1248 mutex_lock(&pcr->pcr_mutex);
1249
1250 rtsx_pci_start_run(pcr);
1251
1252 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1253 voltage = OUTPUT_3V3;
1254 else
1255 voltage = OUTPUT_1V8;
1256
1257 if (voltage == OUTPUT_1V8) {
1258 err = sd_wait_voltage_stable_1(host);
1259 if (err < 0)
1260 goto out;
1261 }
1262
1263 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1264 if (err < 0)
1265 goto out;
1266
1267 if (voltage == OUTPUT_1V8) {
1268 err = sd_wait_voltage_stable_2(host);
1269 if (err < 0)
1270 goto out;
1271 }
1272
1273 out:
1274 /* Stop toggle SD clock in idle */
1275 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1276 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1277
1278 mutex_unlock(&pcr->pcr_mutex);
1279
1280 return err;
1281 }
1282
sdmmc_execute_tuning(struct mmc_host * mmc,u32 opcode)1283 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1284 {
1285 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1286 struct rtsx_pcr *pcr = host->pcr;
1287 int err = 0;
1288
1289 if (host->eject)
1290 return -ENOMEDIUM;
1291
1292 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1293 if (err)
1294 return err;
1295
1296 mutex_lock(&pcr->pcr_mutex);
1297
1298 rtsx_pci_start_run(pcr);
1299
1300 /* Set initial TX phase */
1301 switch (mmc->ios.timing) {
1302 case MMC_TIMING_UHS_SDR104:
1303 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1304 break;
1305
1306 case MMC_TIMING_UHS_SDR50:
1307 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1308 break;
1309
1310 case MMC_TIMING_UHS_DDR50:
1311 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1312 break;
1313
1314 default:
1315 err = 0;
1316 }
1317
1318 if (err)
1319 goto out;
1320
1321 /* Tuning RX phase */
1322 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1323 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1324 err = sd_tuning_rx(host, opcode);
1325 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1326 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1327
1328 out:
1329 mutex_unlock(&pcr->pcr_mutex);
1330
1331 return err;
1332 }
1333
1334 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1335 .pre_req = sdmmc_pre_req,
1336 .post_req = sdmmc_post_req,
1337 .request = sdmmc_request,
1338 .set_ios = sdmmc_set_ios,
1339 .get_ro = sdmmc_get_ro,
1340 .get_cd = sdmmc_get_cd,
1341 .start_signal_voltage_switch = sdmmc_switch_voltage,
1342 .execute_tuning = sdmmc_execute_tuning,
1343 };
1344
init_extra_caps(struct realtek_pci_sdmmc * host)1345 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1346 {
1347 struct mmc_host *mmc = host->mmc;
1348 struct rtsx_pcr *pcr = host->pcr;
1349
1350 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1351
1352 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1353 mmc->caps |= MMC_CAP_UHS_SDR50;
1354 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1355 mmc->caps |= MMC_CAP_UHS_SDR104;
1356 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1357 mmc->caps |= MMC_CAP_UHS_DDR50;
1358 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1359 mmc->caps |= MMC_CAP_1_8V_DDR;
1360 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1361 mmc->caps |= MMC_CAP_8_BIT_DATA;
1362 }
1363
realtek_init_host(struct realtek_pci_sdmmc * host)1364 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1365 {
1366 struct mmc_host *mmc = host->mmc;
1367
1368 mmc->f_min = 250000;
1369 mmc->f_max = 208000000;
1370 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1371 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1372 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1373 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1374 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1375 mmc->max_current_330 = 400;
1376 mmc->max_current_180 = 800;
1377 mmc->ops = &realtek_pci_sdmmc_ops;
1378
1379 init_extra_caps(host);
1380
1381 mmc->max_segs = 256;
1382 mmc->max_seg_size = 65536;
1383 mmc->max_blk_size = 512;
1384 mmc->max_blk_count = 65535;
1385 mmc->max_req_size = 524288;
1386 }
1387
rtsx_pci_sdmmc_card_event(struct platform_device * pdev)1388 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1389 {
1390 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1391
1392 host->cookie = -1;
1393 mmc_detect_change(host->mmc, 0);
1394 }
1395
rtsx_pci_sdmmc_drv_probe(struct platform_device * pdev)1396 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1397 {
1398 struct mmc_host *mmc;
1399 struct realtek_pci_sdmmc *host;
1400 struct rtsx_pcr *pcr;
1401 struct pcr_handle *handle = pdev->dev.platform_data;
1402
1403 if (!handle)
1404 return -ENXIO;
1405
1406 pcr = handle->pcr;
1407 if (!pcr)
1408 return -ENXIO;
1409
1410 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1411
1412 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1413 if (!mmc)
1414 return -ENOMEM;
1415
1416 host = mmc_priv(mmc);
1417 host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME);
1418 if (!host->workq) {
1419 mmc_free_host(mmc);
1420 return -ENOMEM;
1421 }
1422 host->pcr = pcr;
1423 host->mmc = mmc;
1424 host->pdev = pdev;
1425 host->cookie = -1;
1426 host->power_state = SDMMC_POWER_OFF;
1427 INIT_WORK(&host->work, sd_request);
1428 platform_set_drvdata(pdev, host);
1429 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1430 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1431
1432 mutex_init(&host->host_mutex);
1433
1434 realtek_init_host(host);
1435
1436 mmc_add_host(mmc);
1437
1438 return 0;
1439 }
1440
rtsx_pci_sdmmc_drv_remove(struct platform_device * pdev)1441 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1442 {
1443 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1444 struct rtsx_pcr *pcr;
1445 struct mmc_host *mmc;
1446
1447 if (!host)
1448 return 0;
1449
1450 pcr = host->pcr;
1451 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1452 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1453 mmc = host->mmc;
1454
1455 cancel_work_sync(&host->work);
1456
1457 mutex_lock(&host->host_mutex);
1458 if (host->mrq) {
1459 dev_dbg(&(pdev->dev),
1460 "%s: Controller removed during transfer\n",
1461 mmc_hostname(mmc));
1462
1463 rtsx_pci_complete_unfinished_transfer(pcr);
1464
1465 host->mrq->cmd->error = -ENOMEDIUM;
1466 if (host->mrq->stop)
1467 host->mrq->stop->error = -ENOMEDIUM;
1468 mmc_request_done(mmc, host->mrq);
1469 }
1470 mutex_unlock(&host->host_mutex);
1471
1472 mmc_remove_host(mmc);
1473 host->eject = true;
1474
1475 flush_workqueue(host->workq);
1476 destroy_workqueue(host->workq);
1477 host->workq = NULL;
1478
1479 mmc_free_host(mmc);
1480
1481 dev_dbg(&(pdev->dev),
1482 ": Realtek PCI-E SDMMC controller has been removed\n");
1483
1484 return 0;
1485 }
1486
1487 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1488 {
1489 .name = DRV_NAME_RTSX_PCI_SDMMC,
1490 }, {
1491 /* sentinel */
1492 }
1493 };
1494 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1495
1496 static struct platform_driver rtsx_pci_sdmmc_driver = {
1497 .probe = rtsx_pci_sdmmc_drv_probe,
1498 .remove = rtsx_pci_sdmmc_drv_remove,
1499 .id_table = rtsx_pci_sdmmc_ids,
1500 .driver = {
1501 .name = DRV_NAME_RTSX_PCI_SDMMC,
1502 },
1503 };
1504 module_platform_driver(rtsx_pci_sdmmc_driver);
1505
1506 MODULE_LICENSE("GPL");
1507 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1508 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
1509