1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
44 #endif
45
46 #define MAX_TUNING_LOOP 40
47
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
50
51 static void sdhci_finish_data(struct sdhci_host *);
52
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data);
58 static int sdhci_do_get_cd(struct sdhci_host *host);
59
60 #ifdef CONFIG_PM
61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
65 #else
sdhci_runtime_pm_get(struct sdhci_host * host)66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67 {
68 return 0;
69 }
sdhci_runtime_pm_put(struct sdhci_host * host)70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71 {
72 return 0;
73 }
sdhci_runtime_pm_bus_on(struct sdhci_host * host)74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
75 {
76 }
sdhci_runtime_pm_bus_off(struct sdhci_host * host)77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
78 {
79 }
80 #endif
81
sdhci_dumpregs(struct sdhci_host * host)82 static void sdhci_dumpregs(struct sdhci_host *host)
83 {
84 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
85 mmc_hostname(host->mmc));
86
87 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
88 sdhci_readl(host, SDHCI_DMA_ADDRESS),
89 sdhci_readw(host, SDHCI_HOST_VERSION));
90 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
91 sdhci_readw(host, SDHCI_BLOCK_SIZE),
92 sdhci_readw(host, SDHCI_BLOCK_COUNT));
93 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
94 sdhci_readl(host, SDHCI_ARGUMENT),
95 sdhci_readw(host, SDHCI_TRANSFER_MODE));
96 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
97 sdhci_readl(host, SDHCI_PRESENT_STATE),
98 sdhci_readb(host, SDHCI_HOST_CONTROL));
99 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
100 sdhci_readb(host, SDHCI_POWER_CONTROL),
101 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
102 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
103 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
104 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
105 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
106 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
107 sdhci_readl(host, SDHCI_INT_STATUS));
108 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109 sdhci_readl(host, SDHCI_INT_ENABLE),
110 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
111 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112 sdhci_readw(host, SDHCI_ACMD12_ERR),
113 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
114 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
115 sdhci_readl(host, SDHCI_CAPABILITIES),
116 sdhci_readl(host, SDHCI_CAPABILITIES_1));
117 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
118 sdhci_readw(host, SDHCI_COMMAND),
119 sdhci_readl(host, SDHCI_MAX_CURRENT));
120 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
121 sdhci_readw(host, SDHCI_HOST_CONTROL2));
122
123 if (host->flags & SDHCI_USE_ADMA) {
124 if (host->flags & SDHCI_USE_64_BIT_DMA)
125 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host->ioaddr + SDHCI_ADMA_ERROR),
127 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
129 else
130 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host->ioaddr + SDHCI_ADMA_ERROR),
132 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
133 }
134
135 pr_debug(DRIVER_NAME ": ===========================================\n");
136 }
137
138 /*****************************************************************************\
139 * *
140 * Low level functions *
141 * *
142 \*****************************************************************************/
143
sdhci_set_card_detection(struct sdhci_host * host,bool enable)144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
145 {
146 u32 present;
147
148 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
149 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
150 return;
151
152 if (enable) {
153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154 SDHCI_CARD_PRESENT;
155
156 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
157 SDHCI_INT_CARD_INSERT;
158 } else {
159 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
160 }
161
162 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
163 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
164 }
165
sdhci_enable_card_detection(struct sdhci_host * host)166 static void sdhci_enable_card_detection(struct sdhci_host *host)
167 {
168 sdhci_set_card_detection(host, true);
169 }
170
sdhci_disable_card_detection(struct sdhci_host * host)171 static void sdhci_disable_card_detection(struct sdhci_host *host)
172 {
173 sdhci_set_card_detection(host, false);
174 }
175
sdhci_reset(struct sdhci_host * host,u8 mask)176 void sdhci_reset(struct sdhci_host *host, u8 mask)
177 {
178 unsigned long timeout;
179
180 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
181
182 if (mask & SDHCI_RESET_ALL) {
183 host->clock = 0;
184 /* Reset-all turns off SD Bus Power */
185 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
186 sdhci_runtime_pm_bus_off(host);
187 }
188
189 /* Wait max 100 ms */
190 timeout = 100;
191
192 /* hw clears the bit when it's done */
193 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
194 if (timeout == 0) {
195 pr_err("%s: Reset 0x%x never completed.\n",
196 mmc_hostname(host->mmc), (int)mask);
197 sdhci_dumpregs(host);
198 return;
199 }
200 timeout--;
201 mdelay(1);
202 }
203 }
204 EXPORT_SYMBOL_GPL(sdhci_reset);
205
sdhci_do_reset(struct sdhci_host * host,u8 mask)206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
207 {
208 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
209 if (!sdhci_do_get_cd(host))
210 return;
211 }
212
213 host->ops->reset(host, mask);
214
215 if (mask & SDHCI_RESET_ALL) {
216 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
217 if (host->ops->enable_dma)
218 host->ops->enable_dma(host);
219 }
220
221 /* Resetting the controller clears many */
222 host->preset_enabled = false;
223 }
224 }
225
226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
227
sdhci_init(struct sdhci_host * host,int soft)228 static void sdhci_init(struct sdhci_host *host, int soft)
229 {
230 if (soft)
231 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
232 else
233 sdhci_do_reset(host, SDHCI_RESET_ALL);
234
235 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
237 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
238 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
239 SDHCI_INT_RESPONSE;
240
241 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
242 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
243
244 if (soft) {
245 /* force clock reconfiguration */
246 host->clock = 0;
247 sdhci_set_ios(host->mmc, &host->mmc->ios);
248 }
249 }
250
sdhci_reinit(struct sdhci_host * host)251 static void sdhci_reinit(struct sdhci_host *host)
252 {
253 sdhci_init(host, 0);
254 sdhci_enable_card_detection(host);
255 }
256
sdhci_activate_led(struct sdhci_host * host)257 static void sdhci_activate_led(struct sdhci_host *host)
258 {
259 u8 ctrl;
260
261 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
262 ctrl |= SDHCI_CTRL_LED;
263 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
264 }
265
sdhci_deactivate_led(struct sdhci_host * host)266 static void sdhci_deactivate_led(struct sdhci_host *host)
267 {
268 u8 ctrl;
269
270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
271 ctrl &= ~SDHCI_CTRL_LED;
272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
273 }
274
275 #ifdef SDHCI_USE_LEDS_CLASS
sdhci_led_control(struct led_classdev * led,enum led_brightness brightness)276 static void sdhci_led_control(struct led_classdev *led,
277 enum led_brightness brightness)
278 {
279 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
280 unsigned long flags;
281
282 spin_lock_irqsave(&host->lock, flags);
283
284 if (host->runtime_suspended)
285 goto out;
286
287 if (brightness == LED_OFF)
288 sdhci_deactivate_led(host);
289 else
290 sdhci_activate_led(host);
291 out:
292 spin_unlock_irqrestore(&host->lock, flags);
293 }
294 #endif
295
296 /*****************************************************************************\
297 * *
298 * Core functions *
299 * *
300 \*****************************************************************************/
301
sdhci_read_block_pio(struct sdhci_host * host)302 static void sdhci_read_block_pio(struct sdhci_host *host)
303 {
304 unsigned long flags;
305 size_t blksize, len, chunk;
306 u32 uninitialized_var(scratch);
307 u8 *buf;
308
309 DBG("PIO reading\n");
310
311 blksize = host->data->blksz;
312 chunk = 0;
313
314 local_irq_save(flags);
315
316 while (blksize) {
317 BUG_ON(!sg_miter_next(&host->sg_miter));
318
319 len = min(host->sg_miter.length, blksize);
320
321 blksize -= len;
322 host->sg_miter.consumed = len;
323
324 buf = host->sg_miter.addr;
325
326 while (len) {
327 if (chunk == 0) {
328 scratch = sdhci_readl(host, SDHCI_BUFFER);
329 chunk = 4;
330 }
331
332 *buf = scratch & 0xFF;
333
334 buf++;
335 scratch >>= 8;
336 chunk--;
337 len--;
338 }
339 }
340
341 sg_miter_stop(&host->sg_miter);
342
343 local_irq_restore(flags);
344 }
345
sdhci_write_block_pio(struct sdhci_host * host)346 static void sdhci_write_block_pio(struct sdhci_host *host)
347 {
348 unsigned long flags;
349 size_t blksize, len, chunk;
350 u32 scratch;
351 u8 *buf;
352
353 DBG("PIO writing\n");
354
355 blksize = host->data->blksz;
356 chunk = 0;
357 scratch = 0;
358
359 local_irq_save(flags);
360
361 while (blksize) {
362 BUG_ON(!sg_miter_next(&host->sg_miter));
363
364 len = min(host->sg_miter.length, blksize);
365
366 blksize -= len;
367 host->sg_miter.consumed = len;
368
369 buf = host->sg_miter.addr;
370
371 while (len) {
372 scratch |= (u32)*buf << (chunk * 8);
373
374 buf++;
375 chunk++;
376 len--;
377
378 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
379 sdhci_writel(host, scratch, SDHCI_BUFFER);
380 chunk = 0;
381 scratch = 0;
382 }
383 }
384 }
385
386 sg_miter_stop(&host->sg_miter);
387
388 local_irq_restore(flags);
389 }
390
sdhci_transfer_pio(struct sdhci_host * host)391 static void sdhci_transfer_pio(struct sdhci_host *host)
392 {
393 u32 mask;
394
395 BUG_ON(!host->data);
396
397 if (host->blocks == 0)
398 return;
399
400 if (host->data->flags & MMC_DATA_READ)
401 mask = SDHCI_DATA_AVAILABLE;
402 else
403 mask = SDHCI_SPACE_AVAILABLE;
404
405 /*
406 * Some controllers (JMicron JMB38x) mess up the buffer bits
407 * for transfers < 4 bytes. As long as it is just one block,
408 * we can ignore the bits.
409 */
410 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
411 (host->data->blocks == 1))
412 mask = ~0;
413
414 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
415 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
416 udelay(100);
417
418 if (host->data->flags & MMC_DATA_READ)
419 sdhci_read_block_pio(host);
420 else
421 sdhci_write_block_pio(host);
422
423 host->blocks--;
424 if (host->blocks == 0)
425 break;
426 }
427
428 DBG("PIO transfer complete.\n");
429 }
430
sdhci_kmap_atomic(struct scatterlist * sg,unsigned long * flags)431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
432 {
433 local_irq_save(*flags);
434 return kmap_atomic(sg_page(sg)) + sg->offset;
435 }
436
sdhci_kunmap_atomic(void * buffer,unsigned long * flags)437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
438 {
439 kunmap_atomic(buffer);
440 local_irq_restore(*flags);
441 }
442
sdhci_adma_write_desc(struct sdhci_host * host,void * desc,dma_addr_t addr,int len,unsigned cmd)443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
444 dma_addr_t addr, int len, unsigned cmd)
445 {
446 struct sdhci_adma2_64_desc *dma_desc = desc;
447
448 /* 32-bit and 64-bit descriptors have these members in same position */
449 dma_desc->cmd = cpu_to_le16(cmd);
450 dma_desc->len = cpu_to_le16(len);
451 dma_desc->addr_lo = cpu_to_le32((u32)addr);
452
453 if (host->flags & SDHCI_USE_64_BIT_DMA)
454 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
455 }
456
sdhci_adma_mark_end(void * desc)457 static void sdhci_adma_mark_end(void *desc)
458 {
459 struct sdhci_adma2_64_desc *dma_desc = desc;
460
461 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
462 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
463 }
464
sdhci_adma_table_pre(struct sdhci_host * host,struct mmc_data * data)465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466 struct mmc_data *data)
467 {
468 int direction;
469
470 void *desc;
471 void *align;
472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;
480
481 /*
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
492 host->align_buffer, host->align_buffer_sz, direction);
493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
494 goto fail;
495 BUG_ON(host->align_addr & SDHCI_ADMA2_MASK);
496
497 host->sg_count = sdhci_pre_dma_transfer(host, data);
498 if (host->sg_count < 0)
499 goto unmap_align;
500
501 desc = host->adma_table;
502 align = host->align_buffer;
503
504 align_addr = host->align_addr;
505
506 for_each_sg(data->sg, sg, host->sg_count, i) {
507 addr = sg_dma_address(sg);
508 len = sg_dma_len(sg);
509
510 /*
511 * The SDHCI specification states that ADMA
512 * addresses must be 32-bit aligned. If they
513 * aren't, then we use a bounce buffer for
514 * the (up to three) bytes that screw up the
515 * alignment.
516 */
517 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
518 SDHCI_ADMA2_MASK;
519 if (offset) {
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
522 memcpy(align, buffer, offset);
523 sdhci_kunmap_atomic(buffer, &flags);
524 }
525
526 /* tran, valid */
527 sdhci_adma_write_desc(host, desc, align_addr, offset,
528 ADMA2_TRAN_VALID);
529
530 BUG_ON(offset > 65536);
531
532 align += SDHCI_ADMA2_ALIGN;
533 align_addr += SDHCI_ADMA2_ALIGN;
534
535 desc += host->desc_sz;
536
537 addr += offset;
538 len -= offset;
539 }
540
541 BUG_ON(len > 65536);
542
543 if (len) {
544 /* tran, valid */
545 sdhci_adma_write_desc(host, desc, addr, len,
546 ADMA2_TRAN_VALID);
547 desc += host->desc_sz;
548 }
549
550 /*
551 * If this triggers then we have a calculation bug
552 * somewhere. :/
553 */
554 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
555 }
556
557 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
558 /*
559 * Mark the last descriptor as the terminating descriptor
560 */
561 if (desc != host->adma_table) {
562 desc -= host->desc_sz;
563 sdhci_adma_mark_end(desc);
564 }
565 } else {
566 /*
567 * Add a terminating entry.
568 */
569
570 /* nop, end, valid */
571 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
572 }
573
574 /*
575 * Resync align buffer as we might have changed it.
576 */
577 if (data->flags & MMC_DATA_WRITE) {
578 dma_sync_single_for_device(mmc_dev(host->mmc),
579 host->align_addr, host->align_buffer_sz, direction);
580 }
581
582 return 0;
583
584 unmap_align:
585 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
586 host->align_buffer_sz, direction);
587 fail:
588 return -EINVAL;
589 }
590
sdhci_adma_table_post(struct sdhci_host * host,struct mmc_data * data)591 static void sdhci_adma_table_post(struct sdhci_host *host,
592 struct mmc_data *data)
593 {
594 int direction;
595
596 struct scatterlist *sg;
597 int i, size;
598 void *align;
599 char *buffer;
600 unsigned long flags;
601 bool has_unaligned;
602
603 if (data->flags & MMC_DATA_READ)
604 direction = DMA_FROM_DEVICE;
605 else
606 direction = DMA_TO_DEVICE;
607
608 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
609 host->align_buffer_sz, direction);
610
611 /* Do a quick scan of the SG list for any unaligned mappings */
612 has_unaligned = false;
613 for_each_sg(data->sg, sg, host->sg_count, i)
614 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
615 has_unaligned = true;
616 break;
617 }
618
619 if (has_unaligned && data->flags & MMC_DATA_READ) {
620 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
621 data->sg_len, direction);
622
623 align = host->align_buffer;
624
625 for_each_sg(data->sg, sg, host->sg_count, i) {
626 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
627 size = SDHCI_ADMA2_ALIGN -
628 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
629
630 buffer = sdhci_kmap_atomic(sg, &flags);
631 memcpy(buffer, align, size);
632 sdhci_kunmap_atomic(buffer, &flags);
633
634 align += SDHCI_ADMA2_ALIGN;
635 }
636 }
637 }
638
639 if (data->host_cookie == COOKIE_MAPPED) {
640 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
641 data->sg_len, direction);
642 data->host_cookie = COOKIE_UNMAPPED;
643 }
644 }
645
sdhci_calc_timeout(struct sdhci_host * host,struct mmc_command * cmd)646 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
647 {
648 u8 count;
649 struct mmc_data *data = cmd->data;
650 unsigned target_timeout, current_timeout;
651
652 /*
653 * If the host controller provides us with an incorrect timeout
654 * value, just skip the check and use 0xE. The hardware may take
655 * longer to time out, but that's much better than having a too-short
656 * timeout value.
657 */
658 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
659 return 0xE;
660
661 /* Unspecified timeout, assume max */
662 if (!data && !cmd->busy_timeout)
663 return 0xE;
664
665 /* timeout in us */
666 if (!data)
667 target_timeout = cmd->busy_timeout * 1000;
668 else {
669 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
670 if (host->clock && data->timeout_clks) {
671 unsigned long long val;
672
673 /*
674 * data->timeout_clks is in units of clock cycles.
675 * host->clock is in Hz. target_timeout is in us.
676 * Hence, us = 1000000 * cycles / Hz. Round up.
677 */
678 val = 1000000ULL * data->timeout_clks;
679 if (do_div(val, host->clock))
680 target_timeout++;
681 target_timeout += val;
682 }
683 }
684
685 /*
686 * Figure out needed cycles.
687 * We do this in steps in order to fit inside a 32 bit int.
688 * The first step is the minimum timeout, which will have a
689 * minimum resolution of 6 bits:
690 * (1) 2^13*1000 > 2^22,
691 * (2) host->timeout_clk < 2^16
692 * =>
693 * (1) / (2) > 2^6
694 */
695 count = 0;
696 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
697 while (current_timeout < target_timeout) {
698 count++;
699 current_timeout <<= 1;
700 if (count >= 0xF)
701 break;
702 }
703
704 if (count >= 0xF) {
705 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
706 mmc_hostname(host->mmc), count, cmd->opcode);
707 count = 0xE;
708 }
709
710 return count;
711 }
712
sdhci_set_transfer_irqs(struct sdhci_host * host)713 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
714 {
715 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
716 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
717
718 if (host->flags & SDHCI_REQ_USE_DMA)
719 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
720 else
721 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
722
723 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
724 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
725 }
726
sdhci_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)727 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
728 {
729 u8 count;
730
731 if (host->ops->set_timeout) {
732 host->ops->set_timeout(host, cmd);
733 } else {
734 count = sdhci_calc_timeout(host, cmd);
735 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
736 }
737 }
738
sdhci_prepare_data(struct sdhci_host * host,struct mmc_command * cmd)739 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
740 {
741 u8 ctrl;
742 struct mmc_data *data = cmd->data;
743 int ret;
744
745 WARN_ON(host->data);
746
747 if (data || (cmd->flags & MMC_RSP_BUSY))
748 sdhci_set_timeout(host, cmd);
749
750 if (!data)
751 return;
752
753 /* Sanity checks */
754 BUG_ON(data->blksz * data->blocks > 524288);
755 BUG_ON(data->blksz > host->mmc->max_blk_size);
756 BUG_ON(data->blocks > 65535);
757
758 host->data = data;
759 host->data_early = 0;
760 host->data->bytes_xfered = 0;
761
762 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
763 host->flags |= SDHCI_REQ_USE_DMA;
764
765 /*
766 * FIXME: This doesn't account for merging when mapping the
767 * scatterlist.
768 */
769 if (host->flags & SDHCI_REQ_USE_DMA) {
770 int broken, i;
771 struct scatterlist *sg;
772
773 broken = 0;
774 if (host->flags & SDHCI_USE_ADMA) {
775 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
776 broken = 1;
777 } else {
778 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
779 broken = 1;
780 }
781
782 if (unlikely(broken)) {
783 for_each_sg(data->sg, sg, data->sg_len, i) {
784 if (sg->length & 0x3) {
785 DBG("Reverting to PIO because of "
786 "transfer size (%d)\n",
787 sg->length);
788 host->flags &= ~SDHCI_REQ_USE_DMA;
789 break;
790 }
791 }
792 }
793 }
794
795 /*
796 * The assumption here being that alignment is the same after
797 * translation to device address space.
798 */
799 if (host->flags & SDHCI_REQ_USE_DMA) {
800 int broken, i;
801 struct scatterlist *sg;
802
803 broken = 0;
804 if (host->flags & SDHCI_USE_ADMA) {
805 /*
806 * As we use 3 byte chunks to work around
807 * alignment problems, we need to check this
808 * quirk.
809 */
810 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
811 broken = 1;
812 } else {
813 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
814 broken = 1;
815 }
816
817 if (unlikely(broken)) {
818 for_each_sg(data->sg, sg, data->sg_len, i) {
819 if (sg->offset & 0x3) {
820 DBG("Reverting to PIO because of "
821 "bad alignment\n");
822 host->flags &= ~SDHCI_REQ_USE_DMA;
823 break;
824 }
825 }
826 }
827 }
828
829 if (host->flags & SDHCI_REQ_USE_DMA) {
830 if (host->flags & SDHCI_USE_ADMA) {
831 ret = sdhci_adma_table_pre(host, data);
832 if (ret) {
833 /*
834 * This only happens when someone fed
835 * us an invalid request.
836 */
837 WARN_ON(1);
838 host->flags &= ~SDHCI_REQ_USE_DMA;
839 } else {
840 sdhci_writel(host, host->adma_addr,
841 SDHCI_ADMA_ADDRESS);
842 if (host->flags & SDHCI_USE_64_BIT_DMA)
843 sdhci_writel(host,
844 (u64)host->adma_addr >> 32,
845 SDHCI_ADMA_ADDRESS_HI);
846 }
847 } else {
848 int sg_cnt;
849
850 sg_cnt = sdhci_pre_dma_transfer(host, data);
851 if (sg_cnt <= 0) {
852 /*
853 * This only happens when someone fed
854 * us an invalid request.
855 */
856 WARN_ON(1);
857 host->flags &= ~SDHCI_REQ_USE_DMA;
858 } else {
859 WARN_ON(sg_cnt != 1);
860 sdhci_writel(host, sg_dma_address(data->sg),
861 SDHCI_DMA_ADDRESS);
862 }
863 }
864 }
865
866 /*
867 * Always adjust the DMA selection as some controllers
868 * (e.g. JMicron) can't do PIO properly when the selection
869 * is ADMA.
870 */
871 if (host->version >= SDHCI_SPEC_200) {
872 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
873 ctrl &= ~SDHCI_CTRL_DMA_MASK;
874 if ((host->flags & SDHCI_REQ_USE_DMA) &&
875 (host->flags & SDHCI_USE_ADMA)) {
876 if (host->flags & SDHCI_USE_64_BIT_DMA)
877 ctrl |= SDHCI_CTRL_ADMA64;
878 else
879 ctrl |= SDHCI_CTRL_ADMA32;
880 } else {
881 ctrl |= SDHCI_CTRL_SDMA;
882 }
883 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
884 }
885
886 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
887 int flags;
888
889 flags = SG_MITER_ATOMIC;
890 if (host->data->flags & MMC_DATA_READ)
891 flags |= SG_MITER_TO_SG;
892 else
893 flags |= SG_MITER_FROM_SG;
894 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
895 host->blocks = data->blocks;
896 }
897
898 sdhci_set_transfer_irqs(host);
899
900 /* Set the DMA boundary value and block size */
901 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
902 data->blksz), SDHCI_BLOCK_SIZE);
903 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
904 }
905
sdhci_set_transfer_mode(struct sdhci_host * host,struct mmc_command * cmd)906 static void sdhci_set_transfer_mode(struct sdhci_host *host,
907 struct mmc_command *cmd)
908 {
909 u16 mode = 0;
910 struct mmc_data *data = cmd->data;
911
912 if (data == NULL) {
913 if (host->quirks2 &
914 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
915 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
916 } else {
917 /* clear Auto CMD settings for no data CMDs */
918 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
919 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
920 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
921 }
922 return;
923 }
924
925 WARN_ON(!host->data);
926
927 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
928 mode = SDHCI_TRNS_BLK_CNT_EN;
929
930 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
931 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
932 /*
933 * If we are sending CMD23, CMD12 never gets sent
934 * on successful completion (so no Auto-CMD12).
935 */
936 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
937 (cmd->opcode != SD_IO_RW_EXTENDED))
938 mode |= SDHCI_TRNS_AUTO_CMD12;
939 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
940 mode |= SDHCI_TRNS_AUTO_CMD23;
941 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
942 }
943 }
944
945 if (data->flags & MMC_DATA_READ)
946 mode |= SDHCI_TRNS_READ;
947 if (host->flags & SDHCI_REQ_USE_DMA)
948 mode |= SDHCI_TRNS_DMA;
949
950 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
951 }
952
sdhci_finish_data(struct sdhci_host * host)953 static void sdhci_finish_data(struct sdhci_host *host)
954 {
955 struct mmc_data *data;
956
957 BUG_ON(!host->data);
958
959 data = host->data;
960 host->data = NULL;
961
962 if (host->flags & SDHCI_REQ_USE_DMA) {
963 if (host->flags & SDHCI_USE_ADMA)
964 sdhci_adma_table_post(host, data);
965 else {
966 if (data->host_cookie == COOKIE_MAPPED) {
967 dma_unmap_sg(mmc_dev(host->mmc),
968 data->sg, data->sg_len,
969 (data->flags & MMC_DATA_READ) ?
970 DMA_FROM_DEVICE : DMA_TO_DEVICE);
971 data->host_cookie = COOKIE_UNMAPPED;
972 }
973 }
974 }
975
976 /*
977 * The specification states that the block count register must
978 * be updated, but it does not specify at what point in the
979 * data flow. That makes the register entirely useless to read
980 * back so we have to assume that nothing made it to the card
981 * in the event of an error.
982 */
983 if (data->error)
984 data->bytes_xfered = 0;
985 else
986 data->bytes_xfered = data->blksz * data->blocks;
987
988 /*
989 * Need to send CMD12 if -
990 * a) open-ended multiblock transfer (no CMD23)
991 * b) error in multiblock transfer
992 */
993 if (data->stop &&
994 (data->error ||
995 !host->mrq->sbc)) {
996
997 /*
998 * The controller needs a reset of internal state machines
999 * upon error conditions.
1000 */
1001 if (data->error) {
1002 sdhci_do_reset(host, SDHCI_RESET_CMD);
1003 sdhci_do_reset(host, SDHCI_RESET_DATA);
1004 }
1005
1006 sdhci_send_command(host, data->stop);
1007 } else
1008 tasklet_schedule(&host->finish_tasklet);
1009 }
1010
sdhci_send_command(struct sdhci_host * host,struct mmc_command * cmd)1011 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1012 {
1013 int flags;
1014 u32 mask;
1015 unsigned long timeout;
1016
1017 WARN_ON(host->cmd);
1018
1019 /* Wait max 10 ms */
1020 timeout = 10;
1021
1022 mask = SDHCI_CMD_INHIBIT;
1023 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1024 mask |= SDHCI_DATA_INHIBIT;
1025
1026 /* We shouldn't wait for data inihibit for stop commands, even
1027 though they might use busy signaling */
1028 if (host->mrq->data && (cmd == host->mrq->data->stop))
1029 mask &= ~SDHCI_DATA_INHIBIT;
1030
1031 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1032 if (timeout == 0) {
1033 pr_err("%s: Controller never released "
1034 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1035 sdhci_dumpregs(host);
1036 cmd->error = -EIO;
1037 tasklet_schedule(&host->finish_tasklet);
1038 return;
1039 }
1040 timeout--;
1041 mdelay(1);
1042 }
1043
1044 timeout = jiffies;
1045 if (!cmd->data && cmd->busy_timeout > 9000)
1046 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1047 else
1048 timeout += 10 * HZ;
1049 mod_timer(&host->timer, timeout);
1050
1051 host->cmd = cmd;
1052 host->busy_handle = 0;
1053
1054 sdhci_prepare_data(host, cmd);
1055
1056 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1057
1058 sdhci_set_transfer_mode(host, cmd);
1059
1060 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1061 pr_err("%s: Unsupported response type!\n",
1062 mmc_hostname(host->mmc));
1063 cmd->error = -EINVAL;
1064 tasklet_schedule(&host->finish_tasklet);
1065 return;
1066 }
1067
1068 if (!(cmd->flags & MMC_RSP_PRESENT))
1069 flags = SDHCI_CMD_RESP_NONE;
1070 else if (cmd->flags & MMC_RSP_136)
1071 flags = SDHCI_CMD_RESP_LONG;
1072 else if (cmd->flags & MMC_RSP_BUSY)
1073 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1074 else
1075 flags = SDHCI_CMD_RESP_SHORT;
1076
1077 if (cmd->flags & MMC_RSP_CRC)
1078 flags |= SDHCI_CMD_CRC;
1079 if (cmd->flags & MMC_RSP_OPCODE)
1080 flags |= SDHCI_CMD_INDEX;
1081
1082 /* CMD19 is special in that the Data Present Select should be set */
1083 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1084 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1085 flags |= SDHCI_CMD_DATA;
1086
1087 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1088 }
1089 EXPORT_SYMBOL_GPL(sdhci_send_command);
1090
sdhci_finish_command(struct sdhci_host * host)1091 static void sdhci_finish_command(struct sdhci_host *host)
1092 {
1093 int i;
1094
1095 BUG_ON(host->cmd == NULL);
1096
1097 if (host->cmd->flags & MMC_RSP_PRESENT) {
1098 if (host->cmd->flags & MMC_RSP_136) {
1099 /* CRC is stripped so we need to do some shifting. */
1100 for (i = 0;i < 4;i++) {
1101 host->cmd->resp[i] = sdhci_readl(host,
1102 SDHCI_RESPONSE + (3-i)*4) << 8;
1103 if (i != 3)
1104 host->cmd->resp[i] |=
1105 sdhci_readb(host,
1106 SDHCI_RESPONSE + (3-i)*4-1);
1107 }
1108 } else {
1109 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1110 }
1111 }
1112
1113 host->cmd->error = 0;
1114
1115 /* Finished CMD23, now send actual command. */
1116 if (host->cmd == host->mrq->sbc) {
1117 host->cmd = NULL;
1118 sdhci_send_command(host, host->mrq->cmd);
1119 } else {
1120
1121 /* Processed actual command. */
1122 if (host->data && host->data_early)
1123 sdhci_finish_data(host);
1124
1125 if (!host->cmd->data)
1126 tasklet_schedule(&host->finish_tasklet);
1127
1128 host->cmd = NULL;
1129 }
1130 }
1131
sdhci_get_preset_value(struct sdhci_host * host)1132 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1133 {
1134 u16 preset = 0;
1135
1136 switch (host->timing) {
1137 case MMC_TIMING_MMC_HS:
1138 case MMC_TIMING_SD_HS:
1139 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1140 break;
1141 case MMC_TIMING_UHS_SDR12:
1142 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1143 break;
1144 case MMC_TIMING_UHS_SDR25:
1145 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1146 break;
1147 case MMC_TIMING_UHS_SDR50:
1148 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1149 break;
1150 case MMC_TIMING_UHS_SDR104:
1151 case MMC_TIMING_MMC_HS200:
1152 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1153 break;
1154 case MMC_TIMING_UHS_DDR50:
1155 case MMC_TIMING_MMC_DDR52:
1156 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1157 break;
1158 case MMC_TIMING_MMC_HS400:
1159 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1160 break;
1161 default:
1162 pr_warn("%s: Invalid UHS-I mode selected\n",
1163 mmc_hostname(host->mmc));
1164 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1165 break;
1166 }
1167 return preset;
1168 }
1169
sdhci_set_clock(struct sdhci_host * host,unsigned int clock)1170 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1171 {
1172 int div = 0; /* Initialized for compiler warning */
1173 int real_div = div, clk_mul = 1;
1174 u16 clk = 0;
1175 unsigned long timeout;
1176 bool switch_base_clk = false;
1177
1178 host->mmc->actual_clock = 0;
1179
1180 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1181 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1182 mdelay(1);
1183
1184 if (clock == 0)
1185 return;
1186
1187 if (host->version >= SDHCI_SPEC_300) {
1188 if (host->preset_enabled) {
1189 u16 pre_val;
1190
1191 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1192 pre_val = sdhci_get_preset_value(host);
1193 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1194 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1195 if (host->clk_mul &&
1196 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1197 clk = SDHCI_PROG_CLOCK_MODE;
1198 real_div = div + 1;
1199 clk_mul = host->clk_mul;
1200 } else {
1201 real_div = max_t(int, 1, div << 1);
1202 }
1203 goto clock_set;
1204 }
1205
1206 /*
1207 * Check if the Host Controller supports Programmable Clock
1208 * Mode.
1209 */
1210 if (host->clk_mul) {
1211 for (div = 1; div <= 1024; div++) {
1212 if ((host->max_clk * host->clk_mul / div)
1213 <= clock)
1214 break;
1215 }
1216 if ((host->max_clk * host->clk_mul / div) <= clock) {
1217 /*
1218 * Set Programmable Clock Mode in the Clock
1219 * Control register.
1220 */
1221 clk = SDHCI_PROG_CLOCK_MODE;
1222 real_div = div;
1223 clk_mul = host->clk_mul;
1224 div--;
1225 } else {
1226 /*
1227 * Divisor can be too small to reach clock
1228 * speed requirement. Then use the base clock.
1229 */
1230 switch_base_clk = true;
1231 }
1232 }
1233
1234 if (!host->clk_mul || switch_base_clk) {
1235 /* Version 3.00 divisors must be a multiple of 2. */
1236 if (host->max_clk <= clock)
1237 div = 1;
1238 else {
1239 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1240 div += 2) {
1241 if ((host->max_clk / div) <= clock)
1242 break;
1243 }
1244 }
1245 real_div = div;
1246 div >>= 1;
1247 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1248 && !div && host->max_clk <= 25000000)
1249 div = 1;
1250 }
1251 } else {
1252 /* Version 2.00 divisors must be a power of 2. */
1253 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1254 if ((host->max_clk / div) <= clock)
1255 break;
1256 }
1257 real_div = div;
1258 div >>= 1;
1259 }
1260
1261 clock_set:
1262 if (real_div)
1263 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1264 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1265 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1266 << SDHCI_DIVIDER_HI_SHIFT;
1267 clk |= SDHCI_CLOCK_INT_EN;
1268 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1269
1270 /* Wait max 20 ms */
1271 timeout = 20;
1272 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1273 & SDHCI_CLOCK_INT_STABLE)) {
1274 if (timeout == 0) {
1275 pr_err("%s: Internal clock never "
1276 "stabilised.\n", mmc_hostname(host->mmc));
1277 sdhci_dumpregs(host);
1278 return;
1279 }
1280 timeout--;
1281 spin_unlock_irq(&host->lock);
1282 usleep_range(900, 1100);
1283 spin_lock_irq(&host->lock);
1284 }
1285
1286 clk |= SDHCI_CLOCK_CARD_EN;
1287 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1288 }
1289 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1290
sdhci_set_power_reg(struct sdhci_host * host,unsigned char mode,unsigned short vdd)1291 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1292 unsigned short vdd)
1293 {
1294 struct mmc_host *mmc = host->mmc;
1295
1296 spin_unlock_irq(&host->lock);
1297 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1298 spin_lock_irq(&host->lock);
1299
1300 if (mode != MMC_POWER_OFF)
1301 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1302 else
1303 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1304 }
1305
sdhci_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)1306 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1307 unsigned short vdd)
1308 {
1309 u8 pwr = 0;
1310
1311 if (mode != MMC_POWER_OFF) {
1312 switch (1 << vdd) {
1313 case MMC_VDD_165_195:
1314 pwr = SDHCI_POWER_180;
1315 break;
1316 case MMC_VDD_29_30:
1317 case MMC_VDD_30_31:
1318 pwr = SDHCI_POWER_300;
1319 break;
1320 case MMC_VDD_32_33:
1321 case MMC_VDD_33_34:
1322 /*
1323 * 3.4 ~ 3.6V are valid only for those platforms where it's
1324 * known that the voltage range is supported by hardware.
1325 */
1326 case MMC_VDD_34_35:
1327 case MMC_VDD_35_36:
1328 pwr = SDHCI_POWER_330;
1329 break;
1330 default:
1331 WARN(1, "%s: Invalid vdd %#x\n",
1332 mmc_hostname(host->mmc), vdd);
1333 break;
1334 }
1335 }
1336
1337 if (host->pwr == pwr)
1338 return;
1339
1340 host->pwr = pwr;
1341
1342 if (pwr == 0) {
1343 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1344 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1345 sdhci_runtime_pm_bus_off(host);
1346 } else {
1347 /*
1348 * Spec says that we should clear the power reg before setting
1349 * a new value. Some controllers don't seem to like this though.
1350 */
1351 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1352 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1353
1354 /*
1355 * At least the Marvell CaFe chip gets confused if we set the
1356 * voltage and set turn on power at the same time, so set the
1357 * voltage first.
1358 */
1359 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1360 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1361
1362 pwr |= SDHCI_POWER_ON;
1363
1364 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1365
1366 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1367 sdhci_runtime_pm_bus_on(host);
1368
1369 /*
1370 * Some controllers need an extra 10ms delay of 10ms before
1371 * they can apply clock after applying power
1372 */
1373 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1374 mdelay(10);
1375 }
1376 }
1377 EXPORT_SYMBOL_GPL(sdhci_set_power);
1378
__sdhci_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)1379 static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1380 unsigned short vdd)
1381 {
1382 struct mmc_host *mmc = host->mmc;
1383
1384 if (host->ops->set_power)
1385 host->ops->set_power(host, mode, vdd);
1386 else if (!IS_ERR(mmc->supply.vmmc))
1387 sdhci_set_power_reg(host, mode, vdd);
1388 else
1389 sdhci_set_power(host, mode, vdd);
1390 }
1391
1392 /*****************************************************************************\
1393 * *
1394 * MMC callbacks *
1395 * *
1396 \*****************************************************************************/
1397
sdhci_request(struct mmc_host * mmc,struct mmc_request * mrq)1398 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1399 {
1400 struct sdhci_host *host;
1401 int present;
1402 unsigned long flags;
1403
1404 host = mmc_priv(mmc);
1405
1406 sdhci_runtime_pm_get(host);
1407
1408 /* Firstly check card presence */
1409 present = mmc->ops->get_cd(mmc);
1410
1411 spin_lock_irqsave(&host->lock, flags);
1412
1413 WARN_ON(host->mrq != NULL);
1414
1415 #ifndef SDHCI_USE_LEDS_CLASS
1416 sdhci_activate_led(host);
1417 #endif
1418
1419 /*
1420 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1421 * requests if Auto-CMD12 is enabled.
1422 */
1423 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1424 if (mrq->stop) {
1425 mrq->data->stop = NULL;
1426 mrq->stop = NULL;
1427 }
1428 }
1429
1430 host->mrq = mrq;
1431
1432 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1433 host->mrq->cmd->error = -ENOMEDIUM;
1434 tasklet_schedule(&host->finish_tasklet);
1435 } else {
1436 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1437 sdhci_send_command(host, mrq->sbc);
1438 else
1439 sdhci_send_command(host, mrq->cmd);
1440 }
1441
1442 mmiowb();
1443 spin_unlock_irqrestore(&host->lock, flags);
1444 }
1445
sdhci_set_bus_width(struct sdhci_host * host,int width)1446 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1447 {
1448 u8 ctrl;
1449
1450 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1451 if (width == MMC_BUS_WIDTH_8) {
1452 ctrl &= ~SDHCI_CTRL_4BITBUS;
1453 if (host->version >= SDHCI_SPEC_300)
1454 ctrl |= SDHCI_CTRL_8BITBUS;
1455 } else {
1456 if (host->version >= SDHCI_SPEC_300)
1457 ctrl &= ~SDHCI_CTRL_8BITBUS;
1458 if (width == MMC_BUS_WIDTH_4)
1459 ctrl |= SDHCI_CTRL_4BITBUS;
1460 else
1461 ctrl &= ~SDHCI_CTRL_4BITBUS;
1462 }
1463 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1464 }
1465 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1466
sdhci_set_uhs_signaling(struct sdhci_host * host,unsigned timing)1467 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1468 {
1469 u16 ctrl_2;
1470
1471 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1472 /* Select Bus Speed Mode for host */
1473 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1474 if ((timing == MMC_TIMING_MMC_HS200) ||
1475 (timing == MMC_TIMING_UHS_SDR104))
1476 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1477 else if (timing == MMC_TIMING_UHS_SDR12)
1478 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1479 else if (timing == MMC_TIMING_UHS_SDR25)
1480 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1481 else if (timing == MMC_TIMING_UHS_SDR50)
1482 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1483 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1484 (timing == MMC_TIMING_MMC_DDR52))
1485 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1486 else if (timing == MMC_TIMING_MMC_HS400)
1487 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1488 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1489 }
1490 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1491
sdhci_do_set_ios(struct sdhci_host * host,struct mmc_ios * ios)1492 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1493 {
1494 unsigned long flags;
1495 u8 ctrl;
1496 struct mmc_host *mmc = host->mmc;
1497
1498 spin_lock_irqsave(&host->lock, flags);
1499
1500 if (host->flags & SDHCI_DEVICE_DEAD) {
1501 spin_unlock_irqrestore(&host->lock, flags);
1502 if (!IS_ERR(mmc->supply.vmmc) &&
1503 ios->power_mode == MMC_POWER_OFF)
1504 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1505 return;
1506 }
1507
1508 /*
1509 * Reset the chip on each power off.
1510 * Should clear out any weird states.
1511 */
1512 if (ios->power_mode == MMC_POWER_OFF) {
1513 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1514 sdhci_reinit(host);
1515 }
1516
1517 if (host->version >= SDHCI_SPEC_300 &&
1518 (ios->power_mode == MMC_POWER_UP) &&
1519 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1520 sdhci_enable_preset_value(host, false);
1521
1522 if (!ios->clock || ios->clock != host->clock) {
1523 host->ops->set_clock(host, ios->clock);
1524 host->clock = ios->clock;
1525
1526 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1527 host->clock) {
1528 host->timeout_clk = host->mmc->actual_clock ?
1529 host->mmc->actual_clock / 1000 :
1530 host->clock / 1000;
1531 host->mmc->max_busy_timeout =
1532 host->ops->get_max_timeout_count ?
1533 host->ops->get_max_timeout_count(host) :
1534 1 << 27;
1535 host->mmc->max_busy_timeout /= host->timeout_clk;
1536 }
1537 }
1538
1539 __sdhci_set_power(host, ios->power_mode, ios->vdd);
1540
1541 if (host->ops->platform_send_init_74_clocks)
1542 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1543
1544 host->ops->set_bus_width(host, ios->bus_width);
1545
1546 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1547
1548 if ((ios->timing == MMC_TIMING_SD_HS ||
1549 ios->timing == MMC_TIMING_MMC_HS)
1550 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1551 ctrl |= SDHCI_CTRL_HISPD;
1552 else
1553 ctrl &= ~SDHCI_CTRL_HISPD;
1554
1555 if (host->version >= SDHCI_SPEC_300) {
1556 u16 clk, ctrl_2;
1557
1558 /* In case of UHS-I modes, set High Speed Enable */
1559 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1560 (ios->timing == MMC_TIMING_MMC_HS200) ||
1561 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1562 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1563 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1564 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1565 (ios->timing == MMC_TIMING_UHS_SDR25))
1566 ctrl |= SDHCI_CTRL_HISPD;
1567
1568 if (!host->preset_enabled) {
1569 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1570 /*
1571 * We only need to set Driver Strength if the
1572 * preset value enable is not set.
1573 */
1574 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1575 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1576 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1577 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1578 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1579 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1580 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1581 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1582 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1583 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1584 else {
1585 pr_warn("%s: invalid driver type, default to "
1586 "driver type B\n", mmc_hostname(mmc));
1587 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1588 }
1589
1590 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1591 } else {
1592 /*
1593 * According to SDHC Spec v3.00, if the Preset Value
1594 * Enable in the Host Control 2 register is set, we
1595 * need to reset SD Clock Enable before changing High
1596 * Speed Enable to avoid generating clock gliches.
1597 */
1598
1599 /* Reset SD Clock Enable */
1600 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1601 clk &= ~SDHCI_CLOCK_CARD_EN;
1602 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1603
1604 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1605
1606 /* Re-enable SD Clock */
1607 host->ops->set_clock(host, host->clock);
1608 }
1609
1610 /* Reset SD Clock Enable */
1611 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1612 clk &= ~SDHCI_CLOCK_CARD_EN;
1613 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1614
1615 host->ops->set_uhs_signaling(host, ios->timing);
1616 host->timing = ios->timing;
1617
1618 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1619 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1620 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1621 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1622 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1623 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1624 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1625 u16 preset;
1626
1627 sdhci_enable_preset_value(host, true);
1628 preset = sdhci_get_preset_value(host);
1629 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1630 >> SDHCI_PRESET_DRV_SHIFT;
1631 }
1632
1633 /* Re-enable SD Clock */
1634 host->ops->set_clock(host, host->clock);
1635 } else
1636 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1637
1638 /*
1639 * Some (ENE) controllers go apeshit on some ios operation,
1640 * signalling timeout and CRC errors even on CMD0. Resetting
1641 * it on each ios seems to solve the problem.
1642 */
1643 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1644 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1645
1646 mmiowb();
1647 spin_unlock_irqrestore(&host->lock, flags);
1648 }
1649
sdhci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1650 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1651 {
1652 struct sdhci_host *host = mmc_priv(mmc);
1653
1654 sdhci_runtime_pm_get(host);
1655 sdhci_do_set_ios(host, ios);
1656 sdhci_runtime_pm_put(host);
1657 }
1658
sdhci_do_get_cd(struct sdhci_host * host)1659 static int sdhci_do_get_cd(struct sdhci_host *host)
1660 {
1661 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1662
1663 if (host->flags & SDHCI_DEVICE_DEAD)
1664 return 0;
1665
1666 /* If nonremovable, assume that the card is always present. */
1667 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1668 return 1;
1669
1670 /*
1671 * Try slot gpio detect, if defined it take precedence
1672 * over build in controller functionality
1673 */
1674 if (!IS_ERR_VALUE(gpio_cd))
1675 return !!gpio_cd;
1676
1677 /* If polling, assume that the card is always present. */
1678 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1679 return 1;
1680
1681 /* Host native card detect */
1682 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1683 }
1684
sdhci_get_cd(struct mmc_host * mmc)1685 static int sdhci_get_cd(struct mmc_host *mmc)
1686 {
1687 struct sdhci_host *host = mmc_priv(mmc);
1688 int ret;
1689
1690 sdhci_runtime_pm_get(host);
1691 ret = sdhci_do_get_cd(host);
1692 sdhci_runtime_pm_put(host);
1693 return ret;
1694 }
1695
sdhci_check_ro(struct sdhci_host * host)1696 static int sdhci_check_ro(struct sdhci_host *host)
1697 {
1698 unsigned long flags;
1699 int is_readonly;
1700
1701 spin_lock_irqsave(&host->lock, flags);
1702
1703 if (host->flags & SDHCI_DEVICE_DEAD)
1704 is_readonly = 0;
1705 else if (host->ops->get_ro)
1706 is_readonly = host->ops->get_ro(host);
1707 else
1708 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1709 & SDHCI_WRITE_PROTECT);
1710
1711 spin_unlock_irqrestore(&host->lock, flags);
1712
1713 /* This quirk needs to be replaced by a callback-function later */
1714 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1715 !is_readonly : is_readonly;
1716 }
1717
1718 #define SAMPLE_COUNT 5
1719
sdhci_do_get_ro(struct sdhci_host * host)1720 static int sdhci_do_get_ro(struct sdhci_host *host)
1721 {
1722 int i, ro_count;
1723
1724 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1725 return sdhci_check_ro(host);
1726
1727 ro_count = 0;
1728 for (i = 0; i < SAMPLE_COUNT; i++) {
1729 if (sdhci_check_ro(host)) {
1730 if (++ro_count > SAMPLE_COUNT / 2)
1731 return 1;
1732 }
1733 msleep(30);
1734 }
1735 return 0;
1736 }
1737
sdhci_hw_reset(struct mmc_host * mmc)1738 static void sdhci_hw_reset(struct mmc_host *mmc)
1739 {
1740 struct sdhci_host *host = mmc_priv(mmc);
1741
1742 if (host->ops && host->ops->hw_reset)
1743 host->ops->hw_reset(host);
1744 }
1745
sdhci_get_ro(struct mmc_host * mmc)1746 static int sdhci_get_ro(struct mmc_host *mmc)
1747 {
1748 struct sdhci_host *host = mmc_priv(mmc);
1749 int ret;
1750
1751 sdhci_runtime_pm_get(host);
1752 ret = sdhci_do_get_ro(host);
1753 sdhci_runtime_pm_put(host);
1754 return ret;
1755 }
1756
sdhci_enable_sdio_irq_nolock(struct sdhci_host * host,int enable)1757 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1758 {
1759 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1760 if (enable)
1761 host->ier |= SDHCI_INT_CARD_INT;
1762 else
1763 host->ier &= ~SDHCI_INT_CARD_INT;
1764
1765 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1766 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1767 mmiowb();
1768 }
1769 }
1770
sdhci_enable_sdio_irq(struct mmc_host * mmc,int enable)1771 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1772 {
1773 struct sdhci_host *host = mmc_priv(mmc);
1774 unsigned long flags;
1775
1776 sdhci_runtime_pm_get(host);
1777
1778 spin_lock_irqsave(&host->lock, flags);
1779 if (enable)
1780 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1781 else
1782 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1783
1784 sdhci_enable_sdio_irq_nolock(host, enable);
1785 spin_unlock_irqrestore(&host->lock, flags);
1786
1787 sdhci_runtime_pm_put(host);
1788 }
1789
sdhci_do_start_signal_voltage_switch(struct sdhci_host * host,struct mmc_ios * ios)1790 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1791 struct mmc_ios *ios)
1792 {
1793 struct mmc_host *mmc = host->mmc;
1794 u16 ctrl;
1795 int ret;
1796
1797 /*
1798 * Signal Voltage Switching is only applicable for Host Controllers
1799 * v3.00 and above.
1800 */
1801 if (host->version < SDHCI_SPEC_300)
1802 return 0;
1803
1804 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1805
1806 switch (ios->signal_voltage) {
1807 case MMC_SIGNAL_VOLTAGE_330:
1808 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1809 ctrl &= ~SDHCI_CTRL_VDD_180;
1810 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1811
1812 if (!IS_ERR(mmc->supply.vqmmc)) {
1813 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1814 3600000);
1815 if (ret) {
1816 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1817 mmc_hostname(mmc));
1818 return -EIO;
1819 }
1820 }
1821 /* Wait for 5ms */
1822 usleep_range(5000, 5500);
1823
1824 /* 3.3V regulator output should be stable within 5 ms */
1825 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1826 if (!(ctrl & SDHCI_CTRL_VDD_180))
1827 return 0;
1828
1829 pr_warn("%s: 3.3V regulator output did not became stable\n",
1830 mmc_hostname(mmc));
1831
1832 return -EAGAIN;
1833 case MMC_SIGNAL_VOLTAGE_180:
1834 if (!IS_ERR(mmc->supply.vqmmc)) {
1835 ret = regulator_set_voltage(mmc->supply.vqmmc,
1836 1700000, 1950000);
1837 if (ret) {
1838 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1839 mmc_hostname(mmc));
1840 return -EIO;
1841 }
1842 }
1843
1844 /*
1845 * Enable 1.8V Signal Enable in the Host Control2
1846 * register
1847 */
1848 ctrl |= SDHCI_CTRL_VDD_180;
1849 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1850
1851 /* Some controller need to do more when switching */
1852 if (host->ops->voltage_switch)
1853 host->ops->voltage_switch(host);
1854
1855 /* 1.8V regulator output should be stable within 5 ms */
1856 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1857 if (ctrl & SDHCI_CTRL_VDD_180)
1858 return 0;
1859
1860 pr_warn("%s: 1.8V regulator output did not became stable\n",
1861 mmc_hostname(mmc));
1862
1863 return -EAGAIN;
1864 case MMC_SIGNAL_VOLTAGE_120:
1865 if (!IS_ERR(mmc->supply.vqmmc)) {
1866 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1867 1300000);
1868 if (ret) {
1869 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1870 mmc_hostname(mmc));
1871 return -EIO;
1872 }
1873 }
1874 return 0;
1875 default:
1876 /* No signal voltage switch required */
1877 return 0;
1878 }
1879 }
1880
sdhci_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)1881 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1882 struct mmc_ios *ios)
1883 {
1884 struct sdhci_host *host = mmc_priv(mmc);
1885 int err;
1886
1887 if (host->version < SDHCI_SPEC_300)
1888 return 0;
1889 sdhci_runtime_pm_get(host);
1890 err = sdhci_do_start_signal_voltage_switch(host, ios);
1891 sdhci_runtime_pm_put(host);
1892 return err;
1893 }
1894
sdhci_card_busy(struct mmc_host * mmc)1895 static int sdhci_card_busy(struct mmc_host *mmc)
1896 {
1897 struct sdhci_host *host = mmc_priv(mmc);
1898 u32 present_state;
1899
1900 sdhci_runtime_pm_get(host);
1901 /* Check whether DAT[3:0] is 0000 */
1902 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1903 sdhci_runtime_pm_put(host);
1904
1905 return !(present_state & SDHCI_DATA_LVL_MASK);
1906 }
1907
sdhci_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)1908 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1909 {
1910 struct sdhci_host *host = mmc_priv(mmc);
1911 unsigned long flags;
1912
1913 spin_lock_irqsave(&host->lock, flags);
1914 host->flags |= SDHCI_HS400_TUNING;
1915 spin_unlock_irqrestore(&host->lock, flags);
1916
1917 return 0;
1918 }
1919
sdhci_execute_tuning(struct mmc_host * mmc,u32 opcode)1920 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1921 {
1922 struct sdhci_host *host = mmc_priv(mmc);
1923 u16 ctrl;
1924 int tuning_loop_counter = MAX_TUNING_LOOP;
1925 int err = 0;
1926 unsigned long flags;
1927 unsigned int tuning_count = 0;
1928 bool hs400_tuning;
1929
1930 sdhci_runtime_pm_get(host);
1931 spin_lock_irqsave(&host->lock, flags);
1932
1933 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1934 host->flags &= ~SDHCI_HS400_TUNING;
1935
1936 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1937 tuning_count = host->tuning_count;
1938
1939 /*
1940 * The Host Controller needs tuning in case of SDR104 and DDR50
1941 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1942 * the Capabilities register.
1943 * If the Host Controller supports the HS200 mode then the
1944 * tuning function has to be executed.
1945 */
1946 switch (host->timing) {
1947 /* HS400 tuning is done in HS200 mode */
1948 case MMC_TIMING_MMC_HS400:
1949 err = -EINVAL;
1950 goto out_unlock;
1951
1952 case MMC_TIMING_MMC_HS200:
1953 /*
1954 * Periodic re-tuning for HS400 is not expected to be needed, so
1955 * disable it here.
1956 */
1957 if (hs400_tuning)
1958 tuning_count = 0;
1959 break;
1960
1961 case MMC_TIMING_UHS_SDR104:
1962 case MMC_TIMING_UHS_DDR50:
1963 break;
1964
1965 case MMC_TIMING_UHS_SDR50:
1966 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1967 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1968 break;
1969 /* FALLTHROUGH */
1970
1971 default:
1972 goto out_unlock;
1973 }
1974
1975 if (host->ops->platform_execute_tuning) {
1976 spin_unlock_irqrestore(&host->lock, flags);
1977 err = host->ops->platform_execute_tuning(host, opcode);
1978 sdhci_runtime_pm_put(host);
1979 return err;
1980 }
1981
1982 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1983 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1984 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1985 ctrl |= SDHCI_CTRL_TUNED_CLK;
1986 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1987
1988 /*
1989 * As per the Host Controller spec v3.00, tuning command
1990 * generates Buffer Read Ready interrupt, so enable that.
1991 *
1992 * Note: The spec clearly says that when tuning sequence
1993 * is being performed, the controller does not generate
1994 * interrupts other than Buffer Read Ready interrupt. But
1995 * to make sure we don't hit a controller bug, we _only_
1996 * enable Buffer Read Ready interrupt here.
1997 */
1998 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1999 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2000
2001 /*
2002 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
2003 * of loops reaches 40 times or a timeout of 150ms occurs.
2004 */
2005 do {
2006 struct mmc_command cmd = {0};
2007 struct mmc_request mrq = {NULL};
2008
2009 cmd.opcode = opcode;
2010 cmd.arg = 0;
2011 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2012 cmd.retries = 0;
2013 cmd.data = NULL;
2014 cmd.error = 0;
2015
2016 if (tuning_loop_counter-- == 0)
2017 break;
2018
2019 mrq.cmd = &cmd;
2020 host->mrq = &mrq;
2021
2022 /*
2023 * In response to CMD19, the card sends 64 bytes of tuning
2024 * block to the Host Controller. So we set the block size
2025 * to 64 here.
2026 */
2027 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2028 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2029 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2030 SDHCI_BLOCK_SIZE);
2031 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2032 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2033 SDHCI_BLOCK_SIZE);
2034 } else {
2035 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2036 SDHCI_BLOCK_SIZE);
2037 }
2038
2039 /*
2040 * The tuning block is sent by the card to the host controller.
2041 * So we set the TRNS_READ bit in the Transfer Mode register.
2042 * This also takes care of setting DMA Enable and Multi Block
2043 * Select in the same register to 0.
2044 */
2045 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2046
2047 sdhci_send_command(host, &cmd);
2048
2049 host->cmd = NULL;
2050 host->mrq = NULL;
2051
2052 spin_unlock_irqrestore(&host->lock, flags);
2053 /* Wait for Buffer Read Ready interrupt */
2054 wait_event_interruptible_timeout(host->buf_ready_int,
2055 (host->tuning_done == 1),
2056 msecs_to_jiffies(50));
2057 spin_lock_irqsave(&host->lock, flags);
2058
2059 if (!host->tuning_done) {
2060 pr_debug(DRIVER_NAME ": Timeout waiting for "
2061 "Buffer Read Ready interrupt during tuning "
2062 "procedure, falling back to fixed sampling "
2063 "clock\n");
2064 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2065 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2066 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2067 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2068
2069 sdhci_do_reset(host, SDHCI_RESET_CMD);
2070 sdhci_do_reset(host, SDHCI_RESET_DATA);
2071
2072 err = -EIO;
2073
2074 if (cmd.opcode != MMC_SEND_TUNING_BLOCK_HS200)
2075 goto out;
2076
2077 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2078 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2079
2080 spin_unlock_irqrestore(&host->lock, flags);
2081
2082 memset(&cmd, 0, sizeof(cmd));
2083 cmd.opcode = MMC_STOP_TRANSMISSION;
2084 cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
2085 cmd.busy_timeout = 50;
2086 mmc_wait_for_cmd(mmc, &cmd, 0);
2087
2088 spin_lock_irqsave(&host->lock, flags);
2089
2090 goto out;
2091 }
2092
2093 host->tuning_done = 0;
2094
2095 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2096
2097 /* eMMC spec does not require a delay between tuning cycles */
2098 if (opcode == MMC_SEND_TUNING_BLOCK)
2099 mdelay(1);
2100 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2101
2102 /*
2103 * The Host Driver has exhausted the maximum number of loops allowed,
2104 * so use fixed sampling frequency.
2105 */
2106 if (tuning_loop_counter < 0) {
2107 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2108 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2109 }
2110 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2111 pr_info(DRIVER_NAME ": Tuning procedure"
2112 " failed, falling back to fixed sampling"
2113 " clock\n");
2114 err = -EIO;
2115 }
2116
2117 out:
2118 if (tuning_count) {
2119 /*
2120 * In case tuning fails, host controllers which support
2121 * re-tuning can try tuning again at a later time, when the
2122 * re-tuning timer expires. So for these controllers, we
2123 * return 0. Since there might be other controllers who do not
2124 * have this capability, we return error for them.
2125 */
2126 err = 0;
2127 }
2128
2129 host->mmc->retune_period = err ? 0 : tuning_count;
2130
2131 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2132 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2133 out_unlock:
2134 spin_unlock_irqrestore(&host->lock, flags);
2135 sdhci_runtime_pm_put(host);
2136
2137 return err;
2138 }
2139
sdhci_select_drive_strength(struct mmc_card * card,unsigned int max_dtr,int host_drv,int card_drv,int * drv_type)2140 static int sdhci_select_drive_strength(struct mmc_card *card,
2141 unsigned int max_dtr, int host_drv,
2142 int card_drv, int *drv_type)
2143 {
2144 struct sdhci_host *host = mmc_priv(card->host);
2145
2146 if (!host->ops->select_drive_strength)
2147 return 0;
2148
2149 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2150 card_drv, drv_type);
2151 }
2152
sdhci_enable_preset_value(struct sdhci_host * host,bool enable)2153 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2154 {
2155 /* Host Controller v3.00 defines preset value registers */
2156 if (host->version < SDHCI_SPEC_300)
2157 return;
2158
2159 /*
2160 * We only enable or disable Preset Value if they are not already
2161 * enabled or disabled respectively. Otherwise, we bail out.
2162 */
2163 if (host->preset_enabled != enable) {
2164 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2165
2166 if (enable)
2167 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2168 else
2169 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2170
2171 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2172
2173 if (enable)
2174 host->flags |= SDHCI_PV_ENABLED;
2175 else
2176 host->flags &= ~SDHCI_PV_ENABLED;
2177
2178 host->preset_enabled = enable;
2179 }
2180 }
2181
sdhci_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)2182 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2183 int err)
2184 {
2185 struct sdhci_host *host = mmc_priv(mmc);
2186 struct mmc_data *data = mrq->data;
2187
2188 if (host->flags & SDHCI_REQ_USE_DMA) {
2189 if (data->host_cookie == COOKIE_GIVEN ||
2190 data->host_cookie == COOKIE_MAPPED)
2191 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2192 data->flags & MMC_DATA_WRITE ?
2193 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2194 data->host_cookie = COOKIE_UNMAPPED;
2195 }
2196 }
2197
sdhci_pre_dma_transfer(struct sdhci_host * host,struct mmc_data * data)2198 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2199 struct mmc_data *data)
2200 {
2201 int sg_count;
2202
2203 if (data->host_cookie == COOKIE_MAPPED) {
2204 data->host_cookie = COOKIE_GIVEN;
2205 return data->sg_count;
2206 }
2207
2208 WARN_ON(data->host_cookie == COOKIE_GIVEN);
2209
2210 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2211 data->flags & MMC_DATA_WRITE ?
2212 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2213
2214 if (sg_count == 0)
2215 return -ENOSPC;
2216
2217 data->sg_count = sg_count;
2218 data->host_cookie = COOKIE_MAPPED;
2219
2220 return sg_count;
2221 }
2222
sdhci_pre_req(struct mmc_host * mmc,struct mmc_request * mrq,bool is_first_req)2223 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2224 bool is_first_req)
2225 {
2226 struct sdhci_host *host = mmc_priv(mmc);
2227
2228 mrq->data->host_cookie = COOKIE_UNMAPPED;
2229
2230 if (host->flags & SDHCI_REQ_USE_DMA)
2231 sdhci_pre_dma_transfer(host, mrq->data);
2232 }
2233
sdhci_card_event(struct mmc_host * mmc)2234 static void sdhci_card_event(struct mmc_host *mmc)
2235 {
2236 struct sdhci_host *host = mmc_priv(mmc);
2237 unsigned long flags;
2238 int present;
2239
2240 /* First check if client has provided their own card event */
2241 if (host->ops->card_event)
2242 host->ops->card_event(host);
2243
2244 present = sdhci_do_get_cd(host);
2245
2246 spin_lock_irqsave(&host->lock, flags);
2247
2248 /* Check host->mrq first in case we are runtime suspended */
2249 if (host->mrq && !present) {
2250 pr_err("%s: Card removed during transfer!\n",
2251 mmc_hostname(host->mmc));
2252 pr_err("%s: Resetting controller.\n",
2253 mmc_hostname(host->mmc));
2254
2255 sdhci_do_reset(host, SDHCI_RESET_CMD);
2256 sdhci_do_reset(host, SDHCI_RESET_DATA);
2257
2258 host->mrq->cmd->error = -ENOMEDIUM;
2259 tasklet_schedule(&host->finish_tasklet);
2260 }
2261
2262 spin_unlock_irqrestore(&host->lock, flags);
2263 }
2264
2265 static const struct mmc_host_ops sdhci_ops = {
2266 .request = sdhci_request,
2267 .post_req = sdhci_post_req,
2268 .pre_req = sdhci_pre_req,
2269 .set_ios = sdhci_set_ios,
2270 .get_cd = sdhci_get_cd,
2271 .get_ro = sdhci_get_ro,
2272 .hw_reset = sdhci_hw_reset,
2273 .enable_sdio_irq = sdhci_enable_sdio_irq,
2274 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2275 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2276 .execute_tuning = sdhci_execute_tuning,
2277 .select_drive_strength = sdhci_select_drive_strength,
2278 .card_event = sdhci_card_event,
2279 .card_busy = sdhci_card_busy,
2280 };
2281
2282 /*****************************************************************************\
2283 * *
2284 * Tasklets *
2285 * *
2286 \*****************************************************************************/
2287
sdhci_tasklet_finish(unsigned long param)2288 static void sdhci_tasklet_finish(unsigned long param)
2289 {
2290 struct sdhci_host *host;
2291 unsigned long flags;
2292 struct mmc_request *mrq;
2293
2294 host = (struct sdhci_host*)param;
2295
2296 spin_lock_irqsave(&host->lock, flags);
2297
2298 /*
2299 * If this tasklet gets rescheduled while running, it will
2300 * be run again afterwards but without any active request.
2301 */
2302 if (!host->mrq) {
2303 spin_unlock_irqrestore(&host->lock, flags);
2304 return;
2305 }
2306
2307 del_timer(&host->timer);
2308
2309 mrq = host->mrq;
2310
2311 /*
2312 * The controller needs a reset of internal state machines
2313 * upon error conditions.
2314 */
2315 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2316 ((mrq->cmd && mrq->cmd->error) ||
2317 (mrq->sbc && mrq->sbc->error) ||
2318 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2319 (mrq->data->stop && mrq->data->stop->error))) ||
2320 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2321
2322 /* Some controllers need this kick or reset won't work here */
2323 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2324 /* This is to force an update */
2325 host->ops->set_clock(host, host->clock);
2326
2327 /* Spec says we should do both at the same time, but Ricoh
2328 controllers do not like that. */
2329 sdhci_do_reset(host, SDHCI_RESET_CMD);
2330 sdhci_do_reset(host, SDHCI_RESET_DATA);
2331 }
2332
2333 host->mrq = NULL;
2334 host->cmd = NULL;
2335 host->data = NULL;
2336
2337 #ifndef SDHCI_USE_LEDS_CLASS
2338 sdhci_deactivate_led(host);
2339 #endif
2340
2341 mmiowb();
2342 spin_unlock_irqrestore(&host->lock, flags);
2343
2344 mmc_request_done(host->mmc, mrq);
2345 sdhci_runtime_pm_put(host);
2346 }
2347
sdhci_timeout_timer(unsigned long data)2348 static void sdhci_timeout_timer(unsigned long data)
2349 {
2350 struct sdhci_host *host;
2351 unsigned long flags;
2352
2353 host = (struct sdhci_host*)data;
2354
2355 spin_lock_irqsave(&host->lock, flags);
2356
2357 if (host->mrq) {
2358 pr_err("%s: Timeout waiting for hardware "
2359 "interrupt.\n", mmc_hostname(host->mmc));
2360 sdhci_dumpregs(host);
2361
2362 if (host->data) {
2363 host->data->error = -ETIMEDOUT;
2364 sdhci_finish_data(host);
2365 } else {
2366 if (host->cmd)
2367 host->cmd->error = -ETIMEDOUT;
2368 else
2369 host->mrq->cmd->error = -ETIMEDOUT;
2370
2371 tasklet_schedule(&host->finish_tasklet);
2372 }
2373 }
2374
2375 mmiowb();
2376 spin_unlock_irqrestore(&host->lock, flags);
2377 }
2378
2379 /*****************************************************************************\
2380 * *
2381 * Interrupt handling *
2382 * *
2383 \*****************************************************************************/
2384
sdhci_cmd_irq(struct sdhci_host * host,u32 intmask,u32 * mask)2385 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2386 {
2387 BUG_ON(intmask == 0);
2388
2389 if (!host->cmd) {
2390 pr_err("%s: Got command interrupt 0x%08x even "
2391 "though no command operation was in progress.\n",
2392 mmc_hostname(host->mmc), (unsigned)intmask);
2393 sdhci_dumpregs(host);
2394 return;
2395 }
2396
2397 if (intmask & SDHCI_INT_TIMEOUT)
2398 host->cmd->error = -ETIMEDOUT;
2399 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2400 SDHCI_INT_INDEX))
2401 host->cmd->error = -EILSEQ;
2402
2403 if (host->cmd->error) {
2404 tasklet_schedule(&host->finish_tasklet);
2405 return;
2406 }
2407
2408 /*
2409 * The host can send and interrupt when the busy state has
2410 * ended, allowing us to wait without wasting CPU cycles.
2411 * Unfortunately this is overloaded on the "data complete"
2412 * interrupt, so we need to take some care when handling
2413 * it.
2414 *
2415 * Note: The 1.0 specification is a bit ambiguous about this
2416 * feature so there might be some problems with older
2417 * controllers.
2418 */
2419 if (host->cmd->flags & MMC_RSP_BUSY) {
2420 if (host->cmd->data)
2421 DBG("Cannot wait for busy signal when also "
2422 "doing a data transfer");
2423 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2424 && !host->busy_handle) {
2425 /* Mark that command complete before busy is ended */
2426 host->busy_handle = 1;
2427 return;
2428 }
2429
2430 /* The controller does not support the end-of-busy IRQ,
2431 * fall through and take the SDHCI_INT_RESPONSE */
2432 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2433 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2434 *mask &= ~SDHCI_INT_DATA_END;
2435 }
2436
2437 if (intmask & SDHCI_INT_RESPONSE)
2438 sdhci_finish_command(host);
2439 }
2440
2441 #ifdef CONFIG_MMC_DEBUG
sdhci_adma_show_error(struct sdhci_host * host)2442 static void sdhci_adma_show_error(struct sdhci_host *host)
2443 {
2444 const char *name = mmc_hostname(host->mmc);
2445 void *desc = host->adma_table;
2446
2447 sdhci_dumpregs(host);
2448
2449 while (true) {
2450 struct sdhci_adma2_64_desc *dma_desc = desc;
2451
2452 if (host->flags & SDHCI_USE_64_BIT_DMA)
2453 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2454 name, desc, le32_to_cpu(dma_desc->addr_hi),
2455 le32_to_cpu(dma_desc->addr_lo),
2456 le16_to_cpu(dma_desc->len),
2457 le16_to_cpu(dma_desc->cmd));
2458 else
2459 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2460 name, desc, le32_to_cpu(dma_desc->addr_lo),
2461 le16_to_cpu(dma_desc->len),
2462 le16_to_cpu(dma_desc->cmd));
2463
2464 desc += host->desc_sz;
2465
2466 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2467 break;
2468 }
2469 }
2470 #else
sdhci_adma_show_error(struct sdhci_host * host)2471 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2472 #endif
2473
sdhci_data_irq(struct sdhci_host * host,u32 intmask)2474 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2475 {
2476 u32 command;
2477 BUG_ON(intmask == 0);
2478
2479 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2480 if (intmask & SDHCI_INT_DATA_AVAIL) {
2481 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2482 if (command == MMC_SEND_TUNING_BLOCK ||
2483 command == MMC_SEND_TUNING_BLOCK_HS200) {
2484 host->tuning_done = 1;
2485 wake_up(&host->buf_ready_int);
2486 return;
2487 }
2488 }
2489
2490 if (!host->data) {
2491 /*
2492 * The "data complete" interrupt is also used to
2493 * indicate that a busy state has ended. See comment
2494 * above in sdhci_cmd_irq().
2495 */
2496 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2497 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2498 host->cmd->error = -ETIMEDOUT;
2499 tasklet_schedule(&host->finish_tasklet);
2500 return;
2501 }
2502 if (intmask & SDHCI_INT_DATA_END) {
2503 /*
2504 * Some cards handle busy-end interrupt
2505 * before the command completed, so make
2506 * sure we do things in the proper order.
2507 */
2508 if (host->busy_handle)
2509 sdhci_finish_command(host);
2510 else
2511 host->busy_handle = 1;
2512 return;
2513 }
2514 }
2515
2516 pr_err("%s: Got data interrupt 0x%08x even "
2517 "though no data operation was in progress.\n",
2518 mmc_hostname(host->mmc), (unsigned)intmask);
2519 sdhci_dumpregs(host);
2520
2521 return;
2522 }
2523
2524 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2525 host->data->error = -ETIMEDOUT;
2526 else if (intmask & SDHCI_INT_DATA_END_BIT)
2527 host->data->error = -EILSEQ;
2528 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2529 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2530 != MMC_BUS_TEST_R)
2531 host->data->error = -EILSEQ;
2532 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2533 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2534 sdhci_adma_show_error(host);
2535 host->data->error = -EIO;
2536 if (host->ops->adma_workaround)
2537 host->ops->adma_workaround(host, intmask);
2538 }
2539
2540 if (host->data->error)
2541 sdhci_finish_data(host);
2542 else {
2543 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2544 sdhci_transfer_pio(host);
2545
2546 /*
2547 * We currently don't do anything fancy with DMA
2548 * boundaries, but as we can't disable the feature
2549 * we need to at least restart the transfer.
2550 *
2551 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2552 * should return a valid address to continue from, but as
2553 * some controllers are faulty, don't trust them.
2554 */
2555 if (intmask & SDHCI_INT_DMA_END) {
2556 u32 dmastart, dmanow;
2557 dmastart = sg_dma_address(host->data->sg);
2558 dmanow = dmastart + host->data->bytes_xfered;
2559 /*
2560 * Force update to the next DMA block boundary.
2561 */
2562 dmanow = (dmanow &
2563 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2564 SDHCI_DEFAULT_BOUNDARY_SIZE;
2565 host->data->bytes_xfered = dmanow - dmastart;
2566 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2567 " next 0x%08x\n",
2568 mmc_hostname(host->mmc), dmastart,
2569 host->data->bytes_xfered, dmanow);
2570 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2571 }
2572
2573 if (intmask & SDHCI_INT_DATA_END) {
2574 if (host->cmd) {
2575 /*
2576 * Data managed to finish before the
2577 * command completed. Make sure we do
2578 * things in the proper order.
2579 */
2580 host->data_early = 1;
2581 } else {
2582 sdhci_finish_data(host);
2583 }
2584 }
2585 }
2586 }
2587
sdhci_irq(int irq,void * dev_id)2588 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2589 {
2590 irqreturn_t result = IRQ_NONE;
2591 struct sdhci_host *host = dev_id;
2592 u32 intmask, mask, unexpected = 0;
2593 int max_loops = 16;
2594
2595 spin_lock(&host->lock);
2596
2597 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2598 spin_unlock(&host->lock);
2599 return IRQ_NONE;
2600 }
2601
2602 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2603 if (!intmask || intmask == 0xffffffff) {
2604 result = IRQ_NONE;
2605 goto out;
2606 }
2607
2608 do {
2609 /* Clear selected interrupts. */
2610 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2611 SDHCI_INT_BUS_POWER);
2612 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2613
2614 DBG("*** %s got interrupt: 0x%08x\n",
2615 mmc_hostname(host->mmc), intmask);
2616
2617 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2618 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2619 SDHCI_CARD_PRESENT;
2620
2621 /*
2622 * There is a observation on i.mx esdhc. INSERT
2623 * bit will be immediately set again when it gets
2624 * cleared, if a card is inserted. We have to mask
2625 * the irq to prevent interrupt storm which will
2626 * freeze the system. And the REMOVE gets the
2627 * same situation.
2628 *
2629 * More testing are needed here to ensure it works
2630 * for other platforms though.
2631 */
2632 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2633 SDHCI_INT_CARD_REMOVE);
2634 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2635 SDHCI_INT_CARD_INSERT;
2636 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2637 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2638
2639 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2640 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2641
2642 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2643 SDHCI_INT_CARD_REMOVE);
2644 result = IRQ_WAKE_THREAD;
2645 }
2646
2647 if (intmask & SDHCI_INT_CMD_MASK)
2648 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2649 &intmask);
2650
2651 if (intmask & SDHCI_INT_DATA_MASK)
2652 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2653
2654 if (intmask & SDHCI_INT_BUS_POWER)
2655 pr_err("%s: Card is consuming too much power!\n",
2656 mmc_hostname(host->mmc));
2657
2658 if ((intmask & SDHCI_INT_CARD_INT) &&
2659 (host->ier & SDHCI_INT_CARD_INT)) {
2660 sdhci_enable_sdio_irq_nolock(host, false);
2661 host->thread_isr |= SDHCI_INT_CARD_INT;
2662 result = IRQ_WAKE_THREAD;
2663 }
2664
2665 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2666 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2667 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2668 SDHCI_INT_CARD_INT);
2669
2670 if (intmask) {
2671 unexpected |= intmask;
2672 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2673 }
2674
2675 if (result == IRQ_NONE)
2676 result = IRQ_HANDLED;
2677
2678 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2679 } while (intmask && --max_loops);
2680 out:
2681 spin_unlock(&host->lock);
2682
2683 if (unexpected) {
2684 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2685 mmc_hostname(host->mmc), unexpected);
2686 sdhci_dumpregs(host);
2687 }
2688
2689 return result;
2690 }
2691
sdhci_thread_irq(int irq,void * dev_id)2692 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2693 {
2694 struct sdhci_host *host = dev_id;
2695 unsigned long flags;
2696 u32 isr;
2697
2698 spin_lock_irqsave(&host->lock, flags);
2699 isr = host->thread_isr;
2700 host->thread_isr = 0;
2701 spin_unlock_irqrestore(&host->lock, flags);
2702
2703 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2704 sdhci_card_event(host->mmc);
2705 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2706 }
2707
2708 if (isr & SDHCI_INT_CARD_INT) {
2709 sdio_run_irqs(host->mmc);
2710
2711 spin_lock_irqsave(&host->lock, flags);
2712 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2713 sdhci_enable_sdio_irq_nolock(host, true);
2714 spin_unlock_irqrestore(&host->lock, flags);
2715 }
2716
2717 return isr ? IRQ_HANDLED : IRQ_NONE;
2718 }
2719
2720 /*****************************************************************************\
2721 * *
2722 * Suspend/resume *
2723 * *
2724 \*****************************************************************************/
2725
2726 #ifdef CONFIG_PM
sdhci_enable_irq_wakeups(struct sdhci_host * host)2727 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2728 {
2729 u8 val;
2730 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2731 | SDHCI_WAKE_ON_INT;
2732
2733 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2734 val |= mask ;
2735 /* Avoid fake wake up */
2736 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2737 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2738 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2739 }
2740 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2741
sdhci_disable_irq_wakeups(struct sdhci_host * host)2742 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2743 {
2744 u8 val;
2745 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2746 | SDHCI_WAKE_ON_INT;
2747
2748 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2749 val &= ~mask;
2750 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2751 }
2752
sdhci_suspend_host(struct sdhci_host * host)2753 int sdhci_suspend_host(struct sdhci_host *host)
2754 {
2755 sdhci_disable_card_detection(host);
2756
2757 mmc_retune_timer_stop(host->mmc);
2758 mmc_retune_needed(host->mmc);
2759
2760 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2761 host->ier = 0;
2762 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2763 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2764 free_irq(host->irq, host);
2765 } else {
2766 sdhci_enable_irq_wakeups(host);
2767 enable_irq_wake(host->irq);
2768 }
2769 return 0;
2770 }
2771
2772 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2773
sdhci_resume_host(struct sdhci_host * host)2774 int sdhci_resume_host(struct sdhci_host *host)
2775 {
2776 int ret = 0;
2777
2778 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2779 if (host->ops->enable_dma)
2780 host->ops->enable_dma(host);
2781 }
2782
2783 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2784 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2785 /* Card keeps power but host controller does not */
2786 sdhci_init(host, 0);
2787 host->pwr = 0;
2788 host->clock = 0;
2789 sdhci_do_set_ios(host, &host->mmc->ios);
2790 } else {
2791 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2792 mmiowb();
2793 }
2794
2795 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2796 ret = request_threaded_irq(host->irq, sdhci_irq,
2797 sdhci_thread_irq, IRQF_SHARED,
2798 mmc_hostname(host->mmc), host);
2799 if (ret)
2800 return ret;
2801 } else {
2802 sdhci_disable_irq_wakeups(host);
2803 disable_irq_wake(host->irq);
2804 }
2805
2806 sdhci_enable_card_detection(host);
2807
2808 return ret;
2809 }
2810
2811 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2812
sdhci_runtime_pm_get(struct sdhci_host * host)2813 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2814 {
2815 return pm_runtime_get_sync(host->mmc->parent);
2816 }
2817
sdhci_runtime_pm_put(struct sdhci_host * host)2818 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2819 {
2820 pm_runtime_mark_last_busy(host->mmc->parent);
2821 return pm_runtime_put_autosuspend(host->mmc->parent);
2822 }
2823
sdhci_runtime_pm_bus_on(struct sdhci_host * host)2824 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2825 {
2826 if (host->bus_on)
2827 return;
2828 host->bus_on = true;
2829 pm_runtime_get_noresume(host->mmc->parent);
2830 }
2831
sdhci_runtime_pm_bus_off(struct sdhci_host * host)2832 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2833 {
2834 if (!host->bus_on)
2835 return;
2836 host->bus_on = false;
2837 pm_runtime_put_noidle(host->mmc->parent);
2838 }
2839
sdhci_runtime_suspend_host(struct sdhci_host * host)2840 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2841 {
2842 unsigned long flags;
2843
2844 mmc_retune_timer_stop(host->mmc);
2845 mmc_retune_needed(host->mmc);
2846
2847 spin_lock_irqsave(&host->lock, flags);
2848 host->ier &= SDHCI_INT_CARD_INT;
2849 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2850 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2851 spin_unlock_irqrestore(&host->lock, flags);
2852
2853 synchronize_hardirq(host->irq);
2854
2855 spin_lock_irqsave(&host->lock, flags);
2856 host->runtime_suspended = true;
2857 spin_unlock_irqrestore(&host->lock, flags);
2858
2859 return 0;
2860 }
2861 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2862
sdhci_runtime_resume_host(struct sdhci_host * host)2863 int sdhci_runtime_resume_host(struct sdhci_host *host)
2864 {
2865 unsigned long flags;
2866 int host_flags = host->flags;
2867
2868 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2869 if (host->ops->enable_dma)
2870 host->ops->enable_dma(host);
2871 }
2872
2873 sdhci_init(host, 0);
2874
2875 /* Force clock and power re-program */
2876 host->pwr = 0;
2877 host->clock = 0;
2878 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2879 sdhci_do_set_ios(host, &host->mmc->ios);
2880
2881 if ((host_flags & SDHCI_PV_ENABLED) &&
2882 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2883 spin_lock_irqsave(&host->lock, flags);
2884 sdhci_enable_preset_value(host, true);
2885 spin_unlock_irqrestore(&host->lock, flags);
2886 }
2887
2888 spin_lock_irqsave(&host->lock, flags);
2889
2890 host->runtime_suspended = false;
2891
2892 /* Enable SDIO IRQ */
2893 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2894 sdhci_enable_sdio_irq_nolock(host, true);
2895
2896 /* Enable Card Detection */
2897 sdhci_enable_card_detection(host);
2898
2899 spin_unlock_irqrestore(&host->lock, flags);
2900
2901 return 0;
2902 }
2903 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2904
2905 #endif /* CONFIG_PM */
2906
2907 /*****************************************************************************\
2908 * *
2909 * Device allocation/registration *
2910 * *
2911 \*****************************************************************************/
2912
sdhci_alloc_host(struct device * dev,size_t priv_size)2913 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2914 size_t priv_size)
2915 {
2916 struct mmc_host *mmc;
2917 struct sdhci_host *host;
2918
2919 WARN_ON(dev == NULL);
2920
2921 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2922 if (!mmc)
2923 return ERR_PTR(-ENOMEM);
2924
2925 host = mmc_priv(mmc);
2926 host->mmc = mmc;
2927 host->mmc_host_ops = sdhci_ops;
2928 mmc->ops = &host->mmc_host_ops;
2929
2930 return host;
2931 }
2932
2933 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2934
sdhci_add_host(struct sdhci_host * host)2935 int sdhci_add_host(struct sdhci_host *host)
2936 {
2937 struct mmc_host *mmc;
2938 u32 caps[2] = {0, 0};
2939 u32 max_current_caps;
2940 unsigned int ocr_avail;
2941 unsigned int override_timeout_clk;
2942 u32 max_clk;
2943 int ret;
2944
2945 WARN_ON(host == NULL);
2946 if (host == NULL)
2947 return -EINVAL;
2948
2949 mmc = host->mmc;
2950
2951 if (debug_quirks)
2952 host->quirks = debug_quirks;
2953 if (debug_quirks2)
2954 host->quirks2 = debug_quirks2;
2955
2956 override_timeout_clk = host->timeout_clk;
2957
2958 sdhci_do_reset(host, SDHCI_RESET_ALL);
2959
2960 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2961 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2962 >> SDHCI_SPEC_VER_SHIFT;
2963 if (host->version > SDHCI_SPEC_300) {
2964 pr_err("%s: Unknown controller version (%d). "
2965 "You may experience problems.\n", mmc_hostname(mmc),
2966 host->version);
2967 }
2968
2969 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2970 sdhci_readl(host, SDHCI_CAPABILITIES);
2971
2972 if (host->version >= SDHCI_SPEC_300)
2973 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2974 host->caps1 :
2975 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2976
2977 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2978 host->flags |= SDHCI_USE_SDMA;
2979 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2980 DBG("Controller doesn't have SDMA capability\n");
2981 else
2982 host->flags |= SDHCI_USE_SDMA;
2983
2984 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2985 (host->flags & SDHCI_USE_SDMA)) {
2986 DBG("Disabling DMA as it is marked broken\n");
2987 host->flags &= ~SDHCI_USE_SDMA;
2988 }
2989
2990 if ((host->version >= SDHCI_SPEC_200) &&
2991 (caps[0] & SDHCI_CAN_DO_ADMA2))
2992 host->flags |= SDHCI_USE_ADMA;
2993
2994 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2995 (host->flags & SDHCI_USE_ADMA)) {
2996 DBG("Disabling ADMA as it is marked broken\n");
2997 host->flags &= ~SDHCI_USE_ADMA;
2998 }
2999
3000 /*
3001 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3002 * and *must* do 64-bit DMA. A driver has the opportunity to change
3003 * that during the first call to ->enable_dma(). Similarly
3004 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3005 * implement.
3006 */
3007 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
3008 host->flags |= SDHCI_USE_64_BIT_DMA;
3009
3010 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3011 if (host->ops->enable_dma) {
3012 if (host->ops->enable_dma(host)) {
3013 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3014 mmc_hostname(mmc));
3015 host->flags &=
3016 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3017 }
3018 }
3019 }
3020
3021 /* SDMA does not support 64-bit DMA */
3022 if (host->flags & SDHCI_USE_64_BIT_DMA)
3023 host->flags &= ~SDHCI_USE_SDMA;
3024
3025 if (host->flags & SDHCI_USE_ADMA) {
3026 /*
3027 * The DMA descriptor table size is calculated as the maximum
3028 * number of segments times 2, to allow for an alignment
3029 * descriptor for each segment, plus 1 for a nop end descriptor,
3030 * all multipled by the descriptor size.
3031 */
3032 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3033 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3034 SDHCI_ADMA2_64_DESC_SZ;
3035 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3036 } else {
3037 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3038 SDHCI_ADMA2_32_DESC_SZ;
3039 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3040 }
3041 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
3042 host->adma_table_sz,
3043 &host->adma_addr,
3044 GFP_KERNEL);
3045 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3046 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3047 if (!host->adma_table || !host->align_buffer) {
3048 if (host->adma_table)
3049 dma_free_coherent(mmc_dev(mmc),
3050 host->adma_table_sz,
3051 host->adma_table,
3052 host->adma_addr);
3053 kfree(host->align_buffer);
3054 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3055 mmc_hostname(mmc));
3056 host->flags &= ~SDHCI_USE_ADMA;
3057 host->adma_table = NULL;
3058 host->align_buffer = NULL;
3059 } else if (host->adma_addr & (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3060 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3061 mmc_hostname(mmc));
3062 host->flags &= ~SDHCI_USE_ADMA;
3063 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3064 host->adma_table, host->adma_addr);
3065 kfree(host->align_buffer);
3066 host->adma_table = NULL;
3067 host->align_buffer = NULL;
3068 }
3069 }
3070
3071 /*
3072 * If we use DMA, then it's up to the caller to set the DMA
3073 * mask, but PIO does not need the hw shim so we set a new
3074 * mask here in that case.
3075 */
3076 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3077 host->dma_mask = DMA_BIT_MASK(64);
3078 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3079 }
3080
3081 if (host->version >= SDHCI_SPEC_300)
3082 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3083 >> SDHCI_CLOCK_BASE_SHIFT;
3084 else
3085 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3086 >> SDHCI_CLOCK_BASE_SHIFT;
3087
3088 host->max_clk *= 1000000;
3089 if (host->max_clk == 0 || host->quirks &
3090 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3091 if (!host->ops->get_max_clock) {
3092 pr_err("%s: Hardware doesn't specify base clock "
3093 "frequency.\n", mmc_hostname(mmc));
3094 return -ENODEV;
3095 }
3096 host->max_clk = host->ops->get_max_clock(host);
3097 }
3098
3099 /*
3100 * In case of Host Controller v3.00, find out whether clock
3101 * multiplier is supported.
3102 */
3103 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3104 SDHCI_CLOCK_MUL_SHIFT;
3105
3106 /*
3107 * In case the value in Clock Multiplier is 0, then programmable
3108 * clock mode is not supported, otherwise the actual clock
3109 * multiplier is one more than the value of Clock Multiplier
3110 * in the Capabilities Register.
3111 */
3112 if (host->clk_mul)
3113 host->clk_mul += 1;
3114
3115 /*
3116 * Set host parameters.
3117 */
3118 max_clk = host->max_clk;
3119
3120 if (host->ops->get_min_clock)
3121 mmc->f_min = host->ops->get_min_clock(host);
3122 else if (host->version >= SDHCI_SPEC_300) {
3123 if (host->clk_mul)
3124 max_clk = host->max_clk * host->clk_mul;
3125 /*
3126 * Divided Clock Mode minimum clock rate is always less than
3127 * Programmable Clock Mode minimum clock rate.
3128 */
3129 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3130 } else
3131 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3132
3133 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3134 mmc->f_max = max_clk;
3135
3136 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3137 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3138 SDHCI_TIMEOUT_CLK_SHIFT;
3139 if (host->timeout_clk == 0) {
3140 if (host->ops->get_timeout_clock) {
3141 host->timeout_clk =
3142 host->ops->get_timeout_clock(host);
3143 } else {
3144 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3145 mmc_hostname(mmc));
3146 return -ENODEV;
3147 }
3148 }
3149
3150 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3151 host->timeout_clk *= 1000;
3152
3153 if (override_timeout_clk)
3154 host->timeout_clk = override_timeout_clk;
3155
3156 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3157 host->ops->get_max_timeout_count(host) : 1 << 27;
3158 mmc->max_busy_timeout /= host->timeout_clk;
3159 }
3160
3161 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3162 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3163
3164 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3165 host->flags |= SDHCI_AUTO_CMD12;
3166
3167 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3168 if ((host->version >= SDHCI_SPEC_300) &&
3169 ((host->flags & SDHCI_USE_ADMA) ||
3170 !(host->flags & SDHCI_USE_SDMA)) &&
3171 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3172 host->flags |= SDHCI_AUTO_CMD23;
3173 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3174 } else {
3175 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3176 }
3177
3178 /*
3179 * A controller may support 8-bit width, but the board itself
3180 * might not have the pins brought out. Boards that support
3181 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3182 * their platform code before calling sdhci_add_host(), and we
3183 * won't assume 8-bit width for hosts without that CAP.
3184 */
3185 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3186 mmc->caps |= MMC_CAP_4_BIT_DATA;
3187
3188 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3189 mmc->caps &= ~MMC_CAP_CMD23;
3190
3191 if (caps[0] & SDHCI_CAN_DO_HISPD)
3192 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3193
3194 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3195 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3196 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3197 mmc->caps |= MMC_CAP_NEEDS_POLL;
3198
3199 /* If there are external regulators, get them */
3200 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3201 return -EPROBE_DEFER;
3202
3203 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3204 if (!IS_ERR(mmc->supply.vqmmc)) {
3205 ret = regulator_enable(mmc->supply.vqmmc);
3206 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3207 1950000))
3208 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3209 SDHCI_SUPPORT_SDR50 |
3210 SDHCI_SUPPORT_DDR50);
3211 if (ret) {
3212 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3213 mmc_hostname(mmc), ret);
3214 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3215 }
3216 }
3217
3218 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3219 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3220 SDHCI_SUPPORT_DDR50);
3221
3222 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3223 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3224 SDHCI_SUPPORT_DDR50))
3225 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3226
3227 /* SDR104 supports also implies SDR50 support */
3228 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3229 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3230 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3231 * field can be promoted to support HS200.
3232 */
3233 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3234 mmc->caps2 |= MMC_CAP2_HS200;
3235 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3236 mmc->caps |= MMC_CAP_UHS_SDR50;
3237
3238 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3239 (caps[1] & SDHCI_SUPPORT_HS400))
3240 mmc->caps2 |= MMC_CAP2_HS400;
3241
3242 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3243 (IS_ERR(mmc->supply.vqmmc) ||
3244 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3245 1300000)))
3246 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3247
3248 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3249 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3250 mmc->caps |= MMC_CAP_UHS_DDR50;
3251
3252 /* Does the host need tuning for SDR50? */
3253 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3254 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3255
3256 /* Does the host need tuning for SDR104 / HS200? */
3257 if (mmc->caps2 & MMC_CAP2_HS200)
3258 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3259
3260 /* Driver Type(s) (A, C, D) supported by the host */
3261 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3262 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3263 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3264 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3265 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3266 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3267
3268 /* Initial value for re-tuning timer count */
3269 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3270 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3271
3272 /*
3273 * In case Re-tuning Timer is not disabled, the actual value of
3274 * re-tuning timer will be 2 ^ (n - 1).
3275 */
3276 if (host->tuning_count)
3277 host->tuning_count = 1 << (host->tuning_count - 1);
3278
3279 /* Re-tuning mode supported by the Host Controller */
3280 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3281 SDHCI_RETUNING_MODE_SHIFT;
3282
3283 ocr_avail = 0;
3284
3285 /*
3286 * According to SD Host Controller spec v3.00, if the Host System
3287 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3288 * the value is meaningful only if Voltage Support in the Capabilities
3289 * register is set. The actual current value is 4 times the register
3290 * value.
3291 */
3292 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3293 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3294 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3295 if (curr > 0) {
3296
3297 /* convert to SDHCI_MAX_CURRENT format */
3298 curr = curr/1000; /* convert to mA */
3299 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3300
3301 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3302 max_current_caps =
3303 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3304 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3305 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3306 }
3307 }
3308
3309 if (caps[0] & SDHCI_CAN_VDD_330) {
3310 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3311
3312 mmc->max_current_330 = ((max_current_caps &
3313 SDHCI_MAX_CURRENT_330_MASK) >>
3314 SDHCI_MAX_CURRENT_330_SHIFT) *
3315 SDHCI_MAX_CURRENT_MULTIPLIER;
3316 }
3317 if (caps[0] & SDHCI_CAN_VDD_300) {
3318 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3319
3320 mmc->max_current_300 = ((max_current_caps &
3321 SDHCI_MAX_CURRENT_300_MASK) >>
3322 SDHCI_MAX_CURRENT_300_SHIFT) *
3323 SDHCI_MAX_CURRENT_MULTIPLIER;
3324 }
3325 if (caps[0] & SDHCI_CAN_VDD_180) {
3326 ocr_avail |= MMC_VDD_165_195;
3327
3328 mmc->max_current_180 = ((max_current_caps &
3329 SDHCI_MAX_CURRENT_180_MASK) >>
3330 SDHCI_MAX_CURRENT_180_SHIFT) *
3331 SDHCI_MAX_CURRENT_MULTIPLIER;
3332 }
3333
3334 /* If OCR set by host, use it instead. */
3335 if (host->ocr_mask)
3336 ocr_avail = host->ocr_mask;
3337
3338 /* If OCR set by external regulators, give it highest prio. */
3339 if (mmc->ocr_avail)
3340 ocr_avail = mmc->ocr_avail;
3341
3342 mmc->ocr_avail = ocr_avail;
3343 mmc->ocr_avail_sdio = ocr_avail;
3344 if (host->ocr_avail_sdio)
3345 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3346 mmc->ocr_avail_sd = ocr_avail;
3347 if (host->ocr_avail_sd)
3348 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3349 else /* normal SD controllers don't support 1.8V */
3350 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3351 mmc->ocr_avail_mmc = ocr_avail;
3352 if (host->ocr_avail_mmc)
3353 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3354
3355 if (mmc->ocr_avail == 0) {
3356 pr_err("%s: Hardware doesn't report any "
3357 "support voltages.\n", mmc_hostname(mmc));
3358 return -ENODEV;
3359 }
3360
3361 spin_lock_init(&host->lock);
3362
3363 /*
3364 * Maximum number of segments. Depends on if the hardware
3365 * can do scatter/gather or not.
3366 */
3367 if (host->flags & SDHCI_USE_ADMA)
3368 mmc->max_segs = SDHCI_MAX_SEGS;
3369 else if (host->flags & SDHCI_USE_SDMA)
3370 mmc->max_segs = 1;
3371 else /* PIO */
3372 mmc->max_segs = SDHCI_MAX_SEGS;
3373
3374 /*
3375 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3376 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3377 * is less anyway.
3378 */
3379 mmc->max_req_size = 524288;
3380
3381 /*
3382 * Maximum segment size. Could be one segment with the maximum number
3383 * of bytes. When doing hardware scatter/gather, each entry cannot
3384 * be larger than 64 KiB though.
3385 */
3386 if (host->flags & SDHCI_USE_ADMA) {
3387 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3388 mmc->max_seg_size = 65535;
3389 else
3390 mmc->max_seg_size = 65536;
3391 } else {
3392 mmc->max_seg_size = mmc->max_req_size;
3393 }
3394
3395 /*
3396 * Maximum block size. This varies from controller to controller and
3397 * is specified in the capabilities register.
3398 */
3399 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3400 mmc->max_blk_size = 2;
3401 } else {
3402 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3403 SDHCI_MAX_BLOCK_SHIFT;
3404 if (mmc->max_blk_size >= 3) {
3405 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3406 mmc_hostname(mmc));
3407 mmc->max_blk_size = 0;
3408 }
3409 }
3410
3411 mmc->max_blk_size = 512 << mmc->max_blk_size;
3412
3413 /*
3414 * Maximum block count.
3415 */
3416 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3417
3418 /*
3419 * Init tasklets.
3420 */
3421 tasklet_init(&host->finish_tasklet,
3422 sdhci_tasklet_finish, (unsigned long)host);
3423
3424 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3425
3426 init_waitqueue_head(&host->buf_ready_int);
3427
3428 sdhci_init(host, 0);
3429
3430 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3431 IRQF_SHARED, mmc_hostname(mmc), host);
3432 if (ret) {
3433 pr_err("%s: Failed to request IRQ %d: %d\n",
3434 mmc_hostname(mmc), host->irq, ret);
3435 goto untasklet;
3436 }
3437
3438 #ifdef CONFIG_MMC_DEBUG
3439 sdhci_dumpregs(host);
3440 #endif
3441
3442 #ifdef SDHCI_USE_LEDS_CLASS
3443 snprintf(host->led_name, sizeof(host->led_name),
3444 "%s::", mmc_hostname(mmc));
3445 host->led.name = host->led_name;
3446 host->led.brightness = LED_OFF;
3447 host->led.default_trigger = mmc_hostname(mmc);
3448 host->led.brightness_set = sdhci_led_control;
3449
3450 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3451 if (ret) {
3452 pr_err("%s: Failed to register LED device: %d\n",
3453 mmc_hostname(mmc), ret);
3454 goto reset;
3455 }
3456 #endif
3457
3458 mmiowb();
3459
3460 mmc_add_host(mmc);
3461
3462 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3463 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3464 (host->flags & SDHCI_USE_ADMA) ?
3465 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3466 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3467
3468 sdhci_enable_card_detection(host);
3469
3470 return 0;
3471
3472 #ifdef SDHCI_USE_LEDS_CLASS
3473 reset:
3474 sdhci_do_reset(host, SDHCI_RESET_ALL);
3475 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3476 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3477 free_irq(host->irq, host);
3478 #endif
3479 untasklet:
3480 tasklet_kill(&host->finish_tasklet);
3481
3482 return ret;
3483 }
3484
3485 EXPORT_SYMBOL_GPL(sdhci_add_host);
3486
sdhci_remove_host(struct sdhci_host * host,int dead)3487 void sdhci_remove_host(struct sdhci_host *host, int dead)
3488 {
3489 struct mmc_host *mmc = host->mmc;
3490 unsigned long flags;
3491
3492 if (dead) {
3493 spin_lock_irqsave(&host->lock, flags);
3494
3495 host->flags |= SDHCI_DEVICE_DEAD;
3496
3497 if (host->mrq) {
3498 pr_err("%s: Controller removed during "
3499 " transfer!\n", mmc_hostname(mmc));
3500
3501 host->mrq->cmd->error = -ENOMEDIUM;
3502 tasklet_schedule(&host->finish_tasklet);
3503 }
3504
3505 spin_unlock_irqrestore(&host->lock, flags);
3506 }
3507
3508 sdhci_disable_card_detection(host);
3509
3510 mmc_remove_host(mmc);
3511
3512 #ifdef SDHCI_USE_LEDS_CLASS
3513 led_classdev_unregister(&host->led);
3514 #endif
3515
3516 if (!dead)
3517 sdhci_do_reset(host, SDHCI_RESET_ALL);
3518
3519 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3520 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3521 free_irq(host->irq, host);
3522
3523 del_timer_sync(&host->timer);
3524
3525 tasklet_kill(&host->finish_tasklet);
3526
3527 if (!IS_ERR(mmc->supply.vqmmc))
3528 regulator_disable(mmc->supply.vqmmc);
3529
3530 if (host->adma_table)
3531 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3532 host->adma_table, host->adma_addr);
3533 kfree(host->align_buffer);
3534
3535 host->adma_table = NULL;
3536 host->align_buffer = NULL;
3537 }
3538
3539 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3540
sdhci_free_host(struct sdhci_host * host)3541 void sdhci_free_host(struct sdhci_host *host)
3542 {
3543 mmc_free_host(host->mmc);
3544 }
3545
3546 EXPORT_SYMBOL_GPL(sdhci_free_host);
3547
3548 /*****************************************************************************\
3549 * *
3550 * Driver init/exit *
3551 * *
3552 \*****************************************************************************/
3553
sdhci_drv_init(void)3554 static int __init sdhci_drv_init(void)
3555 {
3556 pr_info(DRIVER_NAME
3557 ": Secure Digital Host Controller Interface driver\n");
3558 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3559
3560 return 0;
3561 }
3562
sdhci_drv_exit(void)3563 static void __exit sdhci_drv_exit(void)
3564 {
3565 }
3566
3567 module_init(sdhci_drv_init);
3568 module_exit(sdhci_drv_exit);
3569
3570 module_param(debug_quirks, uint, 0444);
3571 module_param(debug_quirks2, uint, 0444);
3572
3573 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3574 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3575 MODULE_LICENSE("GPL");
3576
3577 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3578 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
3579