1 /*
2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/module.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/highmem.h>
15 #include <linux/delay.h>
16
17 #include <linux/mmc/host.h>
18
19 #define DRV_NAME "via_sdmmc"
20
21 #define PCI_DEVICE_ID_VIA_9530 0x9530
22
23 #define VIA_CRDR_SDC_OFF 0x200
24 #define VIA_CRDR_DDMA_OFF 0x400
25 #define VIA_CRDR_PCICTRL_OFF 0x600
26
27 #define VIA_CRDR_MIN_CLOCK 375000
28 #define VIA_CRDR_MAX_CLOCK 48000000
29
30 /*
31 * PCI registers
32 */
33
34 #define VIA_CRDR_PCI_WORK_MODE 0x40
35 #define VIA_CRDR_PCI_DBG_MODE 0x41
36
37 /*
38 * SDC MMIO Registers
39 */
40
41 #define VIA_CRDR_SDCTRL 0x0
42 #define VIA_CRDR_SDCTRL_START 0x01
43 #define VIA_CRDR_SDCTRL_WRITE 0x04
44 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
45 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
46 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30
47 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40
48 #define VIA_CRDR_SDCTRL_STOP 0x70
49
50 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0
51 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000
52 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000
53 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000
54 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
55
56 #define VIA_CRDR_SDCARG 0x4
57
58 #define VIA_CRDR_SDBUSMODE 0x8
59 #define VIA_CRDR_SDMODE_4BIT 0x02
60 #define VIA_CRDR_SDMODE_CLK_ON 0x40
61
62 #define VIA_CRDR_SDBLKLEN 0xc
63 /*
64 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
65 * Bit 11 - Bit 13 : Reserved.
66 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
67 * INTEN : Enable SD host interrupt.
68 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
69 */
70 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
71 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000
72 #define VIA_CRDR_MAX_BLOCK_COUNT 65536
73 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048
74
75 #define VIA_CRDR_SDRESP0 0x10
76 #define VIA_CRDR_SDRESP1 0x14
77 #define VIA_CRDR_SDRESP2 0x18
78 #define VIA_CRDR_SDRESP3 0x1c
79
80 #define VIA_CRDR_SDCURBLKCNT 0x20
81
82 #define VIA_CRDR_SDINTMASK 0x24
83 /*
84 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
85 * BDDIE : Block Data transfer Done Interrupt Enable
86 * CIRIE : Card Insertion or Removal Interrupt Enable
87 * CRDIE : Command-Response transfer Done Interrupt Enable
88 * CRTOIE : Command-Response response TimeOut Interrupt Enable
89 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
90 * DTIE : Data access Timeout Interrupt Enable
91 * SCIE : reSponse CRC error Interrupt Enable
92 * RCIE : Read data CRC error Interrupt Enable
93 * WCIE : Write data CRC error Interrupt Enable
94 */
95 #define VIA_CRDR_SDINTMASK_MBDIE 0x10
96 #define VIA_CRDR_SDINTMASK_BDDIE 0x20
97 #define VIA_CRDR_SDINTMASK_CIRIE 0x80
98 #define VIA_CRDR_SDINTMASK_CRDIE 0x200
99 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400
100 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
101 #define VIA_CRDR_SDINTMASK_DTIE 0x1000
102 #define VIA_CRDR_SDINTMASK_SCIE 0x2000
103 #define VIA_CRDR_SDINTMASK_RCIE 0x4000
104 #define VIA_CRDR_SDINTMASK_WCIE 0x8000
105
106 #define VIA_CRDR_SDACTIVE_INTMASK \
107 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
108 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
109 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
110 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
111
112 #define VIA_CRDR_SDSTATUS 0x28
113 /*
114 * CECC : Reserved
115 * WP : SD card Write Protect status
116 * SLOTD : Reserved
117 * SLOTG : SD SLOT status(Gpi pin status)
118 * MBD : Multiple Blocks transfer Done interrupt status
119 * BDD : Block Data transfer Done interrupt status
120 * CD : Reserved
121 * CIR : Card Insertion or Removal interrupt detected on GPI pin
122 * IO : Reserved
123 * CRD : Command-Response transfer Done interrupt status
124 * CRTO : Command-Response response TimeOut interrupt status
125 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
126 * DT : Data access Timeout interrupt status
127 * SC : reSponse CRC error interrupt status
128 * RC : Read data CRC error interrupt status
129 * WC : Write data CRC error interrupt status
130 */
131 #define VIA_CRDR_SDSTS_CECC 0x01
132 #define VIA_CRDR_SDSTS_WP 0x02
133 #define VIA_CRDR_SDSTS_SLOTD 0x04
134 #define VIA_CRDR_SDSTS_SLOTG 0x08
135 #define VIA_CRDR_SDSTS_MBD 0x10
136 #define VIA_CRDR_SDSTS_BDD 0x20
137 #define VIA_CRDR_SDSTS_CD 0x40
138 #define VIA_CRDR_SDSTS_CIR 0x80
139 #define VIA_CRDR_SDSTS_IO 0x100
140 #define VIA_CRDR_SDSTS_CRD 0x200
141 #define VIA_CRDR_SDSTS_CRTO 0x400
142 #define VIA_CRDR_SDSTS_ASCRDIE 0x800
143 #define VIA_CRDR_SDSTS_DT 0x1000
144 #define VIA_CRDR_SDSTS_SC 0x2000
145 #define VIA_CRDR_SDSTS_RC 0x4000
146 #define VIA_CRDR_SDSTS_WC 0x8000
147
148 #define VIA_CRDR_SDSTS_IGN_MASK\
149 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
150 #define VIA_CRDR_SDSTS_INT_MASK \
151 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
152 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
153 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
154 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
155 #define VIA_CRDR_SDSTS_W1C_MASK \
156 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
157 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
158 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
159 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
160 #define VIA_CRDR_SDSTS_CMD_MASK \
161 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
162 #define VIA_CRDR_SDSTS_DATA_MASK\
163 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
164 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
165
166 #define VIA_CRDR_SDSTATUS2 0x2a
167 /*
168 * CFE : Enable SD host automatic Clock FReezing
169 */
170 #define VIA_CRDR_SDSTS_CFE 0x80
171
172 #define VIA_CRDR_SDRSPTMO 0x2C
173
174 #define VIA_CRDR_SDCLKSEL 0x30
175
176 #define VIA_CRDR_SDEXTCTRL 0x34
177 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
178 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
179 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
180 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
181 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
182 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
183 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
184 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80
185 /* 0x38-0xFF reserved */
186
187 /*
188 * Data DMA Control Registers
189 */
190
191 #define VIA_CRDR_DMABASEADD 0x0
192 #define VIA_CRDR_DMACOUNTER 0x4
193
194 #define VIA_CRDR_DMACTRL 0x8
195 /*
196 * DIR :Transaction Direction
197 * 0 : From card to memory
198 * 1 : From memory to card
199 */
200 #define VIA_CRDR_DMACTRL_DIR 0x100
201 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000
202 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000
203
204 #define VIA_CRDR_DMASTS 0xc
205
206 #define VIA_CRDR_DMASTART 0x10
207 /*0x14-0xFF reserved*/
208
209 /*
210 * PCI Control Registers
211 */
212
213 /*0x0 - 0x1 reserved*/
214 #define VIA_CRDR_PCICLKGATT 0x2
215 /*
216 * SFTRST :
217 * 0 : Soft reset all the controller and it will be de-asserted automatically
218 * 1 : Soft reset is de-asserted
219 */
220 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01
221 /*
222 * 3V3 : Pad power select
223 * 0 : 1.8V
224 * 1 : 3.3V
225 * NOTE : No mater what the actual value should be, this bit always
226 * read as 0. This is a hardware bug.
227 */
228 #define VIA_CRDR_PCICLKGATT_3V3 0x10
229 /*
230 * PAD_PWRON : Pad Power on/off select
231 * 0 : Power off
232 * 1 : Power on
233 * NOTE : No mater what the actual value should be, this bit always
234 * read as 0. This is a hardware bug.
235 */
236 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
237
238 #define VIA_CRDR_PCISDCCLK 0x5
239
240 #define VIA_CRDR_PCIDMACLK 0x7
241 #define VIA_CRDR_PCIDMACLK_SDC 0x2
242
243 #define VIA_CRDR_PCIINTCTRL 0x8
244 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
245
246 #define VIA_CRDR_PCIINTSTATUS 0x9
247 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04
248
249 #define VIA_CRDR_PCITMOCTRL 0xa
250 #define VIA_CRDR_PCITMOCTRL_NO 0x0
251 #define VIA_CRDR_PCITMOCTRL_32US 0x1
252 #define VIA_CRDR_PCITMOCTRL_256US 0x2
253 #define VIA_CRDR_PCITMOCTRL_1024US 0x3
254 #define VIA_CRDR_PCITMOCTRL_256MS 0x4
255 #define VIA_CRDR_PCITMOCTRL_512MS 0x5
256 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6
257
258 /*0xB-0xFF reserved*/
259
260 enum PCI_HOST_CLK_CONTROL {
261 PCI_CLK_375K = 0x03,
262 PCI_CLK_8M = 0x04,
263 PCI_CLK_12M = 0x00,
264 PCI_CLK_16M = 0x05,
265 PCI_CLK_24M = 0x01,
266 PCI_CLK_33M = 0x06,
267 PCI_CLK_48M = 0x02
268 };
269
270 struct sdhcreg {
271 u32 sdcontrol_reg;
272 u32 sdcmdarg_reg;
273 u32 sdbusmode_reg;
274 u32 sdblklen_reg;
275 u32 sdresp_reg[4];
276 u32 sdcurblkcnt_reg;
277 u32 sdintmask_reg;
278 u32 sdstatus_reg;
279 u32 sdrsptmo_reg;
280 u32 sdclksel_reg;
281 u32 sdextctrl_reg;
282 };
283
284 struct pcictrlreg {
285 u8 reserve[2];
286 u8 pciclkgat_reg;
287 u8 pcinfcclk_reg;
288 u8 pcimscclk_reg;
289 u8 pcisdclk_reg;
290 u8 pcicaclk_reg;
291 u8 pcidmaclk_reg;
292 u8 pciintctrl_reg;
293 u8 pciintstatus_reg;
294 u8 pcitmoctrl_reg;
295 u8 Resv;
296 };
297
298 struct via_crdr_mmc_host {
299 struct mmc_host *mmc;
300 struct mmc_request *mrq;
301 struct mmc_command *cmd;
302 struct mmc_data *data;
303
304 void __iomem *mmiobase;
305 void __iomem *sdhc_mmiobase;
306 void __iomem *ddma_mmiobase;
307 void __iomem *pcictrl_mmiobase;
308
309 struct pcictrlreg pm_pcictrl_reg;
310 struct sdhcreg pm_sdhc_reg;
311
312 struct work_struct carddet_work;
313 struct tasklet_struct finish_tasklet;
314
315 struct timer_list timer;
316 spinlock_t lock;
317 u8 power;
318 int reject;
319 unsigned int quirks;
320 };
321
322 /* some devices need a very long delay for power to stabilize */
323 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
324
325 static struct pci_device_id via_ids[] = {
326 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
328 {0,}
329 };
330
331 MODULE_DEVICE_TABLE(pci, via_ids);
332
via_print_sdchc(struct via_crdr_mmc_host * host)333 static void via_print_sdchc(struct via_crdr_mmc_host *host)
334 {
335 void __iomem *addrbase = host->sdhc_mmiobase;
336
337 pr_debug("SDC MMIO Registers:\n");
338 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
339 readl(addrbase + VIA_CRDR_SDCTRL),
340 readl(addrbase + VIA_CRDR_SDCARG),
341 readl(addrbase + VIA_CRDR_SDBUSMODE));
342 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
343 readl(addrbase + VIA_CRDR_SDBLKLEN),
344 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
345 readl(addrbase + VIA_CRDR_SDINTMASK));
346 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
347 readl(addrbase + VIA_CRDR_SDSTATUS),
348 readl(addrbase + VIA_CRDR_SDCLKSEL),
349 readl(addrbase + VIA_CRDR_SDEXTCTRL));
350 }
351
via_print_pcictrl(struct via_crdr_mmc_host * host)352 static void via_print_pcictrl(struct via_crdr_mmc_host *host)
353 {
354 void __iomem *addrbase = host->pcictrl_mmiobase;
355
356 pr_debug("PCI Control Registers:\n");
357 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
358 readb(addrbase + VIA_CRDR_PCICLKGATT),
359 readb(addrbase + VIA_CRDR_PCISDCCLK),
360 readb(addrbase + VIA_CRDR_PCIDMACLK));
361 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
362 readb(addrbase + VIA_CRDR_PCIINTCTRL),
363 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
364 }
365
via_save_pcictrlreg(struct via_crdr_mmc_host * host)366 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
367 {
368 struct pcictrlreg *pm_pcictrl_reg;
369 void __iomem *addrbase;
370
371 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
372 addrbase = host->pcictrl_mmiobase;
373
374 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
375 pm_pcictrl_reg->pciclkgat_reg |=
376 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
377 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
378 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
379 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
380 pm_pcictrl_reg->pciintstatus_reg =
381 readb(addrbase + VIA_CRDR_PCIINTSTATUS);
382 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
383 }
384
via_restore_pcictrlreg(struct via_crdr_mmc_host * host)385 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
386 {
387 struct pcictrlreg *pm_pcictrl_reg;
388 void __iomem *addrbase;
389
390 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
391 addrbase = host->pcictrl_mmiobase;
392
393 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
394 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
395 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
396 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
397 writeb(pm_pcictrl_reg->pciintstatus_reg,
398 addrbase + VIA_CRDR_PCIINTSTATUS);
399 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
400 }
401
via_save_sdcreg(struct via_crdr_mmc_host * host)402 static void via_save_sdcreg(struct via_crdr_mmc_host *host)
403 {
404 struct sdhcreg *pm_sdhc_reg;
405 void __iomem *addrbase;
406
407 pm_sdhc_reg = &(host->pm_sdhc_reg);
408 addrbase = host->sdhc_mmiobase;
409
410 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
411 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
412 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
413 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
414 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
415 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
416 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
417 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
418 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
419 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
420 }
421
via_restore_sdcreg(struct via_crdr_mmc_host * host)422 static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
423 {
424 struct sdhcreg *pm_sdhc_reg;
425 void __iomem *addrbase;
426
427 pm_sdhc_reg = &(host->pm_sdhc_reg);
428 addrbase = host->sdhc_mmiobase;
429
430 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
431 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
432 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
433 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
434 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
435 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
436 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
437 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
438 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
439 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
440 }
441
via_pwron_sleep(struct via_crdr_mmc_host * sdhost)442 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
443 {
444 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
445 msleep(300);
446 else
447 msleep(3);
448 }
449
via_set_ddma(struct via_crdr_mmc_host * host,dma_addr_t dmaaddr,u32 count,int dir,int enirq)450 static void via_set_ddma(struct via_crdr_mmc_host *host,
451 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
452 {
453 void __iomem *addrbase;
454 u32 ctrl_data = 0;
455
456 if (enirq)
457 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
458
459 if (dir)
460 ctrl_data |= VIA_CRDR_DMACTRL_DIR;
461
462 addrbase = host->ddma_mmiobase;
463
464 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
465 writel(count, addrbase + VIA_CRDR_DMACOUNTER);
466 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
467 writel(0x01, addrbase + VIA_CRDR_DMASTART);
468
469 /* It seems that our DMA can not work normally with 375kHz clock */
470 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
471 addrbase = host->pcictrl_mmiobase;
472 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
473 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
474 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
475 }
476 }
477
via_sdc_preparedata(struct via_crdr_mmc_host * host,struct mmc_data * data)478 static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
479 struct mmc_data *data)
480 {
481 void __iomem *addrbase;
482 u32 blk_reg;
483 int count;
484
485 WARN_ON(host->data);
486
487 /* Sanity checks */
488 BUG_ON(data->blksz > host->mmc->max_blk_size);
489 BUG_ON(data->blocks > host->mmc->max_blk_count);
490
491 host->data = data;
492
493 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
494 ((data->flags & MMC_DATA_READ) ?
495 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
496 BUG_ON(count != 1);
497
498 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
499 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
500
501 addrbase = host->sdhc_mmiobase;
502
503 blk_reg = data->blksz - 1;
504 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
505 blk_reg |= (data->blocks) << 16;
506
507 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
508 }
509
via_sdc_get_response(struct via_crdr_mmc_host * host,struct mmc_command * cmd)510 static void via_sdc_get_response(struct via_crdr_mmc_host *host,
511 struct mmc_command *cmd)
512 {
513 void __iomem *addrbase = host->sdhc_mmiobase;
514 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
515 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
516 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
517 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
518
519 if (cmd->flags & MMC_RSP_136) {
520 cmd->resp[0] = ((u8) (dwdata1)) |
521 (((u8) (dwdata0 >> 24)) << 8) |
522 (((u8) (dwdata0 >> 16)) << 16) |
523 (((u8) (dwdata0 >> 8)) << 24);
524
525 cmd->resp[1] = ((u8) (dwdata2)) |
526 (((u8) (dwdata1 >> 24)) << 8) |
527 (((u8) (dwdata1 >> 16)) << 16) |
528 (((u8) (dwdata1 >> 8)) << 24);
529
530 cmd->resp[2] = ((u8) (dwdata3)) |
531 (((u8) (dwdata2 >> 24)) << 8) |
532 (((u8) (dwdata2 >> 16)) << 16) |
533 (((u8) (dwdata2 >> 8)) << 24);
534
535 cmd->resp[3] = 0xff |
536 ((((u8) (dwdata3 >> 24))) << 8) |
537 (((u8) (dwdata3 >> 16)) << 16) |
538 (((u8) (dwdata3 >> 8)) << 24);
539 } else {
540 dwdata0 >>= 8;
541 cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
542 (((dwdata0 >> 8) & 0xff) << 16) |
543 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
544
545 dwdata1 >>= 8;
546 cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
547 (((dwdata1 >> 8) & 0xff) << 16) |
548 (((dwdata1 >> 16) & 0xff) << 8);
549 }
550 }
551
via_sdc_send_command(struct via_crdr_mmc_host * host,struct mmc_command * cmd)552 static void via_sdc_send_command(struct via_crdr_mmc_host *host,
553 struct mmc_command *cmd)
554 {
555 void __iomem *addrbase;
556 struct mmc_data *data;
557 u32 cmdctrl = 0;
558
559 WARN_ON(host->cmd);
560
561 data = cmd->data;
562 mod_timer(&host->timer, jiffies + HZ);
563 host->cmd = cmd;
564
565 /*Command index*/
566 cmdctrl = cmd->opcode << 8;
567
568 /*Response type*/
569 switch (mmc_resp_type(cmd)) {
570 case MMC_RSP_NONE:
571 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
572 break;
573 case MMC_RSP_R1:
574 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
575 break;
576 case MMC_RSP_R1B:
577 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
578 break;
579 case MMC_RSP_R2:
580 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
581 break;
582 case MMC_RSP_R3:
583 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
584 break;
585 default:
586 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
587 break;
588 }
589
590 if (!(cmd->data))
591 goto nodata;
592
593 via_sdc_preparedata(host, data);
594
595 /*Command control*/
596 if (data->blocks > 1) {
597 if (data->flags & MMC_DATA_WRITE) {
598 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
599 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
600 } else {
601 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
602 }
603 } else {
604 if (data->flags & MMC_DATA_WRITE) {
605 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
606 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
607 } else {
608 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
609 }
610 }
611
612 nodata:
613 if (cmd == host->mrq->stop)
614 cmdctrl |= VIA_CRDR_SDCTRL_STOP;
615
616 cmdctrl |= VIA_CRDR_SDCTRL_START;
617
618 addrbase = host->sdhc_mmiobase;
619 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
620 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
621 }
622
via_sdc_finish_data(struct via_crdr_mmc_host * host)623 static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
624 {
625 struct mmc_data *data;
626
627 BUG_ON(!host->data);
628
629 data = host->data;
630 host->data = NULL;
631
632 if (data->error)
633 data->bytes_xfered = 0;
634 else
635 data->bytes_xfered = data->blocks * data->blksz;
636
637 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
638 ((data->flags & MMC_DATA_READ) ?
639 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
640
641 if (data->stop)
642 via_sdc_send_command(host, data->stop);
643 else
644 tasklet_schedule(&host->finish_tasklet);
645 }
646
via_sdc_finish_command(struct via_crdr_mmc_host * host)647 static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
648 {
649 via_sdc_get_response(host, host->cmd);
650
651 host->cmd->error = 0;
652
653 if (!host->cmd->data)
654 tasklet_schedule(&host->finish_tasklet);
655
656 host->cmd = NULL;
657 }
658
via_sdc_request(struct mmc_host * mmc,struct mmc_request * mrq)659 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
660 {
661 void __iomem *addrbase;
662 struct via_crdr_mmc_host *host;
663 unsigned long flags;
664 u16 status;
665
666 host = mmc_priv(mmc);
667
668 spin_lock_irqsave(&host->lock, flags);
669
670 addrbase = host->pcictrl_mmiobase;
671 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
672
673 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
674 status &= VIA_CRDR_SDSTS_W1C_MASK;
675 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
676
677 WARN_ON(host->mrq != NULL);
678 host->mrq = mrq;
679
680 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
681 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
682 host->mrq->cmd->error = -ENOMEDIUM;
683 tasklet_schedule(&host->finish_tasklet);
684 } else {
685 via_sdc_send_command(host, mrq->cmd);
686 }
687
688 mmiowb();
689 spin_unlock_irqrestore(&host->lock, flags);
690 }
691
via_sdc_set_power(struct via_crdr_mmc_host * host,unsigned short power,unsigned int on)692 static void via_sdc_set_power(struct via_crdr_mmc_host *host,
693 unsigned short power, unsigned int on)
694 {
695 unsigned long flags;
696 u8 gatt;
697
698 spin_lock_irqsave(&host->lock, flags);
699
700 host->power = (1 << power);
701
702 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
703 if (host->power == MMC_VDD_165_195)
704 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
705 else
706 gatt |= VIA_CRDR_PCICLKGATT_3V3;
707 if (on)
708 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
709 else
710 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
711 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
712
713 mmiowb();
714 spin_unlock_irqrestore(&host->lock, flags);
715
716 via_pwron_sleep(host);
717 }
718
via_sdc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)719 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
720 {
721 struct via_crdr_mmc_host *host;
722 unsigned long flags;
723 void __iomem *addrbase;
724 u32 org_data, sdextctrl;
725 u8 clock;
726
727 host = mmc_priv(mmc);
728
729 spin_lock_irqsave(&host->lock, flags);
730
731 addrbase = host->sdhc_mmiobase;
732 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
733 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
734
735 if (ios->bus_width == MMC_BUS_WIDTH_1)
736 org_data &= ~VIA_CRDR_SDMODE_4BIT;
737 else
738 org_data |= VIA_CRDR_SDMODE_4BIT;
739
740 if (ios->power_mode == MMC_POWER_OFF)
741 org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
742 else
743 org_data |= VIA_CRDR_SDMODE_CLK_ON;
744
745 if (ios->timing == MMC_TIMING_SD_HS)
746 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
747 else
748 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
749
750 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
751 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
752
753 if (ios->clock >= 48000000)
754 clock = PCI_CLK_48M;
755 else if (ios->clock >= 33000000)
756 clock = PCI_CLK_33M;
757 else if (ios->clock >= 24000000)
758 clock = PCI_CLK_24M;
759 else if (ios->clock >= 16000000)
760 clock = PCI_CLK_16M;
761 else if (ios->clock >= 12000000)
762 clock = PCI_CLK_12M;
763 else if (ios->clock >= 8000000)
764 clock = PCI_CLK_8M;
765 else
766 clock = PCI_CLK_375K;
767
768 addrbase = host->pcictrl_mmiobase;
769 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
770 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
771
772 mmiowb();
773 spin_unlock_irqrestore(&host->lock, flags);
774
775 if (ios->power_mode != MMC_POWER_OFF)
776 via_sdc_set_power(host, ios->vdd, 1);
777 else
778 via_sdc_set_power(host, ios->vdd, 0);
779 }
780
via_sdc_get_ro(struct mmc_host * mmc)781 static int via_sdc_get_ro(struct mmc_host *mmc)
782 {
783 struct via_crdr_mmc_host *host;
784 unsigned long flags;
785 u16 status;
786
787 host = mmc_priv(mmc);
788
789 spin_lock_irqsave(&host->lock, flags);
790
791 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
792
793 spin_unlock_irqrestore(&host->lock, flags);
794
795 return !(status & VIA_CRDR_SDSTS_WP);
796 }
797
798 static const struct mmc_host_ops via_sdc_ops = {
799 .request = via_sdc_request,
800 .set_ios = via_sdc_set_ios,
801 .get_ro = via_sdc_get_ro,
802 };
803
via_reset_pcictrl(struct via_crdr_mmc_host * host)804 static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
805 {
806 unsigned long flags;
807 u8 gatt;
808
809 spin_lock_irqsave(&host->lock, flags);
810
811 via_save_pcictrlreg(host);
812 via_save_sdcreg(host);
813
814 spin_unlock_irqrestore(&host->lock, flags);
815
816 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
817 if (host->power == MMC_VDD_165_195)
818 gatt &= VIA_CRDR_PCICLKGATT_3V3;
819 else
820 gatt |= VIA_CRDR_PCICLKGATT_3V3;
821 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
822 via_pwron_sleep(host);
823 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
824 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
825 msleep(3);
826
827 spin_lock_irqsave(&host->lock, flags);
828
829 via_restore_pcictrlreg(host);
830 via_restore_sdcreg(host);
831
832 mmiowb();
833 spin_unlock_irqrestore(&host->lock, flags);
834 }
835
via_sdc_cmd_isr(struct via_crdr_mmc_host * host,u16 intmask)836 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
837 {
838 BUG_ON(intmask == 0);
839
840 if (!host->cmd) {
841 pr_err("%s: Got command interrupt 0x%x even "
842 "though no command operation was in progress.\n",
843 mmc_hostname(host->mmc), intmask);
844 return;
845 }
846
847 if (intmask & VIA_CRDR_SDSTS_CRTO)
848 host->cmd->error = -ETIMEDOUT;
849 else if (intmask & VIA_CRDR_SDSTS_SC)
850 host->cmd->error = -EILSEQ;
851
852 if (host->cmd->error)
853 tasklet_schedule(&host->finish_tasklet);
854 else if (intmask & VIA_CRDR_SDSTS_CRD)
855 via_sdc_finish_command(host);
856 }
857
via_sdc_data_isr(struct via_crdr_mmc_host * host,u16 intmask)858 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
859 {
860 BUG_ON(intmask == 0);
861
862 if (!host->data)
863 return;
864
865 if (intmask & VIA_CRDR_SDSTS_DT)
866 host->data->error = -ETIMEDOUT;
867 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
868 host->data->error = -EILSEQ;
869
870 via_sdc_finish_data(host);
871 }
872
via_sdc_isr(int irq,void * dev_id)873 static irqreturn_t via_sdc_isr(int irq, void *dev_id)
874 {
875 struct via_crdr_mmc_host *sdhost = dev_id;
876 void __iomem *addrbase;
877 u8 pci_status;
878 u16 sd_status;
879 irqreturn_t result;
880
881 if (!sdhost)
882 return IRQ_NONE;
883
884 spin_lock(&sdhost->lock);
885
886 addrbase = sdhost->pcictrl_mmiobase;
887 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
888 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
889 result = IRQ_NONE;
890 goto out;
891 }
892
893 addrbase = sdhost->sdhc_mmiobase;
894 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
895 sd_status &= VIA_CRDR_SDSTS_INT_MASK;
896 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
897 if (!sd_status) {
898 result = IRQ_NONE;
899 goto out;
900 }
901
902 if (sd_status & VIA_CRDR_SDSTS_CIR) {
903 writew(sd_status & VIA_CRDR_SDSTS_CIR,
904 addrbase + VIA_CRDR_SDSTATUS);
905
906 schedule_work(&sdhost->carddet_work);
907 }
908
909 sd_status &= ~VIA_CRDR_SDSTS_CIR;
910 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
911 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
912 addrbase + VIA_CRDR_SDSTATUS);
913 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
914 }
915 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
916 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
917 addrbase + VIA_CRDR_SDSTATUS);
918 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
919 }
920
921 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
922 if (sd_status) {
923 pr_err("%s: Unexpected interrupt 0x%x\n",
924 mmc_hostname(sdhost->mmc), sd_status);
925 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
926 }
927
928 result = IRQ_HANDLED;
929
930 mmiowb();
931 out:
932 spin_unlock(&sdhost->lock);
933
934 return result;
935 }
936
via_sdc_timeout(unsigned long ulongdata)937 static void via_sdc_timeout(unsigned long ulongdata)
938 {
939 struct via_crdr_mmc_host *sdhost;
940 unsigned long flags;
941
942 sdhost = (struct via_crdr_mmc_host *)ulongdata;
943
944 spin_lock_irqsave(&sdhost->lock, flags);
945
946 if (sdhost->mrq) {
947 pr_err("%s: Timeout waiting for hardware interrupt."
948 "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
949 sdhost->mrq->cmd->opcode);
950
951 if (sdhost->data) {
952 writel(VIA_CRDR_DMACTRL_SFTRST,
953 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
954 sdhost->data->error = -ETIMEDOUT;
955 via_sdc_finish_data(sdhost);
956 } else {
957 if (sdhost->cmd)
958 sdhost->cmd->error = -ETIMEDOUT;
959 else
960 sdhost->mrq->cmd->error = -ETIMEDOUT;
961 tasklet_schedule(&sdhost->finish_tasklet);
962 }
963 }
964
965 mmiowb();
966 spin_unlock_irqrestore(&sdhost->lock, flags);
967 }
968
via_sdc_tasklet_finish(unsigned long param)969 static void via_sdc_tasklet_finish(unsigned long param)
970 {
971 struct via_crdr_mmc_host *host;
972 unsigned long flags;
973 struct mmc_request *mrq;
974
975 host = (struct via_crdr_mmc_host *)param;
976
977 spin_lock_irqsave(&host->lock, flags);
978
979 del_timer(&host->timer);
980 mrq = host->mrq;
981 host->mrq = NULL;
982 host->cmd = NULL;
983 host->data = NULL;
984
985 spin_unlock_irqrestore(&host->lock, flags);
986
987 mmc_request_done(host->mmc, mrq);
988 }
989
via_sdc_card_detect(struct work_struct * work)990 static void via_sdc_card_detect(struct work_struct *work)
991 {
992 struct via_crdr_mmc_host *host;
993 void __iomem *addrbase;
994 unsigned long flags;
995 u16 status;
996
997 host = container_of(work, struct via_crdr_mmc_host, carddet_work);
998
999 addrbase = host->ddma_mmiobase;
1000 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
1001
1002 spin_lock_irqsave(&host->lock, flags);
1003
1004 addrbase = host->pcictrl_mmiobase;
1005 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1006
1007 addrbase = host->sdhc_mmiobase;
1008 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1009 if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1010 if (host->mrq) {
1011 pr_err("%s: Card removed during transfer!\n",
1012 mmc_hostname(host->mmc));
1013 host->mrq->cmd->error = -ENOMEDIUM;
1014 tasklet_schedule(&host->finish_tasklet);
1015 }
1016
1017 mmiowb();
1018 spin_unlock_irqrestore(&host->lock, flags);
1019
1020 via_reset_pcictrl(host);
1021
1022 spin_lock_irqsave(&host->lock, flags);
1023 }
1024
1025 mmiowb();
1026 spin_unlock_irqrestore(&host->lock, flags);
1027
1028 via_print_pcictrl(host);
1029 via_print_sdchc(host);
1030
1031 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1032 }
1033
via_init_mmc_host(struct via_crdr_mmc_host * host)1034 static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1035 {
1036 struct mmc_host *mmc = host->mmc;
1037 void __iomem *addrbase;
1038 u32 lenreg;
1039 u32 status;
1040
1041 init_timer(&host->timer);
1042 host->timer.data = (unsigned long)host;
1043 host->timer.function = via_sdc_timeout;
1044
1045 spin_lock_init(&host->lock);
1046
1047 mmc->f_min = VIA_CRDR_MIN_CLOCK;
1048 mmc->f_max = VIA_CRDR_MAX_CLOCK;
1049 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1050 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1051 mmc->ops = &via_sdc_ops;
1052
1053 /*Hardware cannot do scatter lists*/
1054 mmc->max_segs = 1;
1055
1056 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1057 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1058
1059 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1060 mmc->max_req_size = mmc->max_seg_size;
1061
1062 INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1063
1064 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1065 (unsigned long)host);
1066
1067 addrbase = host->sdhc_mmiobase;
1068 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1069 msleep(1);
1070
1071 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1072 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1073
1074 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1075 status &= VIA_CRDR_SDSTS_W1C_MASK;
1076 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1077
1078 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1079 status |= VIA_CRDR_SDSTS_CFE;
1080 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1081
1082 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1083
1084 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1085 msleep(1);
1086 }
1087
via_sd_probe(struct pci_dev * pcidev,const struct pci_device_id * id)1088 static int via_sd_probe(struct pci_dev *pcidev,
1089 const struct pci_device_id *id)
1090 {
1091 struct mmc_host *mmc;
1092 struct via_crdr_mmc_host *sdhost;
1093 u32 base, len;
1094 u8 gatt;
1095 int ret;
1096
1097 pr_info(DRV_NAME
1098 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1099 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1100 (int)pcidev->revision);
1101
1102 ret = pci_enable_device(pcidev);
1103 if (ret)
1104 return ret;
1105
1106 ret = pci_request_regions(pcidev, DRV_NAME);
1107 if (ret)
1108 goto disable;
1109
1110 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1111 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1112
1113 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1114 if (!mmc) {
1115 ret = -ENOMEM;
1116 goto release;
1117 }
1118
1119 sdhost = mmc_priv(mmc);
1120 sdhost->mmc = mmc;
1121 dev_set_drvdata(&pcidev->dev, sdhost);
1122
1123 len = pci_resource_len(pcidev, 0);
1124 base = pci_resource_start(pcidev, 0);
1125 sdhost->mmiobase = ioremap_nocache(base, len);
1126 if (!sdhost->mmiobase) {
1127 ret = -ENOMEM;
1128 goto free_mmc_host;
1129 }
1130
1131 sdhost->sdhc_mmiobase =
1132 sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1133 sdhost->ddma_mmiobase =
1134 sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1135 sdhost->pcictrl_mmiobase =
1136 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1137
1138 sdhost->power = MMC_VDD_165_195;
1139
1140 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1141 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1142 via_pwron_sleep(sdhost);
1143 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1144 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1145 msleep(3);
1146
1147 via_init_mmc_host(sdhost);
1148
1149 ret =
1150 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1151 sdhost);
1152 if (ret)
1153 goto unmap;
1154
1155 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1156 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1157 writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1158 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1159
1160 /* device-specific quirks */
1161 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1162 pcidev->subsystem_device == 0x3891)
1163 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1164
1165 mmc_add_host(mmc);
1166
1167 return 0;
1168
1169 unmap:
1170 iounmap(sdhost->mmiobase);
1171 free_mmc_host:
1172 dev_set_drvdata(&pcidev->dev, NULL);
1173 mmc_free_host(mmc);
1174 release:
1175 pci_release_regions(pcidev);
1176 disable:
1177 pci_disable_device(pcidev);
1178
1179 return ret;
1180 }
1181
via_sd_remove(struct pci_dev * pcidev)1182 static void via_sd_remove(struct pci_dev *pcidev)
1183 {
1184 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1185 unsigned long flags;
1186 u8 gatt;
1187
1188 spin_lock_irqsave(&sdhost->lock, flags);
1189
1190 /* Ensure we don't accept more commands from mmc layer */
1191 sdhost->reject = 1;
1192
1193 /* Disable generating further interrupts */
1194 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1195 mmiowb();
1196
1197 if (sdhost->mrq) {
1198 pr_err("%s: Controller removed during "
1199 "transfer\n", mmc_hostname(sdhost->mmc));
1200
1201 /* make sure all DMA is stopped */
1202 writel(VIA_CRDR_DMACTRL_SFTRST,
1203 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1204 mmiowb();
1205 sdhost->mrq->cmd->error = -ENOMEDIUM;
1206 if (sdhost->mrq->stop)
1207 sdhost->mrq->stop->error = -ENOMEDIUM;
1208 tasklet_schedule(&sdhost->finish_tasklet);
1209 }
1210 spin_unlock_irqrestore(&sdhost->lock, flags);
1211
1212 mmc_remove_host(sdhost->mmc);
1213
1214 free_irq(pcidev->irq, sdhost);
1215
1216 del_timer_sync(&sdhost->timer);
1217
1218 tasklet_kill(&sdhost->finish_tasklet);
1219
1220 /* switch off power */
1221 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1222 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1223 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1224
1225 iounmap(sdhost->mmiobase);
1226 dev_set_drvdata(&pcidev->dev, NULL);
1227 mmc_free_host(sdhost->mmc);
1228 pci_release_regions(pcidev);
1229 pci_disable_device(pcidev);
1230
1231 pr_info(DRV_NAME
1232 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1233 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1234 }
1235
1236 #ifdef CONFIG_PM
1237
via_init_sdc_pm(struct via_crdr_mmc_host * host)1238 static void via_init_sdc_pm(struct via_crdr_mmc_host *host)
1239 {
1240 struct sdhcreg *pm_sdhcreg;
1241 void __iomem *addrbase;
1242 u32 lenreg;
1243 u16 status;
1244
1245 pm_sdhcreg = &(host->pm_sdhc_reg);
1246 addrbase = host->sdhc_mmiobase;
1247
1248 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1249
1250 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1251 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1252
1253 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1254 status &= VIA_CRDR_SDSTS_W1C_MASK;
1255 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1256
1257 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1258 status |= VIA_CRDR_SDSTS_CFE;
1259 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1260
1261 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1262 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1263 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1264 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1265 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1266 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1267
1268 via_print_pcictrl(host);
1269 via_print_sdchc(host);
1270 }
1271
via_sd_suspend(struct pci_dev * pcidev,pm_message_t state)1272 static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state)
1273 {
1274 struct via_crdr_mmc_host *host;
1275 unsigned long flags;
1276
1277 host = pci_get_drvdata(pcidev);
1278
1279 spin_lock_irqsave(&host->lock, flags);
1280 via_save_pcictrlreg(host);
1281 via_save_sdcreg(host);
1282 spin_unlock_irqrestore(&host->lock, flags);
1283
1284 pci_save_state(pcidev);
1285 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1286 pci_disable_device(pcidev);
1287 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1288
1289 return 0;
1290 }
1291
via_sd_resume(struct pci_dev * pcidev)1292 static int via_sd_resume(struct pci_dev *pcidev)
1293 {
1294 struct via_crdr_mmc_host *sdhost;
1295 int ret = 0;
1296 u8 gatt;
1297
1298 sdhost = pci_get_drvdata(pcidev);
1299
1300 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1301 if (sdhost->power == MMC_VDD_165_195)
1302 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1303 else
1304 gatt |= VIA_CRDR_PCICLKGATT_3V3;
1305 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1306 via_pwron_sleep(sdhost);
1307 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1308 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1309 msleep(3);
1310
1311 msleep(100);
1312
1313 pci_set_power_state(pcidev, PCI_D0);
1314 pci_restore_state(pcidev);
1315 ret = pci_enable_device(pcidev);
1316 if (ret)
1317 return ret;
1318
1319 via_restore_pcictrlreg(sdhost);
1320 via_init_sdc_pm(sdhost);
1321
1322 return ret;
1323 }
1324
1325 #else /* CONFIG_PM */
1326
1327 #define via_sd_suspend NULL
1328 #define via_sd_resume NULL
1329
1330 #endif /* CONFIG_PM */
1331
1332 static struct pci_driver via_sd_driver = {
1333 .name = DRV_NAME,
1334 .id_table = via_ids,
1335 .probe = via_sd_probe,
1336 .remove = via_sd_remove,
1337 .suspend = via_sd_suspend,
1338 .resume = via_sd_resume,
1339 };
1340
1341 module_pci_driver(via_sd_driver);
1342
1343 MODULE_LICENSE("GPL");
1344 MODULE_AUTHOR("VIA Technologies Inc.");
1345 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");
1346