1 /*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/wait.h>
23 #include <linux/mutex.h>
24 #include <linux/slab.h>
25 #include <linux/mtd/mtd.h>
26 #include <linux/module.h>
27
28 #include "denali.h"
29
30 MODULE_LICENSE("GPL");
31
32 /*
33 * We define a module parameter that allows the user to override
34 * the hardware and decide what timing mode should be used.
35 */
36 #define NAND_DEFAULT_TIMINGS -1
37
38 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
39 module_param(onfi_timing_mode, int, S_IRUGO);
40 MODULE_PARM_DESC(onfi_timing_mode,
41 "Overrides default ONFI setting. -1 indicates use default timings");
42
43 #define DENALI_NAND_NAME "denali-nand"
44
45 /*
46 * We define a macro here that combines all interrupts this driver uses into
47 * a single constant value, for convenience.
48 */
49 #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
50 INTR_STATUS__ECC_TRANSACTION_DONE | \
51 INTR_STATUS__ECC_ERR | \
52 INTR_STATUS__PROGRAM_FAIL | \
53 INTR_STATUS__LOAD_COMP | \
54 INTR_STATUS__PROGRAM_COMP | \
55 INTR_STATUS__TIME_OUT | \
56 INTR_STATUS__ERASE_FAIL | \
57 INTR_STATUS__RST_COMP | \
58 INTR_STATUS__ERASE_COMP)
59
60 /*
61 * indicates whether or not the internal value for the flash bank is
62 * valid or not
63 */
64 #define CHIP_SELECT_INVALID -1
65
66 #define SUPPORT_8BITECC 1
67
68 /*
69 * This macro divides two integers and rounds fractional values up
70 * to the nearest integer value.
71 */
72 #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
73
74 /*
75 * this macro allows us to convert from an MTD structure to our own
76 * device context (denali) structure.
77 */
78 #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
79
80 /*
81 * These constants are defined by the driver to enable common driver
82 * configuration options.
83 */
84 #define SPARE_ACCESS 0x41
85 #define MAIN_ACCESS 0x42
86 #define MAIN_SPARE_ACCESS 0x43
87 #define PIPELINE_ACCESS 0x2000
88
89 #define DENALI_READ 0
90 #define DENALI_WRITE 0x100
91
92 /* types of device accesses. We can issue commands and get status */
93 #define COMMAND_CYCLE 0
94 #define ADDR_CYCLE 1
95 #define STATUS_CYCLE 2
96
97 /*
98 * this is a helper macro that allows us to
99 * format the bank into the proper bits for the controller
100 */
101 #define BANK(x) ((x) << 24)
102
103 /* forward declarations */
104 static void clear_interrupts(struct denali_nand_info *denali);
105 static uint32_t wait_for_irq(struct denali_nand_info *denali,
106 uint32_t irq_mask);
107 static void denali_irq_enable(struct denali_nand_info *denali,
108 uint32_t int_mask);
109 static uint32_t read_interrupt_status(struct denali_nand_info *denali);
110
111 /*
112 * Certain operations for the denali NAND controller use an indexed mode to
113 * read/write data. The operation is performed by writing the address value
114 * of the command to the device memory followed by the data. This function
115 * abstracts this common operation.
116 */
index_addr(struct denali_nand_info * denali,uint32_t address,uint32_t data)117 static void index_addr(struct denali_nand_info *denali,
118 uint32_t address, uint32_t data)
119 {
120 iowrite32(address, denali->flash_mem);
121 iowrite32(data, denali->flash_mem + 0x10);
122 }
123
124 /* Perform an indexed read of the device */
index_addr_read_data(struct denali_nand_info * denali,uint32_t address,uint32_t * pdata)125 static void index_addr_read_data(struct denali_nand_info *denali,
126 uint32_t address, uint32_t *pdata)
127 {
128 iowrite32(address, denali->flash_mem);
129 *pdata = ioread32(denali->flash_mem + 0x10);
130 }
131
132 /*
133 * We need to buffer some data for some of the NAND core routines.
134 * The operations manage buffering that data.
135 */
reset_buf(struct denali_nand_info * denali)136 static void reset_buf(struct denali_nand_info *denali)
137 {
138 denali->buf.head = denali->buf.tail = 0;
139 }
140
write_byte_to_buf(struct denali_nand_info * denali,uint8_t byte)141 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
142 {
143 denali->buf.buf[denali->buf.tail++] = byte;
144 }
145
146 /* reads the status of the device */
read_status(struct denali_nand_info * denali)147 static void read_status(struct denali_nand_info *denali)
148 {
149 uint32_t cmd;
150
151 /* initialize the data buffer to store status */
152 reset_buf(denali);
153
154 cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
155 if (cmd)
156 write_byte_to_buf(denali, NAND_STATUS_WP);
157 else
158 write_byte_to_buf(denali, 0);
159 }
160
161 /* resets a specific device connected to the core */
reset_bank(struct denali_nand_info * denali)162 static void reset_bank(struct denali_nand_info *denali)
163 {
164 uint32_t irq_status;
165 uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
166
167 clear_interrupts(denali);
168
169 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
170
171 irq_status = wait_for_irq(denali, irq_mask);
172
173 if (irq_status & INTR_STATUS__TIME_OUT)
174 dev_err(denali->dev, "reset bank failed.\n");
175 }
176
177 /* Reset the flash controller */
denali_nand_reset(struct denali_nand_info * denali)178 static uint16_t denali_nand_reset(struct denali_nand_info *denali)
179 {
180 int i;
181
182 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
183 __FILE__, __LINE__, __func__);
184
185 for (i = 0; i < denali->max_banks; i++)
186 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
187 denali->flash_reg + INTR_STATUS(i));
188
189 for (i = 0; i < denali->max_banks; i++) {
190 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
191 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) &
192 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
193 cpu_relax();
194 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
195 INTR_STATUS__TIME_OUT)
196 dev_dbg(denali->dev,
197 "NAND Reset operation timed out on bank %d\n", i);
198 }
199
200 for (i = 0; i < denali->max_banks; i++)
201 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
202 denali->flash_reg + INTR_STATUS(i));
203
204 return PASS;
205 }
206
207 /*
208 * this routine calculates the ONFI timing values for a given mode and
209 * programs the clocking register accordingly. The mode is determined by
210 * the get_onfi_nand_para routine.
211 */
nand_onfi_timing_set(struct denali_nand_info * denali,uint16_t mode)212 static void nand_onfi_timing_set(struct denali_nand_info *denali,
213 uint16_t mode)
214 {
215 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
216 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
217 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
218 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
219 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
220 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
221 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
222 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
223 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
224 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
225 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
226 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
227
228 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
229 uint16_t dv_window = 0;
230 uint16_t en_lo, en_hi;
231 uint16_t acc_clks;
232 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
233
234 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
235 __FILE__, __LINE__, __func__);
236
237 en_lo = CEIL_DIV(Trp[mode], CLK_X);
238 en_hi = CEIL_DIV(Treh[mode], CLK_X);
239 #if ONFI_BLOOM_TIME
240 if ((en_hi * CLK_X) < (Treh[mode] + 2))
241 en_hi++;
242 #endif
243
244 if ((en_lo + en_hi) * CLK_X < Trc[mode])
245 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
246
247 if ((en_lo + en_hi) < CLK_MULTI)
248 en_lo += CLK_MULTI - en_lo - en_hi;
249
250 while (dv_window < 8) {
251 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
252
253 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
254
255 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
256 data_invalid_rhoh : data_invalid_rloh;
257
258 dv_window = data_invalid - Trea[mode];
259
260 if (dv_window < 8)
261 en_lo++;
262 }
263
264 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
265
266 while (acc_clks * CLK_X - Trea[mode] < 3)
267 acc_clks++;
268
269 if (data_invalid - acc_clks * CLK_X < 2)
270 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
271 __FILE__, __LINE__);
272
273 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
274 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
275 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
276 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
277 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
278 if (cs_cnt == 0)
279 cs_cnt = 1;
280
281 if (Tcea[mode]) {
282 while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode])
283 cs_cnt++;
284 }
285
286 #if MODE5_WORKAROUND
287 if (mode == 5)
288 acc_clks = 5;
289 #endif
290
291 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
292 if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 &&
293 ioread32(denali->flash_reg + DEVICE_ID) == 0x88)
294 acc_clks = 6;
295
296 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
297 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
298 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
299 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
300 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
301 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
302 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
303 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
304 }
305
306 /* queries the NAND device to see what ONFI modes it supports. */
get_onfi_nand_para(struct denali_nand_info * denali)307 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
308 {
309 int i;
310
311 /*
312 * we needn't to do a reset here because driver has already
313 * reset all the banks before
314 */
315 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
316 ONFI_TIMING_MODE__VALUE))
317 return FAIL;
318
319 for (i = 5; i > 0; i--) {
320 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
321 (0x01 << i))
322 break;
323 }
324
325 nand_onfi_timing_set(denali, i);
326
327 /*
328 * By now, all the ONFI devices we know support the page cache
329 * rw feature. So here we enable the pipeline_rw_ahead feature
330 */
331 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
332 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
333
334 return PASS;
335 }
336
get_samsung_nand_para(struct denali_nand_info * denali,uint8_t device_id)337 static void get_samsung_nand_para(struct denali_nand_info *denali,
338 uint8_t device_id)
339 {
340 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
341 /* Set timing register values according to datasheet */
342 iowrite32(5, denali->flash_reg + ACC_CLKS);
343 iowrite32(20, denali->flash_reg + RE_2_WE);
344 iowrite32(12, denali->flash_reg + WE_2_RE);
345 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
346 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
347 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
348 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
349 }
350 }
351
get_toshiba_nand_para(struct denali_nand_info * denali)352 static void get_toshiba_nand_para(struct denali_nand_info *denali)
353 {
354 uint32_t tmp;
355
356 /*
357 * Workaround to fix a controller bug which reports a wrong
358 * spare area size for some kind of Toshiba NAND device
359 */
360 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
361 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
362 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
363 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
364 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
365 iowrite32(tmp,
366 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
367 #if SUPPORT_15BITECC
368 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
369 #elif SUPPORT_8BITECC
370 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
371 #endif
372 }
373 }
374
get_hynix_nand_para(struct denali_nand_info * denali,uint8_t device_id)375 static void get_hynix_nand_para(struct denali_nand_info *denali,
376 uint8_t device_id)
377 {
378 uint32_t main_size, spare_size;
379
380 switch (device_id) {
381 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
382 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
383 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
384 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
385 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
386 main_size = 4096 *
387 ioread32(denali->flash_reg + DEVICES_CONNECTED);
388 spare_size = 224 *
389 ioread32(denali->flash_reg + DEVICES_CONNECTED);
390 iowrite32(main_size,
391 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
392 iowrite32(spare_size,
393 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
394 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
395 #if SUPPORT_15BITECC
396 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
397 #elif SUPPORT_8BITECC
398 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
399 #endif
400 break;
401 default:
402 dev_warn(denali->dev,
403 "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
404 "Will use default parameter values instead.\n",
405 device_id);
406 }
407 }
408
409 /*
410 * determines how many NAND chips are connected to the controller. Note for
411 * Intel CE4100 devices we don't support more than one device.
412 */
find_valid_banks(struct denali_nand_info * denali)413 static void find_valid_banks(struct denali_nand_info *denali)
414 {
415 uint32_t id[denali->max_banks];
416 int i;
417
418 denali->total_used_banks = 1;
419 for (i = 0; i < denali->max_banks; i++) {
420 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
421 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
422 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
423
424 dev_dbg(denali->dev,
425 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
426
427 if (i == 0) {
428 if (!(id[i] & 0x0ff))
429 break; /* WTF? */
430 } else {
431 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
432 denali->total_used_banks++;
433 else
434 break;
435 }
436 }
437
438 if (denali->platform == INTEL_CE4100) {
439 /*
440 * Platform limitations of the CE4100 device limit
441 * users to a single chip solution for NAND.
442 * Multichip support is not enabled.
443 */
444 if (denali->total_used_banks != 1) {
445 dev_err(denali->dev,
446 "Sorry, Intel CE4100 only supports a single NAND device.\n");
447 BUG();
448 }
449 }
450 dev_dbg(denali->dev,
451 "denali->total_used_banks: %d\n", denali->total_used_banks);
452 }
453
454 /*
455 * Use the configuration feature register to determine the maximum number of
456 * banks that the hardware supports.
457 */
detect_max_banks(struct denali_nand_info * denali)458 static void detect_max_banks(struct denali_nand_info *denali)
459 {
460 uint32_t features = ioread32(denali->flash_reg + FEATURES);
461 /*
462 * Read the revision register, so we can calculate the max_banks
463 * properly: the encoding changed from rev 5.0 to 5.1
464 */
465 u32 revision = MAKE_COMPARABLE_REVISION(
466 ioread32(denali->flash_reg + REVISION));
467
468 if (revision < REVISION_5_1)
469 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
470 else
471 denali->max_banks = 1 << (features & FEATURES__N_BANKS);
472 }
473
detect_partition_feature(struct denali_nand_info * denali)474 static void detect_partition_feature(struct denali_nand_info *denali)
475 {
476 /*
477 * For MRST platform, denali->fwblks represent the
478 * number of blocks firmware is taken,
479 * FW is in protect partition and MTD driver has no
480 * permission to access it. So let driver know how many
481 * blocks it can't touch.
482 */
483 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
484 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
485 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
486 denali->fwblks =
487 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
488 MIN_MAX_BANK__MIN_VALUE) *
489 denali->blksperchip)
490 +
491 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
492 MIN_BLK_ADDR__VALUE);
493 } else {
494 denali->fwblks = SPECTRA_START_BLOCK;
495 }
496 } else {
497 denali->fwblks = SPECTRA_START_BLOCK;
498 }
499 }
500
denali_nand_timing_set(struct denali_nand_info * denali)501 static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
502 {
503 uint16_t status = PASS;
504 uint32_t id_bytes[8], addr;
505 uint8_t maf_id, device_id;
506 int i;
507
508 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
509 __FILE__, __LINE__, __func__);
510
511 /*
512 * Use read id method to get device ID and other params.
513 * For some NAND chips, controller can't report the correct
514 * device ID by reading from DEVICE_ID register
515 */
516 addr = MODE_11 | BANK(denali->flash_bank);
517 index_addr(denali, addr | 0, 0x90);
518 index_addr(denali, addr | 1, 0);
519 for (i = 0; i < 8; i++)
520 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
521 maf_id = id_bytes[0];
522 device_id = id_bytes[1];
523
524 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
525 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
526 if (FAIL == get_onfi_nand_para(denali))
527 return FAIL;
528 } else if (maf_id == 0xEC) { /* Samsung NAND */
529 get_samsung_nand_para(denali, device_id);
530 } else if (maf_id == 0x98) { /* Toshiba NAND */
531 get_toshiba_nand_para(denali);
532 } else if (maf_id == 0xAD) { /* Hynix NAND */
533 get_hynix_nand_para(denali, device_id);
534 }
535
536 dev_info(denali->dev,
537 "Dump timing register values:\n"
538 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
539 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
540 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
541 ioread32(denali->flash_reg + ACC_CLKS),
542 ioread32(denali->flash_reg + RE_2_WE),
543 ioread32(denali->flash_reg + RE_2_RE),
544 ioread32(denali->flash_reg + WE_2_RE),
545 ioread32(denali->flash_reg + ADDR_2_DATA),
546 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
547 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
548 ioread32(denali->flash_reg + CS_SETUP_CNT));
549
550 find_valid_banks(denali);
551
552 detect_partition_feature(denali);
553
554 /*
555 * If the user specified to override the default timings
556 * with a specific ONFI mode, we apply those changes here.
557 */
558 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
559 nand_onfi_timing_set(denali, onfi_timing_mode);
560
561 return status;
562 }
563
denali_set_intr_modes(struct denali_nand_info * denali,uint16_t INT_ENABLE)564 static void denali_set_intr_modes(struct denali_nand_info *denali,
565 uint16_t INT_ENABLE)
566 {
567 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
568 __FILE__, __LINE__, __func__);
569
570 if (INT_ENABLE)
571 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
572 else
573 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
574 }
575
576 /*
577 * validation function to verify that the controlling software is making
578 * a valid request
579 */
is_flash_bank_valid(int flash_bank)580 static inline bool is_flash_bank_valid(int flash_bank)
581 {
582 return flash_bank >= 0 && flash_bank < 4;
583 }
584
denali_irq_init(struct denali_nand_info * denali)585 static void denali_irq_init(struct denali_nand_info *denali)
586 {
587 uint32_t int_mask;
588 int i;
589
590 /* Disable global interrupts */
591 denali_set_intr_modes(denali, false);
592
593 int_mask = DENALI_IRQ_ALL;
594
595 /* Clear all status bits */
596 for (i = 0; i < denali->max_banks; ++i)
597 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
598
599 denali_irq_enable(denali, int_mask);
600 }
601
denali_irq_cleanup(int irqnum,struct denali_nand_info * denali)602 static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
603 {
604 denali_set_intr_modes(denali, false);
605 free_irq(irqnum, denali);
606 }
607
denali_irq_enable(struct denali_nand_info * denali,uint32_t int_mask)608 static void denali_irq_enable(struct denali_nand_info *denali,
609 uint32_t int_mask)
610 {
611 int i;
612
613 for (i = 0; i < denali->max_banks; ++i)
614 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
615 }
616
617 /*
618 * This function only returns when an interrupt that this driver cares about
619 * occurs. This is to reduce the overhead of servicing interrupts
620 */
denali_irq_detected(struct denali_nand_info * denali)621 static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
622 {
623 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
624 }
625
626 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
clear_interrupt(struct denali_nand_info * denali,uint32_t irq_mask)627 static inline void clear_interrupt(struct denali_nand_info *denali,
628 uint32_t irq_mask)
629 {
630 uint32_t intr_status_reg;
631
632 intr_status_reg = INTR_STATUS(denali->flash_bank);
633
634 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
635 }
636
clear_interrupts(struct denali_nand_info * denali)637 static void clear_interrupts(struct denali_nand_info *denali)
638 {
639 uint32_t status;
640
641 spin_lock_irq(&denali->irq_lock);
642
643 status = read_interrupt_status(denali);
644 clear_interrupt(denali, status);
645
646 denali->irq_status = 0x0;
647 spin_unlock_irq(&denali->irq_lock);
648 }
649
read_interrupt_status(struct denali_nand_info * denali)650 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
651 {
652 uint32_t intr_status_reg;
653
654 intr_status_reg = INTR_STATUS(denali->flash_bank);
655
656 return ioread32(denali->flash_reg + intr_status_reg);
657 }
658
659 /*
660 * This is the interrupt service routine. It handles all interrupts
661 * sent to this device. Note that on CE4100, this is a shared interrupt.
662 */
denali_isr(int irq,void * dev_id)663 static irqreturn_t denali_isr(int irq, void *dev_id)
664 {
665 struct denali_nand_info *denali = dev_id;
666 uint32_t irq_status;
667 irqreturn_t result = IRQ_NONE;
668
669 spin_lock(&denali->irq_lock);
670
671 /* check to see if a valid NAND chip has been selected. */
672 if (is_flash_bank_valid(denali->flash_bank)) {
673 /*
674 * check to see if controller generated the interrupt,
675 * since this is a shared interrupt
676 */
677 irq_status = denali_irq_detected(denali);
678 if (irq_status != 0) {
679 /* handle interrupt */
680 /* first acknowledge it */
681 clear_interrupt(denali, irq_status);
682 /*
683 * store the status in the device context for someone
684 * to read
685 */
686 denali->irq_status |= irq_status;
687 /* notify anyone who cares that it happened */
688 complete(&denali->complete);
689 /* tell the OS that we've handled this */
690 result = IRQ_HANDLED;
691 }
692 }
693 spin_unlock(&denali->irq_lock);
694 return result;
695 }
696 #define BANK(x) ((x) << 24)
697
wait_for_irq(struct denali_nand_info * denali,uint32_t irq_mask)698 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
699 {
700 unsigned long comp_res;
701 uint32_t intr_status;
702 unsigned long timeout = msecs_to_jiffies(1000);
703
704 do {
705 comp_res =
706 wait_for_completion_timeout(&denali->complete, timeout);
707 spin_lock_irq(&denali->irq_lock);
708 intr_status = denali->irq_status;
709
710 if (intr_status & irq_mask) {
711 denali->irq_status &= ~irq_mask;
712 spin_unlock_irq(&denali->irq_lock);
713 /* our interrupt was detected */
714 break;
715 }
716
717 /*
718 * these are not the interrupts you are looking for -
719 * need to wait again
720 */
721 spin_unlock_irq(&denali->irq_lock);
722 } while (comp_res != 0);
723
724 if (comp_res == 0) {
725 /* timeout */
726 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
727 intr_status, irq_mask);
728
729 intr_status = 0;
730 }
731 return intr_status;
732 }
733
734 /*
735 * This helper function setups the registers for ECC and whether or not
736 * the spare area will be transferred.
737 */
setup_ecc_for_xfer(struct denali_nand_info * denali,bool ecc_en,bool transfer_spare)738 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
739 bool transfer_spare)
740 {
741 int ecc_en_flag, transfer_spare_flag;
742
743 /* set ECC, transfer spare bits if needed */
744 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
745 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
746
747 /* Enable spare area/ECC per user's request. */
748 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
749 iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
750 }
751
752 /*
753 * sends a pipeline command operation to the controller. See the Denali NAND
754 * controller's user guide for more information (section 4.2.3.6).
755 */
denali_send_pipeline_cmd(struct denali_nand_info * denali,bool ecc_en,bool transfer_spare,int access_type,int op)756 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
757 bool ecc_en, bool transfer_spare,
758 int access_type, int op)
759 {
760 int status = PASS;
761 uint32_t page_count = 1;
762 uint32_t addr, cmd, irq_status, irq_mask;
763
764 if (op == DENALI_READ)
765 irq_mask = INTR_STATUS__LOAD_COMP;
766 else if (op == DENALI_WRITE)
767 irq_mask = 0;
768 else
769 BUG();
770
771 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
772
773 clear_interrupts(denali);
774
775 addr = BANK(denali->flash_bank) | denali->page;
776
777 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
778 cmd = MODE_01 | addr;
779 iowrite32(cmd, denali->flash_mem);
780 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
781 /* read spare area */
782 cmd = MODE_10 | addr;
783 index_addr(denali, cmd, access_type);
784
785 cmd = MODE_01 | addr;
786 iowrite32(cmd, denali->flash_mem);
787 } else if (op == DENALI_READ) {
788 /* setup page read request for access type */
789 cmd = MODE_10 | addr;
790 index_addr(denali, cmd, access_type);
791
792 /*
793 * page 33 of the NAND controller spec indicates we should not
794 * use the pipeline commands in Spare area only mode.
795 * So we don't.
796 */
797 if (access_type == SPARE_ACCESS) {
798 cmd = MODE_01 | addr;
799 iowrite32(cmd, denali->flash_mem);
800 } else {
801 index_addr(denali, cmd,
802 PIPELINE_ACCESS | op | page_count);
803
804 /*
805 * wait for command to be accepted
806 * can always use status0 bit as the
807 * mask is identical for each bank.
808 */
809 irq_status = wait_for_irq(denali, irq_mask);
810
811 if (irq_status == 0) {
812 dev_err(denali->dev,
813 "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n",
814 cmd, denali->page, addr);
815 status = FAIL;
816 } else {
817 cmd = MODE_01 | addr;
818 iowrite32(cmd, denali->flash_mem);
819 }
820 }
821 }
822 return status;
823 }
824
825 /* helper function that simply writes a buffer to the flash */
write_data_to_flash_mem(struct denali_nand_info * denali,const uint8_t * buf,int len)826 static int write_data_to_flash_mem(struct denali_nand_info *denali,
827 const uint8_t *buf, int len)
828 {
829 uint32_t *buf32;
830 int i;
831
832 /*
833 * verify that the len is a multiple of 4.
834 * see comment in read_data_from_flash_mem()
835 */
836 BUG_ON((len % 4) != 0);
837
838 /* write the data to the flash memory */
839 buf32 = (uint32_t *)buf;
840 for (i = 0; i < len / 4; i++)
841 iowrite32(*buf32++, denali->flash_mem + 0x10);
842 return i * 4; /* intent is to return the number of bytes read */
843 }
844
845 /* helper function that simply reads a buffer from the flash */
read_data_from_flash_mem(struct denali_nand_info * denali,uint8_t * buf,int len)846 static int read_data_from_flash_mem(struct denali_nand_info *denali,
847 uint8_t *buf, int len)
848 {
849 uint32_t *buf32;
850 int i;
851
852 /*
853 * we assume that len will be a multiple of 4, if not it would be nice
854 * to know about it ASAP rather than have random failures...
855 * This assumption is based on the fact that this function is designed
856 * to be used to read flash pages, which are typically multiples of 4.
857 */
858 BUG_ON((len % 4) != 0);
859
860 /* transfer the data from the flash */
861 buf32 = (uint32_t *)buf;
862 for (i = 0; i < len / 4; i++)
863 *buf32++ = ioread32(denali->flash_mem + 0x10);
864 return i * 4; /* intent is to return the number of bytes read */
865 }
866
867 /* writes OOB data to the device */
write_oob_data(struct mtd_info * mtd,uint8_t * buf,int page)868 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
869 {
870 struct denali_nand_info *denali = mtd_to_denali(mtd);
871 uint32_t irq_status;
872 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
873 INTR_STATUS__PROGRAM_FAIL;
874 int status = 0;
875
876 denali->page = page;
877
878 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
879 DENALI_WRITE) == PASS) {
880 write_data_to_flash_mem(denali, buf, mtd->oobsize);
881
882 /* wait for operation to complete */
883 irq_status = wait_for_irq(denali, irq_mask);
884
885 if (irq_status == 0) {
886 dev_err(denali->dev, "OOB write failed\n");
887 status = -EIO;
888 }
889 } else {
890 dev_err(denali->dev, "unable to send pipeline command\n");
891 status = -EIO;
892 }
893 return status;
894 }
895
896 /* reads OOB data from the device */
read_oob_data(struct mtd_info * mtd,uint8_t * buf,int page)897 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
898 {
899 struct denali_nand_info *denali = mtd_to_denali(mtd);
900 uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
901 uint32_t irq_status, addr, cmd;
902
903 denali->page = page;
904
905 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
906 DENALI_READ) == PASS) {
907 read_data_from_flash_mem(denali, buf, mtd->oobsize);
908
909 /*
910 * wait for command to be accepted
911 * can always use status0 bit as the
912 * mask is identical for each bank.
913 */
914 irq_status = wait_for_irq(denali, irq_mask);
915
916 if (irq_status == 0)
917 dev_err(denali->dev, "page on OOB timeout %d\n",
918 denali->page);
919
920 /*
921 * We set the device back to MAIN_ACCESS here as I observed
922 * instability with the controller if you do a block erase
923 * and the last transaction was a SPARE_ACCESS. Block erase
924 * is reliable (according to the MTD test infrastructure)
925 * if you are in MAIN_ACCESS.
926 */
927 addr = BANK(denali->flash_bank) | denali->page;
928 cmd = MODE_10 | addr;
929 index_addr(denali, cmd, MAIN_ACCESS);
930 }
931 }
932
933 /*
934 * this function examines buffers to see if they contain data that
935 * indicate that the buffer is part of an erased region of flash.
936 */
is_erased(uint8_t * buf,int len)937 static bool is_erased(uint8_t *buf, int len)
938 {
939 int i;
940
941 for (i = 0; i < len; i++)
942 if (buf[i] != 0xFF)
943 return false;
944 return true;
945 }
946 #define ECC_SECTOR_SIZE 512
947
948 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
949 #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
950 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
951 #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
952 #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
953 #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
954
handle_ecc(struct denali_nand_info * denali,uint8_t * buf,uint32_t irq_status,unsigned int * max_bitflips)955 static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
956 uint32_t irq_status, unsigned int *max_bitflips)
957 {
958 bool check_erased_page = false;
959 unsigned int bitflips = 0;
960
961 if (irq_status & INTR_STATUS__ECC_ERR) {
962 /* read the ECC errors. we'll ignore them for now */
963 uint32_t err_address, err_correction_info, err_byte,
964 err_sector, err_device, err_correction_value;
965 denali_set_intr_modes(denali, false);
966
967 do {
968 err_address = ioread32(denali->flash_reg +
969 ECC_ERROR_ADDRESS);
970 err_sector = ECC_SECTOR(err_address);
971 err_byte = ECC_BYTE(err_address);
972
973 err_correction_info = ioread32(denali->flash_reg +
974 ERR_CORRECTION_INFO);
975 err_correction_value =
976 ECC_CORRECTION_VALUE(err_correction_info);
977 err_device = ECC_ERR_DEVICE(err_correction_info);
978
979 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
980 /*
981 * If err_byte is larger than ECC_SECTOR_SIZE,
982 * means error happened in OOB, so we ignore
983 * it. It's no need for us to correct it
984 * err_device is represented the NAND error
985 * bits are happened in if there are more
986 * than one NAND connected.
987 */
988 if (err_byte < ECC_SECTOR_SIZE) {
989 int offset;
990
991 offset = (err_sector *
992 ECC_SECTOR_SIZE +
993 err_byte) *
994 denali->devnum +
995 err_device;
996 /* correct the ECC error */
997 buf[offset] ^= err_correction_value;
998 denali->mtd.ecc_stats.corrected++;
999 bitflips++;
1000 }
1001 } else {
1002 /*
1003 * if the error is not correctable, need to
1004 * look at the page to see if it is an erased
1005 * page. if so, then it's not a real ECC error
1006 */
1007 check_erased_page = true;
1008 }
1009 } while (!ECC_LAST_ERR(err_correction_info));
1010 /*
1011 * Once handle all ecc errors, controller will triger
1012 * a ECC_TRANSACTION_DONE interrupt, so here just wait
1013 * for a while for this interrupt
1014 */
1015 while (!(read_interrupt_status(denali) &
1016 INTR_STATUS__ECC_TRANSACTION_DONE))
1017 cpu_relax();
1018 clear_interrupts(denali);
1019 denali_set_intr_modes(denali, true);
1020 }
1021 *max_bitflips = bitflips;
1022 return check_erased_page;
1023 }
1024
1025 /* programs the controller to either enable/disable DMA transfers */
denali_enable_dma(struct denali_nand_info * denali,bool en)1026 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
1027 {
1028 iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
1029 ioread32(denali->flash_reg + DMA_ENABLE);
1030 }
1031
1032 /* setups the HW to perform the data DMA */
denali_setup_dma(struct denali_nand_info * denali,int op)1033 static void denali_setup_dma(struct denali_nand_info *denali, int op)
1034 {
1035 uint32_t mode;
1036 const int page_count = 1;
1037 uint32_t addr = denali->buf.dma_buf;
1038
1039 mode = MODE_10 | BANK(denali->flash_bank);
1040
1041 /* DMA is a four step process */
1042
1043 /* 1. setup transfer type and # of pages */
1044 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1045
1046 /* 2. set memory high address bits 23:8 */
1047 index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
1048
1049 /* 3. set memory low address bits 23:8 */
1050 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
1051
1052 /* 4. interrupt when complete, burst len = 64 bytes */
1053 index_addr(denali, mode | 0x14000, 0x2400);
1054 }
1055
1056 /*
1057 * writes a page. user specifies type, and this function handles the
1058 * configuration details.
1059 */
write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,bool raw_xfer)1060 static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
1061 const uint8_t *buf, bool raw_xfer)
1062 {
1063 struct denali_nand_info *denali = mtd_to_denali(mtd);
1064 dma_addr_t addr = denali->buf.dma_buf;
1065 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1066 uint32_t irq_status;
1067 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1068 INTR_STATUS__PROGRAM_FAIL;
1069
1070 /*
1071 * if it is a raw xfer, we want to disable ecc and send the spare area.
1072 * !raw_xfer - enable ecc
1073 * raw_xfer - transfer spare
1074 */
1075 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1076
1077 /* copy buffer into DMA buffer */
1078 memcpy(denali->buf.buf, buf, mtd->writesize);
1079
1080 if (raw_xfer) {
1081 /* transfer the data to the spare area */
1082 memcpy(denali->buf.buf + mtd->writesize,
1083 chip->oob_poi,
1084 mtd->oobsize);
1085 }
1086
1087 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
1088
1089 clear_interrupts(denali);
1090 denali_enable_dma(denali, true);
1091
1092 denali_setup_dma(denali, DENALI_WRITE);
1093
1094 /* wait for operation to complete */
1095 irq_status = wait_for_irq(denali, irq_mask);
1096
1097 if (irq_status == 0) {
1098 dev_err(denali->dev, "timeout on write_page (type = %d)\n",
1099 raw_xfer);
1100 denali->status = NAND_STATUS_FAIL;
1101 }
1102
1103 denali_enable_dma(denali, false);
1104 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
1105
1106 return 0;
1107 }
1108
1109 /* NAND core entry points */
1110
1111 /*
1112 * this is the callback that the NAND core calls to write a page. Since
1113 * writing a page with ECC or without is similar, all the work is done
1114 * by write_page above.
1115 */
denali_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)1116 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1117 const uint8_t *buf, int oob_required, int page)
1118 {
1119 /*
1120 * for regular page writes, we let HW handle all the ECC
1121 * data written to the device.
1122 */
1123 return write_page(mtd, chip, buf, false);
1124 }
1125
1126 /*
1127 * This is the callback that the NAND core calls to write a page without ECC.
1128 * raw access is similar to ECC page writes, so all the work is done in the
1129 * write_page() function above.
1130 */
denali_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)1131 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1132 const uint8_t *buf, int oob_required,
1133 int page)
1134 {
1135 /*
1136 * for raw page writes, we want to disable ECC and simply write
1137 * whatever data is in the buffer.
1138 */
1139 return write_page(mtd, chip, buf, true);
1140 }
1141
denali_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)1142 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1143 int page)
1144 {
1145 return write_oob_data(mtd, chip->oob_poi, page);
1146 }
1147
denali_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)1148 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1149 int page)
1150 {
1151 read_oob_data(mtd, chip->oob_poi, page);
1152
1153 return 0;
1154 }
1155
denali_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1156 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1157 uint8_t *buf, int oob_required, int page)
1158 {
1159 unsigned int max_bitflips;
1160 struct denali_nand_info *denali = mtd_to_denali(mtd);
1161
1162 dma_addr_t addr = denali->buf.dma_buf;
1163 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1164
1165 uint32_t irq_status;
1166 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1167 INTR_STATUS__ECC_ERR;
1168 bool check_erased_page = false;
1169
1170 if (page != denali->page) {
1171 dev_err(denali->dev,
1172 "IN %s: page %d is not equal to denali->page %d",
1173 __func__, page, denali->page);
1174 BUG();
1175 }
1176
1177 setup_ecc_for_xfer(denali, true, false);
1178
1179 denali_enable_dma(denali, true);
1180 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1181
1182 clear_interrupts(denali);
1183 denali_setup_dma(denali, DENALI_READ);
1184
1185 /* wait for operation to complete */
1186 irq_status = wait_for_irq(denali, irq_mask);
1187
1188 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1189
1190 memcpy(buf, denali->buf.buf, mtd->writesize);
1191
1192 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
1193 denali_enable_dma(denali, false);
1194
1195 if (check_erased_page) {
1196 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1197
1198 /* check ECC failures that may have occurred on erased pages */
1199 if (check_erased_page) {
1200 if (!is_erased(buf, denali->mtd.writesize))
1201 denali->mtd.ecc_stats.failed++;
1202 if (!is_erased(buf, denali->mtd.oobsize))
1203 denali->mtd.ecc_stats.failed++;
1204 }
1205 }
1206 return max_bitflips;
1207 }
1208
denali_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1209 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1210 uint8_t *buf, int oob_required, int page)
1211 {
1212 struct denali_nand_info *denali = mtd_to_denali(mtd);
1213 dma_addr_t addr = denali->buf.dma_buf;
1214 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1215 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
1216
1217 if (page != denali->page) {
1218 dev_err(denali->dev,
1219 "IN %s: page %d is not equal to denali->page %d",
1220 __func__, page, denali->page);
1221 BUG();
1222 }
1223
1224 setup_ecc_for_xfer(denali, false, true);
1225 denali_enable_dma(denali, true);
1226
1227 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1228
1229 clear_interrupts(denali);
1230 denali_setup_dma(denali, DENALI_READ);
1231
1232 /* wait for operation to complete */
1233 wait_for_irq(denali, irq_mask);
1234
1235 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1236
1237 denali_enable_dma(denali, false);
1238
1239 memcpy(buf, denali->buf.buf, mtd->writesize);
1240 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1241
1242 return 0;
1243 }
1244
denali_read_byte(struct mtd_info * mtd)1245 static uint8_t denali_read_byte(struct mtd_info *mtd)
1246 {
1247 struct denali_nand_info *denali = mtd_to_denali(mtd);
1248 uint8_t result = 0xff;
1249
1250 if (denali->buf.head < denali->buf.tail)
1251 result = denali->buf.buf[denali->buf.head++];
1252
1253 return result;
1254 }
1255
denali_select_chip(struct mtd_info * mtd,int chip)1256 static void denali_select_chip(struct mtd_info *mtd, int chip)
1257 {
1258 struct denali_nand_info *denali = mtd_to_denali(mtd);
1259
1260 spin_lock_irq(&denali->irq_lock);
1261 denali->flash_bank = chip;
1262 spin_unlock_irq(&denali->irq_lock);
1263 }
1264
denali_waitfunc(struct mtd_info * mtd,struct nand_chip * chip)1265 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1266 {
1267 struct denali_nand_info *denali = mtd_to_denali(mtd);
1268 int status = denali->status;
1269
1270 denali->status = 0;
1271
1272 return status;
1273 }
1274
denali_erase(struct mtd_info * mtd,int page)1275 static int denali_erase(struct mtd_info *mtd, int page)
1276 {
1277 struct denali_nand_info *denali = mtd_to_denali(mtd);
1278
1279 uint32_t cmd, irq_status;
1280
1281 clear_interrupts(denali);
1282
1283 /* setup page read request for access type */
1284 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1285 index_addr(denali, cmd, 0x1);
1286
1287 /* wait for erase to complete or failure to occur */
1288 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1289 INTR_STATUS__ERASE_FAIL);
1290
1291 return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS;
1292 }
1293
denali_cmdfunc(struct mtd_info * mtd,unsigned int cmd,int col,int page)1294 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1295 int page)
1296 {
1297 struct denali_nand_info *denali = mtd_to_denali(mtd);
1298 uint32_t addr, id;
1299 int i;
1300
1301 switch (cmd) {
1302 case NAND_CMD_PAGEPROG:
1303 break;
1304 case NAND_CMD_STATUS:
1305 read_status(denali);
1306 break;
1307 case NAND_CMD_READID:
1308 case NAND_CMD_PARAM:
1309 reset_buf(denali);
1310 /*
1311 * sometimes ManufactureId read from register is not right
1312 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1313 * So here we send READID cmd to NAND insteand
1314 */
1315 addr = MODE_11 | BANK(denali->flash_bank);
1316 index_addr(denali, addr | 0, 0x90);
1317 index_addr(denali, addr | 1, col);
1318 for (i = 0; i < 8; i++) {
1319 index_addr_read_data(denali, addr | 2, &id);
1320 write_byte_to_buf(denali, id);
1321 }
1322 break;
1323 case NAND_CMD_READ0:
1324 case NAND_CMD_SEQIN:
1325 denali->page = page;
1326 break;
1327 case NAND_CMD_RESET:
1328 reset_bank(denali);
1329 break;
1330 case NAND_CMD_READOOB:
1331 /* TODO: Read OOB data */
1332 break;
1333 default:
1334 pr_err(": unsupported command received 0x%x\n", cmd);
1335 break;
1336 }
1337 }
1338 /* end NAND core entry points */
1339
1340 /* Initialization code to bring the device up to a known good state */
denali_hw_init(struct denali_nand_info * denali)1341 static void denali_hw_init(struct denali_nand_info *denali)
1342 {
1343 /*
1344 * tell driver how many bit controller will skip before
1345 * writing ECC code in OOB, this register may be already
1346 * set by firmware. So we read this value out.
1347 * if this value is 0, just let it be.
1348 */
1349 denali->bbtskipbytes = ioread32(denali->flash_reg +
1350 SPARE_AREA_SKIP_BYTES);
1351 detect_max_banks(denali);
1352 denali_nand_reset(denali);
1353 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1354 iowrite32(CHIP_EN_DONT_CARE__FLAG,
1355 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1356
1357 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1358
1359 /* Should set value for these registers when init */
1360 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1361 iowrite32(1, denali->flash_reg + ECC_ENABLE);
1362 denali_nand_timing_set(denali);
1363 denali_irq_init(denali);
1364 }
1365
1366 /*
1367 * Althogh controller spec said SLC ECC is forceb to be 4bit,
1368 * but denali controller in MRST only support 15bit and 8bit ECC
1369 * correction
1370 */
1371 #define ECC_8BITS 14
1372 static struct nand_ecclayout nand_8bit_oob = {
1373 .eccbytes = 14,
1374 };
1375
1376 #define ECC_15BITS 26
1377 static struct nand_ecclayout nand_15bit_oob = {
1378 .eccbytes = 26,
1379 };
1380
1381 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1382 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1383
1384 static struct nand_bbt_descr bbt_main_descr = {
1385 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1386 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1387 .offs = 8,
1388 .len = 4,
1389 .veroffs = 12,
1390 .maxblocks = 4,
1391 .pattern = bbt_pattern,
1392 };
1393
1394 static struct nand_bbt_descr bbt_mirror_descr = {
1395 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1396 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1397 .offs = 8,
1398 .len = 4,
1399 .veroffs = 12,
1400 .maxblocks = 4,
1401 .pattern = mirror_pattern,
1402 };
1403
1404 /* initialize driver data structures */
denali_drv_init(struct denali_nand_info * denali)1405 static void denali_drv_init(struct denali_nand_info *denali)
1406 {
1407 denali->idx = 0;
1408
1409 /* setup interrupt handler */
1410 /*
1411 * the completion object will be used to notify
1412 * the callee that the interrupt is done
1413 */
1414 init_completion(&denali->complete);
1415
1416 /*
1417 * the spinlock will be used to synchronize the ISR with any
1418 * element that might be access shared data (interrupt status)
1419 */
1420 spin_lock_init(&denali->irq_lock);
1421
1422 /* indicate that MTD has not selected a valid bank yet */
1423 denali->flash_bank = CHIP_SELECT_INVALID;
1424
1425 /* initialize our irq_status variable to indicate no interrupts */
1426 denali->irq_status = 0;
1427 }
1428
denali_init(struct denali_nand_info * denali)1429 int denali_init(struct denali_nand_info *denali)
1430 {
1431 int ret;
1432
1433 if (denali->platform == INTEL_CE4100) {
1434 /*
1435 * Due to a silicon limitation, we can only support
1436 * ONFI timing mode 1 and below.
1437 */
1438 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1439 pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1440 return -EINVAL;
1441 }
1442 }
1443
1444 /* allocate a temporary buffer for nand_scan_ident() */
1445 denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
1446 GFP_DMA | GFP_KERNEL);
1447 if (!denali->buf.buf)
1448 return -ENOMEM;
1449
1450 denali->mtd.dev.parent = denali->dev;
1451 denali_hw_init(denali);
1452 denali_drv_init(denali);
1453
1454 /*
1455 * denali_isr register is done after all the hardware
1456 * initilization is finished
1457 */
1458 if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
1459 DENALI_NAND_NAME, denali)) {
1460 pr_err("Spectra: Unable to allocate IRQ\n");
1461 return -ENODEV;
1462 }
1463
1464 /* now that our ISR is registered, we can enable interrupts */
1465 denali_set_intr_modes(denali, true);
1466 denali->mtd.name = "denali-nand";
1467 denali->mtd.priv = &denali->nand;
1468
1469 /* register the driver with the NAND core subsystem */
1470 denali->nand.select_chip = denali_select_chip;
1471 denali->nand.cmdfunc = denali_cmdfunc;
1472 denali->nand.read_byte = denali_read_byte;
1473 denali->nand.waitfunc = denali_waitfunc;
1474
1475 /*
1476 * scan for NAND devices attached to the controller
1477 * this is the first stage in a two step process to register
1478 * with the nand subsystem
1479 */
1480 if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
1481 ret = -ENXIO;
1482 goto failed_req_irq;
1483 }
1484
1485 /* allocate the right size buffer now */
1486 devm_kfree(denali->dev, denali->buf.buf);
1487 denali->buf.buf = devm_kzalloc(denali->dev,
1488 denali->mtd.writesize + denali->mtd.oobsize,
1489 GFP_KERNEL);
1490 if (!denali->buf.buf) {
1491 ret = -ENOMEM;
1492 goto failed_req_irq;
1493 }
1494
1495 /* Is 32-bit DMA supported? */
1496 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
1497 if (ret) {
1498 pr_err("Spectra: no usable DMA configuration\n");
1499 goto failed_req_irq;
1500 }
1501
1502 denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
1503 denali->mtd.writesize + denali->mtd.oobsize,
1504 DMA_BIDIRECTIONAL);
1505 if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
1506 dev_err(denali->dev, "Spectra: failed to map DMA buffer\n");
1507 ret = -EIO;
1508 goto failed_req_irq;
1509 }
1510
1511 /*
1512 * support for multi nand
1513 * MTD known nothing about multi nand, so we should tell it
1514 * the real pagesize and anything necessery
1515 */
1516 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1517 denali->nand.chipsize <<= (denali->devnum - 1);
1518 denali->nand.page_shift += (denali->devnum - 1);
1519 denali->nand.pagemask = (denali->nand.chipsize >>
1520 denali->nand.page_shift) - 1;
1521 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1522 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1523 denali->nand.chip_shift += (denali->devnum - 1);
1524 denali->mtd.writesize <<= (denali->devnum - 1);
1525 denali->mtd.oobsize <<= (denali->devnum - 1);
1526 denali->mtd.erasesize <<= (denali->devnum - 1);
1527 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
1528 denali->bbtskipbytes *= denali->devnum;
1529
1530 /*
1531 * second stage of the NAND scan
1532 * this stage requires information regarding ECC and
1533 * bad block management.
1534 */
1535
1536 /* Bad block management */
1537 denali->nand.bbt_td = &bbt_main_descr;
1538 denali->nand.bbt_md = &bbt_mirror_descr;
1539
1540 /* skip the scan for now until we have OOB read and write support */
1541 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
1542 denali->nand.options |= NAND_SKIP_BBTSCAN;
1543 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1544
1545 /* no subpage writes on denali */
1546 denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1547
1548 /*
1549 * Denali Controller only support 15bit and 8bit ECC in MRST,
1550 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1551 * SLC if possible.
1552 * */
1553 if (!nand_is_slc(&denali->nand) &&
1554 (denali->mtd.oobsize > (denali->bbtskipbytes +
1555 ECC_15BITS * (denali->mtd.writesize /
1556 ECC_SECTOR_SIZE)))) {
1557 /* if MLC OOB size is large enough, use 15bit ECC*/
1558 denali->nand.ecc.strength = 15;
1559 denali->nand.ecc.layout = &nand_15bit_oob;
1560 denali->nand.ecc.bytes = ECC_15BITS;
1561 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
1562 } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1563 ECC_8BITS * (denali->mtd.writesize /
1564 ECC_SECTOR_SIZE))) {
1565 pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
1566 goto failed_req_irq;
1567 } else {
1568 denali->nand.ecc.strength = 8;
1569 denali->nand.ecc.layout = &nand_8bit_oob;
1570 denali->nand.ecc.bytes = ECC_8BITS;
1571 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1572 }
1573
1574 denali->nand.ecc.bytes *= denali->devnum;
1575 denali->nand.ecc.strength *= denali->devnum;
1576 denali->nand.ecc.layout->eccbytes *=
1577 denali->mtd.writesize / ECC_SECTOR_SIZE;
1578 denali->nand.ecc.layout->oobfree[0].offset =
1579 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1580 denali->nand.ecc.layout->oobfree[0].length =
1581 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
1582 denali->bbtskipbytes;
1583
1584 /*
1585 * Let driver know the total blocks number and how many blocks
1586 * contained by each nand chip. blksperchip will help driver to
1587 * know how many blocks is taken by FW.
1588 */
1589 denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift;
1590 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1591
1592 /* override the default read operations */
1593 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
1594 denali->nand.ecc.read_page = denali_read_page;
1595 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1596 denali->nand.ecc.write_page = denali_write_page;
1597 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1598 denali->nand.ecc.read_oob = denali_read_oob;
1599 denali->nand.ecc.write_oob = denali_write_oob;
1600 denali->nand.erase = denali_erase;
1601
1602 if (nand_scan_tail(&denali->mtd)) {
1603 ret = -ENXIO;
1604 goto failed_req_irq;
1605 }
1606
1607 ret = mtd_device_register(&denali->mtd, NULL, 0);
1608 if (ret) {
1609 dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n",
1610 ret);
1611 goto failed_req_irq;
1612 }
1613 return 0;
1614
1615 failed_req_irq:
1616 denali_irq_cleanup(denali->irq, denali);
1617
1618 return ret;
1619 }
1620 EXPORT_SYMBOL(denali_init);
1621
1622 /* driver exit point */
denali_remove(struct denali_nand_info * denali)1623 void denali_remove(struct denali_nand_info *denali)
1624 {
1625 /*
1626 * Pre-compute DMA buffer size to avoid any problems in case
1627 * nand_release() ever changes in a way that mtd->writesize and
1628 * mtd->oobsize are not reliable after this call.
1629 */
1630 int bufsize = denali->mtd.writesize + denali->mtd.oobsize;
1631
1632 nand_release(&denali->mtd);
1633 denali_irq_cleanup(denali->irq, denali);
1634 dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize,
1635 DMA_BIDIRECTIONAL);
1636 }
1637 EXPORT_SYMBOL(denali_remove);
1638