1 /*
2 * Copyright © 2012 Mike Dunn <mikedunn@newsguy.com>
3 *
4 * mtd nand driver for M-Systems DiskOnChip G4
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * Tested on the Palm Treo 680. The G4 is also present on Toshiba Portege, Asus
12 * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
13 * Should work on these as well. Let me know!
14 *
15 * TODO:
16 *
17 * Mechanism for management of password-protected areas
18 *
19 * Hamming ecc when reading oob only
20 *
21 * According to the M-Sys documentation, this device is also available in a
22 * "dual-die" configuration having a 256MB capacity, but no mechanism for
23 * detecting this variant is documented. Currently this driver assumes 128MB
24 * capacity.
25 *
26 * Support for multiple cascaded devices ("floors"). Not sure which gadgets
27 * contain multiple G4s in a cascaded configuration, if any.
28 *
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/string.h>
35 #include <linux/sched.h>
36 #include <linux/delay.h>
37 #include <linux/module.h>
38 #include <linux/export.h>
39 #include <linux/platform_device.h>
40 #include <linux/io.h>
41 #include <linux/bitops.h>
42 #include <linux/mtd/partitions.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/bch.h>
46 #include <linux/bitrev.h>
47 #include <linux/jiffies.h>
48
49 /*
50 * In "reliable mode" consecutive 2k pages are used in parallel (in some
51 * fashion) to store the same data. The data can be read back from the
52 * even-numbered pages in the normal manner; odd-numbered pages will appear to
53 * contain junk. Systems that boot from the docg4 typically write the secondary
54 * program loader (SPL) code in this mode. The SPL is loaded by the initial
55 * program loader (IPL, stored in the docg4's 2k NOR-like region that is mapped
56 * to the reset vector address). This module parameter enables you to use this
57 * driver to write the SPL. When in this mode, no more than 2k of data can be
58 * written at a time, because the addresses do not increment in the normal
59 * manner, and the starting offset must be within an even-numbered 2k region;
60 * i.e., invalid starting offsets are 0x800, 0xa00, 0xc00, 0xe00, 0x1800,
61 * 0x1a00, ... Reliable mode is a special case and should not be used unless
62 * you know what you're doing.
63 */
64 static bool reliable_mode;
65 module_param(reliable_mode, bool, 0);
66 MODULE_PARM_DESC(reliable_mode, "pages are programmed in reliable mode");
67
68 /*
69 * You'll want to ignore badblocks if you're reading a partition that contains
70 * data written by the TrueFFS library (i.e., by PalmOS, Windows, etc), since
71 * it does not use mtd nand's method for marking bad blocks (using oob area).
72 * This will also skip the check of the "page written" flag.
73 */
74 static bool ignore_badblocks;
75 module_param(ignore_badblocks, bool, 0);
76 MODULE_PARM_DESC(ignore_badblocks, "no badblock checking performed");
77
78 struct docg4_priv {
79 struct mtd_info *mtd;
80 struct device *dev;
81 void __iomem *virtadr;
82 int status;
83 struct {
84 unsigned int command;
85 int column;
86 int page;
87 } last_command;
88 uint8_t oob_buf[16];
89 uint8_t ecc_buf[7];
90 int oob_page;
91 struct bch_control *bch;
92 };
93
94 /*
95 * Defines prefixed with DOCG4 are unique to the diskonchip G4. All others are
96 * shared with other diskonchip devices (P3, G3 at least).
97 *
98 * Functions with names prefixed with docg4_ are mtd / nand interface functions
99 * (though they may also be called internally). All others are internal.
100 */
101
102 #define DOC_IOSPACE_DATA 0x0800
103
104 /* register offsets */
105 #define DOC_CHIPID 0x1000
106 #define DOC_DEVICESELECT 0x100a
107 #define DOC_ASICMODE 0x100c
108 #define DOC_DATAEND 0x101e
109 #define DOC_NOP 0x103e
110
111 #define DOC_FLASHSEQUENCE 0x1032
112 #define DOC_FLASHCOMMAND 0x1034
113 #define DOC_FLASHADDRESS 0x1036
114 #define DOC_FLASHCONTROL 0x1038
115 #define DOC_ECCCONF0 0x1040
116 #define DOC_ECCCONF1 0x1042
117 #define DOC_HAMMINGPARITY 0x1046
118 #define DOC_BCH_SYNDROM(idx) (0x1048 + idx)
119
120 #define DOC_ASICMODECONFIRM 0x1072
121 #define DOC_CHIPID_INV 0x1074
122 #define DOC_POWERMODE 0x107c
123
124 #define DOCG4_MYSTERY_REG 0x1050
125
126 /* apparently used only to write oob bytes 6 and 7 */
127 #define DOCG4_OOB_6_7 0x1052
128
129 /* DOC_FLASHSEQUENCE register commands */
130 #define DOC_SEQ_RESET 0x00
131 #define DOCG4_SEQ_PAGE_READ 0x03
132 #define DOCG4_SEQ_FLUSH 0x29
133 #define DOCG4_SEQ_PAGEWRITE 0x16
134 #define DOCG4_SEQ_PAGEPROG 0x1e
135 #define DOCG4_SEQ_BLOCKERASE 0x24
136 #define DOCG4_SEQ_SETMODE 0x45
137
138 /* DOC_FLASHCOMMAND register commands */
139 #define DOCG4_CMD_PAGE_READ 0x00
140 #define DOC_CMD_ERASECYCLE2 0xd0
141 #define DOCG4_CMD_FLUSH 0x70
142 #define DOCG4_CMD_READ2 0x30
143 #define DOC_CMD_PROG_BLOCK_ADDR 0x60
144 #define DOCG4_CMD_PAGEWRITE 0x80
145 #define DOC_CMD_PROG_CYCLE2 0x10
146 #define DOCG4_CMD_FAST_MODE 0xa3 /* functionality guessed */
147 #define DOC_CMD_RELIABLE_MODE 0x22
148 #define DOC_CMD_RESET 0xff
149
150 /* DOC_POWERMODE register bits */
151 #define DOC_POWERDOWN_READY 0x80
152
153 /* DOC_FLASHCONTROL register bits */
154 #define DOC_CTRL_CE 0x10
155 #define DOC_CTRL_UNKNOWN 0x40
156 #define DOC_CTRL_FLASHREADY 0x01
157
158 /* DOC_ECCCONF0 register bits */
159 #define DOC_ECCCONF0_READ_MODE 0x8000
160 #define DOC_ECCCONF0_UNKNOWN 0x2000
161 #define DOC_ECCCONF0_ECC_ENABLE 0x1000
162 #define DOC_ECCCONF0_DATA_BYTES_MASK 0x07ff
163
164 /* DOC_ECCCONF1 register bits */
165 #define DOC_ECCCONF1_BCH_SYNDROM_ERR 0x80
166 #define DOC_ECCCONF1_ECC_ENABLE 0x07
167 #define DOC_ECCCONF1_PAGE_IS_WRITTEN 0x20
168
169 /* DOC_ASICMODE register bits */
170 #define DOC_ASICMODE_RESET 0x00
171 #define DOC_ASICMODE_NORMAL 0x01
172 #define DOC_ASICMODE_POWERDOWN 0x02
173 #define DOC_ASICMODE_MDWREN 0x04
174 #define DOC_ASICMODE_BDETCT_RESET 0x08
175 #define DOC_ASICMODE_RSTIN_RESET 0x10
176 #define DOC_ASICMODE_RAM_WE 0x20
177
178 /* good status values read after read/write/erase operations */
179 #define DOCG4_PROGSTATUS_GOOD 0x51
180 #define DOCG4_PROGSTATUS_GOOD_2 0xe0
181
182 /*
183 * On read operations (page and oob-only), the first byte read from I/O reg is a
184 * status. On error, it reads 0x73; otherwise, it reads either 0x71 (first read
185 * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
186 */
187 #define DOCG4_READ_ERROR 0x02 /* bit 1 indicates read error */
188
189 /* anatomy of the device */
190 #define DOCG4_CHIP_SIZE 0x8000000
191 #define DOCG4_PAGE_SIZE 0x200
192 #define DOCG4_PAGES_PER_BLOCK 0x200
193 #define DOCG4_BLOCK_SIZE (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
194 #define DOCG4_NUMBLOCKS (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
195 #define DOCG4_OOB_SIZE 0x10
196 #define DOCG4_CHIP_SHIFT 27 /* log_2(DOCG4_CHIP_SIZE) */
197 #define DOCG4_PAGE_SHIFT 9 /* log_2(DOCG4_PAGE_SIZE) */
198 #define DOCG4_ERASE_SHIFT 18 /* log_2(DOCG4_BLOCK_SIZE) */
199
200 /* all but the last byte is included in ecc calculation */
201 #define DOCG4_BCH_SIZE (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
202
203 #define DOCG4_USERDATA_LEN 520 /* 512 byte page plus 8 oob avail to user */
204
205 /* expected values from the ID registers */
206 #define DOCG4_IDREG1_VALUE 0x0400
207 #define DOCG4_IDREG2_VALUE 0xfbff
208
209 /* primitive polynomial used to build the Galois field used by hw ecc gen */
210 #define DOCG4_PRIMITIVE_POLY 0x4443
211
212 #define DOCG4_M 14 /* Galois field is of order 2^14 */
213 #define DOCG4_T 4 /* BCH alg corrects up to 4 bit errors */
214
215 #define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
216 #define DOCG4_REDUNDANT_BBT_PAGE 24 /* page where redundant factory bbt lives */
217
218 /*
219 * Bytes 0, 1 are used as badblock marker.
220 * Bytes 2 - 6 are available to the user.
221 * Byte 7 is hamming ecc for first 7 oob bytes only.
222 * Bytes 8 - 14 are hw-generated ecc covering entire page + oob bytes 0 - 14.
223 * Byte 15 (the last) is used by the driver as a "page written" flag.
224 */
225 static struct nand_ecclayout docg4_oobinfo = {
226 .eccbytes = 9,
227 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
228 .oobavail = 5,
229 .oobfree = { {.offset = 2, .length = 5} }
230 };
231
232 /*
233 * The device has a nop register which M-Sys claims is for the purpose of
234 * inserting precise delays. But beware; at least some operations fail if the
235 * nop writes are replaced with a generic delay!
236 */
write_nop(void __iomem * docptr)237 static inline void write_nop(void __iomem *docptr)
238 {
239 writew(0, docptr + DOC_NOP);
240 }
241
docg4_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)242 static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
243 {
244 int i;
245 struct nand_chip *nand = mtd->priv;
246 uint16_t *p = (uint16_t *) buf;
247 len >>= 1;
248
249 for (i = 0; i < len; i++)
250 p[i] = readw(nand->IO_ADDR_R);
251 }
252
docg4_write_buf16(struct mtd_info * mtd,const uint8_t * buf,int len)253 static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
254 {
255 int i;
256 struct nand_chip *nand = mtd->priv;
257 uint16_t *p = (uint16_t *) buf;
258 len >>= 1;
259
260 for (i = 0; i < len; i++)
261 writew(p[i], nand->IO_ADDR_W);
262 }
263
poll_status(struct docg4_priv * doc)264 static int poll_status(struct docg4_priv *doc)
265 {
266 /*
267 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
268 * register. Operations known to take a long time (e.g., block erase)
269 * should sleep for a while before calling this.
270 */
271
272 uint16_t flash_status;
273 unsigned long timeo;
274 void __iomem *docptr = doc->virtadr;
275
276 dev_dbg(doc->dev, "%s...\n", __func__);
277
278 /* hardware quirk requires reading twice initially */
279 flash_status = readw(docptr + DOC_FLASHCONTROL);
280
281 timeo = jiffies + msecs_to_jiffies(200); /* generous timeout */
282 do {
283 cpu_relax();
284 flash_status = readb(docptr + DOC_FLASHCONTROL);
285 } while (!(flash_status & DOC_CTRL_FLASHREADY) &&
286 time_before(jiffies, timeo));
287
288 if (unlikely(!(flash_status & DOC_CTRL_FLASHREADY))) {
289 dev_err(doc->dev, "%s: timed out!\n", __func__);
290 return NAND_STATUS_FAIL;
291 }
292
293 return 0;
294 }
295
296
docg4_wait(struct mtd_info * mtd,struct nand_chip * nand)297 static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
298 {
299
300 struct docg4_priv *doc = nand->priv;
301 int status = NAND_STATUS_WP; /* inverse logic?? */
302 dev_dbg(doc->dev, "%s...\n", __func__);
303
304 /* report any previously unreported error */
305 if (doc->status) {
306 status |= doc->status;
307 doc->status = 0;
308 return status;
309 }
310
311 status |= poll_status(doc);
312 return status;
313 }
314
docg4_select_chip(struct mtd_info * mtd,int chip)315 static void docg4_select_chip(struct mtd_info *mtd, int chip)
316 {
317 /*
318 * Select among multiple cascaded chips ("floors"). Multiple floors are
319 * not yet supported, so the only valid non-negative value is 0.
320 */
321 struct nand_chip *nand = mtd->priv;
322 struct docg4_priv *doc = nand->priv;
323 void __iomem *docptr = doc->virtadr;
324
325 dev_dbg(doc->dev, "%s: chip %d\n", __func__, chip);
326
327 if (chip < 0)
328 return; /* deselected */
329
330 if (chip > 0)
331 dev_warn(doc->dev, "multiple floors currently unsupported\n");
332
333 writew(0, docptr + DOC_DEVICESELECT);
334 }
335
reset(struct mtd_info * mtd)336 static void reset(struct mtd_info *mtd)
337 {
338 /* full device reset */
339
340 struct nand_chip *nand = mtd->priv;
341 struct docg4_priv *doc = nand->priv;
342 void __iomem *docptr = doc->virtadr;
343
344 writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN,
345 docptr + DOC_ASICMODE);
346 writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
347 docptr + DOC_ASICMODECONFIRM);
348 write_nop(docptr);
349
350 writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
351 docptr + DOC_ASICMODE);
352 writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
353 docptr + DOC_ASICMODECONFIRM);
354
355 writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
356
357 poll_status(doc);
358 }
359
read_hw_ecc(void __iomem * docptr,uint8_t * ecc_buf)360 static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
361 {
362 /* read the 7 hw-generated ecc bytes */
363
364 int i;
365 for (i = 0; i < 7; i++) { /* hw quirk; read twice */
366 ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
367 ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
368 }
369 }
370
correct_data(struct mtd_info * mtd,uint8_t * buf,int page)371 static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
372 {
373 /*
374 * Called after a page read when hardware reports bitflips.
375 * Up to four bitflips can be corrected.
376 */
377
378 struct nand_chip *nand = mtd->priv;
379 struct docg4_priv *doc = nand->priv;
380 void __iomem *docptr = doc->virtadr;
381 int i, numerrs, errpos[4];
382 const uint8_t blank_read_hwecc[8] = {
383 0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
384
385 read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
386
387 /* check if read error is due to a blank page */
388 if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
389 return 0; /* yes */
390
391 /* skip additional check of "written flag" if ignore_badblocks */
392 if (ignore_badblocks == false) {
393
394 /*
395 * If the hw ecc bytes are not those of a blank page, there's
396 * still a chance that the page is blank, but was read with
397 * errors. Check the "written flag" in last oob byte, which
398 * is set to zero when a page is written. If more than half
399 * the bits are set, assume a blank page. Unfortunately, the
400 * bit flips(s) are not reported in stats.
401 */
402
403 if (nand->oob_poi[15]) {
404 int bit, numsetbits = 0;
405 unsigned long written_flag = nand->oob_poi[15];
406 for_each_set_bit(bit, &written_flag, 8)
407 numsetbits++;
408 if (numsetbits > 4) { /* assume blank */
409 dev_warn(doc->dev,
410 "error(s) in blank page "
411 "at offset %08x\n",
412 page * DOCG4_PAGE_SIZE);
413 return 0;
414 }
415 }
416 }
417
418 /*
419 * The hardware ecc unit produces oob_ecc ^ calc_ecc. The kernel's bch
420 * algorithm is used to decode this. However the hw operates on page
421 * data in a bit order that is the reverse of that of the bch alg,
422 * requiring that the bits be reversed on the result. Thanks to Ivan
423 * Djelic for his analysis!
424 */
425 for (i = 0; i < 7; i++)
426 doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
427
428 numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
429 doc->ecc_buf, NULL, errpos);
430
431 if (numerrs == -EBADMSG) {
432 dev_warn(doc->dev, "uncorrectable errors at offset %08x\n",
433 page * DOCG4_PAGE_SIZE);
434 return -EBADMSG;
435 }
436
437 BUG_ON(numerrs < 0); /* -EINVAL, or anything other than -EBADMSG */
438
439 /* undo last step in BCH alg (modulo mirroring not needed) */
440 for (i = 0; i < numerrs; i++)
441 errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
442
443 /* fix the errors */
444 for (i = 0; i < numerrs; i++) {
445
446 /* ignore if error within oob ecc bytes */
447 if (errpos[i] > DOCG4_USERDATA_LEN * 8)
448 continue;
449
450 /* if error within oob area preceeding ecc bytes... */
451 if (errpos[i] > DOCG4_PAGE_SIZE * 8)
452 change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
453 (unsigned long *)nand->oob_poi);
454
455 else /* error in page data */
456 change_bit(errpos[i], (unsigned long *)buf);
457 }
458
459 dev_notice(doc->dev, "%d error(s) corrected at offset %08x\n",
460 numerrs, page * DOCG4_PAGE_SIZE);
461
462 return numerrs;
463 }
464
docg4_read_byte(struct mtd_info * mtd)465 static uint8_t docg4_read_byte(struct mtd_info *mtd)
466 {
467 struct nand_chip *nand = mtd->priv;
468 struct docg4_priv *doc = nand->priv;
469
470 dev_dbg(doc->dev, "%s\n", __func__);
471
472 if (doc->last_command.command == NAND_CMD_STATUS) {
473 int status;
474
475 /*
476 * Previous nand command was status request, so nand
477 * infrastructure code expects to read the status here. If an
478 * error occurred in a previous operation, report it.
479 */
480 doc->last_command.command = 0;
481
482 if (doc->status) {
483 status = doc->status;
484 doc->status = 0;
485 }
486
487 /* why is NAND_STATUS_WP inverse logic?? */
488 else
489 status = NAND_STATUS_WP | NAND_STATUS_READY;
490
491 return status;
492 }
493
494 dev_warn(doc->dev, "unexpected call to read_byte()\n");
495
496 return 0;
497 }
498
write_addr(struct docg4_priv * doc,uint32_t docg4_addr)499 static void write_addr(struct docg4_priv *doc, uint32_t docg4_addr)
500 {
501 /* write the four address bytes packed in docg4_addr to the device */
502
503 void __iomem *docptr = doc->virtadr;
504 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
505 docg4_addr >>= 8;
506 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
507 docg4_addr >>= 8;
508 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
509 docg4_addr >>= 8;
510 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
511 }
512
read_progstatus(struct docg4_priv * doc)513 static int read_progstatus(struct docg4_priv *doc)
514 {
515 /*
516 * This apparently checks the status of programming. Done after an
517 * erasure, and after page data is written. On error, the status is
518 * saved, to be later retrieved by the nand infrastructure code.
519 */
520 void __iomem *docptr = doc->virtadr;
521
522 /* status is read from the I/O reg */
523 uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
524 uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
525 uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
526
527 dev_dbg(doc->dev, "docg4: %s: %02x %02x %02x\n",
528 __func__, status1, status2, status3);
529
530 if (status1 != DOCG4_PROGSTATUS_GOOD
531 || status2 != DOCG4_PROGSTATUS_GOOD_2
532 || status3 != DOCG4_PROGSTATUS_GOOD_2) {
533 doc->status = NAND_STATUS_FAIL;
534 dev_warn(doc->dev, "read_progstatus failed: "
535 "%02x, %02x, %02x\n", status1, status2, status3);
536 return -EIO;
537 }
538 return 0;
539 }
540
pageprog(struct mtd_info * mtd)541 static int pageprog(struct mtd_info *mtd)
542 {
543 /*
544 * Final step in writing a page. Writes the contents of its
545 * internal buffer out to the flash array, or some such.
546 */
547
548 struct nand_chip *nand = mtd->priv;
549 struct docg4_priv *doc = nand->priv;
550 void __iomem *docptr = doc->virtadr;
551 int retval = 0;
552
553 dev_dbg(doc->dev, "docg4: %s\n", __func__);
554
555 writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
556 writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
557 write_nop(docptr);
558 write_nop(docptr);
559
560 /* Just busy-wait; usleep_range() slows things down noticeably. */
561 poll_status(doc);
562
563 writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
564 writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
565 writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
566 write_nop(docptr);
567 write_nop(docptr);
568 write_nop(docptr);
569 write_nop(docptr);
570 write_nop(docptr);
571
572 retval = read_progstatus(doc);
573 writew(0, docptr + DOC_DATAEND);
574 write_nop(docptr);
575 poll_status(doc);
576 write_nop(docptr);
577
578 return retval;
579 }
580
sequence_reset(struct mtd_info * mtd)581 static void sequence_reset(struct mtd_info *mtd)
582 {
583 /* common starting sequence for all operations */
584
585 struct nand_chip *nand = mtd->priv;
586 struct docg4_priv *doc = nand->priv;
587 void __iomem *docptr = doc->virtadr;
588
589 writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
590 writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
591 writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
592 write_nop(docptr);
593 write_nop(docptr);
594 poll_status(doc);
595 write_nop(docptr);
596 }
597
read_page_prologue(struct mtd_info * mtd,uint32_t docg4_addr)598 static void read_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
599 {
600 /* first step in reading a page */
601
602 struct nand_chip *nand = mtd->priv;
603 struct docg4_priv *doc = nand->priv;
604 void __iomem *docptr = doc->virtadr;
605
606 dev_dbg(doc->dev,
607 "docg4: %s: g4 page %08x\n", __func__, docg4_addr);
608
609 sequence_reset(mtd);
610
611 writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
612 writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
613 write_nop(docptr);
614
615 write_addr(doc, docg4_addr);
616
617 write_nop(docptr);
618 writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
619 write_nop(docptr);
620 write_nop(docptr);
621
622 poll_status(doc);
623 }
624
write_page_prologue(struct mtd_info * mtd,uint32_t docg4_addr)625 static void write_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
626 {
627 /* first step in writing a page */
628
629 struct nand_chip *nand = mtd->priv;
630 struct docg4_priv *doc = nand->priv;
631 void __iomem *docptr = doc->virtadr;
632
633 dev_dbg(doc->dev,
634 "docg4: %s: g4 addr: %x\n", __func__, docg4_addr);
635 sequence_reset(mtd);
636
637 if (unlikely(reliable_mode)) {
638 writew(DOCG4_SEQ_SETMODE, docptr + DOC_FLASHSEQUENCE);
639 writew(DOCG4_CMD_FAST_MODE, docptr + DOC_FLASHCOMMAND);
640 writew(DOC_CMD_RELIABLE_MODE, docptr + DOC_FLASHCOMMAND);
641 write_nop(docptr);
642 }
643
644 writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
645 writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
646 write_nop(docptr);
647 write_addr(doc, docg4_addr);
648 write_nop(docptr);
649 write_nop(docptr);
650 poll_status(doc);
651 }
652
mtd_to_docg4_address(int page,int column)653 static uint32_t mtd_to_docg4_address(int page, int column)
654 {
655 /*
656 * Convert mtd address to format used by the device, 32 bit packed.
657 *
658 * Some notes on G4 addressing... The M-Sys documentation on this device
659 * claims that pages are 2K in length, and indeed, the format of the
660 * address used by the device reflects that. But within each page are
661 * four 512 byte "sub-pages", each with its own oob data that is
662 * read/written immediately after the 512 bytes of page data. This oob
663 * data contains the ecc bytes for the preceeding 512 bytes.
664 *
665 * Rather than tell the mtd nand infrastructure that page size is 2k,
666 * with four sub-pages each, we engage in a little subterfuge and tell
667 * the infrastructure code that pages are 512 bytes in size. This is
668 * done because during the course of reverse-engineering the device, I
669 * never observed an instance where an entire 2K "page" was read or
670 * written as a unit. Each "sub-page" is always addressed individually,
671 * its data read/written, and ecc handled before the next "sub-page" is
672 * addressed.
673 *
674 * This requires us to convert addresses passed by the mtd nand
675 * infrastructure code to those used by the device.
676 *
677 * The address that is written to the device consists of four bytes: the
678 * first two are the 2k page number, and the second is the index into
679 * the page. The index is in terms of 16-bit half-words and includes
680 * the preceeding oob data, so e.g., the index into the second
681 * "sub-page" is 0x108, and the full device address of the start of mtd
682 * page 0x201 is 0x00800108.
683 */
684 int g4_page = page / 4; /* device's 2K page */
685 int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
686 return (g4_page << 16) | g4_index; /* pack */
687 }
688
docg4_command(struct mtd_info * mtd,unsigned command,int column,int page_addr)689 static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
690 int page_addr)
691 {
692 /* handle standard nand commands */
693
694 struct nand_chip *nand = mtd->priv;
695 struct docg4_priv *doc = nand->priv;
696 uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
697
698 dev_dbg(doc->dev, "%s %x, page_addr=%x, column=%x\n",
699 __func__, command, page_addr, column);
700
701 /*
702 * Save the command and its arguments. This enables emulation of
703 * standard flash devices, and also some optimizations.
704 */
705 doc->last_command.command = command;
706 doc->last_command.column = column;
707 doc->last_command.page = page_addr;
708
709 switch (command) {
710
711 case NAND_CMD_RESET:
712 reset(mtd);
713 break;
714
715 case NAND_CMD_READ0:
716 read_page_prologue(mtd, g4_addr);
717 break;
718
719 case NAND_CMD_STATUS:
720 /* next call to read_byte() will expect a status */
721 break;
722
723 case NAND_CMD_SEQIN:
724 if (unlikely(reliable_mode)) {
725 uint16_t g4_page = g4_addr >> 16;
726
727 /* writes to odd-numbered 2k pages are invalid */
728 if (g4_page & 0x01)
729 dev_warn(doc->dev,
730 "invalid reliable mode address\n");
731 }
732
733 write_page_prologue(mtd, g4_addr);
734
735 /* hack for deferred write of oob bytes */
736 if (doc->oob_page == page_addr)
737 memcpy(nand->oob_poi, doc->oob_buf, 16);
738 break;
739
740 case NAND_CMD_PAGEPROG:
741 pageprog(mtd);
742 break;
743
744 /* we don't expect these, based on review of nand_base.c */
745 case NAND_CMD_READOOB:
746 case NAND_CMD_READID:
747 case NAND_CMD_ERASE1:
748 case NAND_CMD_ERASE2:
749 dev_warn(doc->dev, "docg4_command: "
750 "unexpected nand command 0x%x\n", command);
751 break;
752
753 }
754 }
755
read_page(struct mtd_info * mtd,struct nand_chip * nand,uint8_t * buf,int page,bool use_ecc)756 static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
757 uint8_t *buf, int page, bool use_ecc)
758 {
759 struct docg4_priv *doc = nand->priv;
760 void __iomem *docptr = doc->virtadr;
761 uint16_t status, edc_err, *buf16;
762 int bits_corrected = 0;
763
764 dev_dbg(doc->dev, "%s: page %08x\n", __func__, page);
765
766 writew(DOC_ECCCONF0_READ_MODE |
767 DOC_ECCCONF0_ECC_ENABLE |
768 DOC_ECCCONF0_UNKNOWN |
769 DOCG4_BCH_SIZE,
770 docptr + DOC_ECCCONF0);
771 write_nop(docptr);
772 write_nop(docptr);
773 write_nop(docptr);
774 write_nop(docptr);
775 write_nop(docptr);
776
777 /* the 1st byte from the I/O reg is a status; the rest is page data */
778 status = readw(docptr + DOC_IOSPACE_DATA);
779 if (status & DOCG4_READ_ERROR) {
780 dev_err(doc->dev,
781 "docg4_read_page: bad status: 0x%02x\n", status);
782 writew(0, docptr + DOC_DATAEND);
783 return -EIO;
784 }
785
786 dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
787
788 docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
789
790 /* this device always reads oob after page data */
791 /* first 14 oob bytes read from I/O reg */
792 docg4_read_buf(mtd, nand->oob_poi, 14);
793
794 /* last 2 read from another reg */
795 buf16 = (uint16_t *)(nand->oob_poi + 14);
796 *buf16 = readw(docptr + DOCG4_MYSTERY_REG);
797
798 write_nop(docptr);
799
800 if (likely(use_ecc == true)) {
801
802 /* read the register that tells us if bitflip(s) detected */
803 edc_err = readw(docptr + DOC_ECCCONF1);
804 edc_err = readw(docptr + DOC_ECCCONF1);
805 dev_dbg(doc->dev, "%s: edc_err = 0x%02x\n", __func__, edc_err);
806
807 /* If bitflips are reported, attempt to correct with ecc */
808 if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
809 bits_corrected = correct_data(mtd, buf, page);
810 if (bits_corrected == -EBADMSG)
811 mtd->ecc_stats.failed++;
812 else
813 mtd->ecc_stats.corrected += bits_corrected;
814 }
815 }
816
817 writew(0, docptr + DOC_DATAEND);
818 if (bits_corrected == -EBADMSG) /* uncorrectable errors */
819 return 0;
820 return bits_corrected;
821 }
822
823
docg4_read_page_raw(struct mtd_info * mtd,struct nand_chip * nand,uint8_t * buf,int oob_required,int page)824 static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
825 uint8_t *buf, int oob_required, int page)
826 {
827 return read_page(mtd, nand, buf, page, false);
828 }
829
docg4_read_page(struct mtd_info * mtd,struct nand_chip * nand,uint8_t * buf,int oob_required,int page)830 static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
831 uint8_t *buf, int oob_required, int page)
832 {
833 return read_page(mtd, nand, buf, page, true);
834 }
835
docg4_read_oob(struct mtd_info * mtd,struct nand_chip * nand,int page)836 static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
837 int page)
838 {
839 struct docg4_priv *doc = nand->priv;
840 void __iomem *docptr = doc->virtadr;
841 uint16_t status;
842
843 dev_dbg(doc->dev, "%s: page %x\n", __func__, page);
844
845 docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page);
846
847 writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
848 write_nop(docptr);
849 write_nop(docptr);
850 write_nop(docptr);
851 write_nop(docptr);
852 write_nop(docptr);
853
854 /* the 1st byte from the I/O reg is a status; the rest is oob data */
855 status = readw(docptr + DOC_IOSPACE_DATA);
856 if (status & DOCG4_READ_ERROR) {
857 dev_warn(doc->dev,
858 "docg4_read_oob failed: status = 0x%02x\n", status);
859 return -EIO;
860 }
861
862 dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
863
864 docg4_read_buf(mtd, nand->oob_poi, 16);
865
866 write_nop(docptr);
867 write_nop(docptr);
868 write_nop(docptr);
869 writew(0, docptr + DOC_DATAEND);
870 write_nop(docptr);
871
872 return 0;
873 }
874
docg4_erase_block(struct mtd_info * mtd,int page)875 static int docg4_erase_block(struct mtd_info *mtd, int page)
876 {
877 struct nand_chip *nand = mtd->priv;
878 struct docg4_priv *doc = nand->priv;
879 void __iomem *docptr = doc->virtadr;
880 uint16_t g4_page;
881
882 dev_dbg(doc->dev, "%s: page %04x\n", __func__, page);
883
884 sequence_reset(mtd);
885
886 writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
887 writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
888 write_nop(docptr);
889
890 /* only 2 bytes of address are written to specify erase block */
891 g4_page = (uint16_t)(page / 4); /* to g4's 2k page addressing */
892 writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
893 g4_page >>= 8;
894 writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
895 write_nop(docptr);
896
897 /* start the erasure */
898 writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
899 write_nop(docptr);
900 write_nop(docptr);
901
902 usleep_range(500, 1000); /* erasure is long; take a snooze */
903 poll_status(doc);
904 writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
905 writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
906 writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
907 write_nop(docptr);
908 write_nop(docptr);
909 write_nop(docptr);
910 write_nop(docptr);
911 write_nop(docptr);
912
913 read_progstatus(doc);
914
915 writew(0, docptr + DOC_DATAEND);
916 write_nop(docptr);
917 poll_status(doc);
918 write_nop(docptr);
919
920 return nand->waitfunc(mtd, nand);
921 }
922
write_page(struct mtd_info * mtd,struct nand_chip * nand,const uint8_t * buf,bool use_ecc)923 static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
924 const uint8_t *buf, bool use_ecc)
925 {
926 struct docg4_priv *doc = nand->priv;
927 void __iomem *docptr = doc->virtadr;
928 uint8_t ecc_buf[8];
929
930 dev_dbg(doc->dev, "%s...\n", __func__);
931
932 writew(DOC_ECCCONF0_ECC_ENABLE |
933 DOC_ECCCONF0_UNKNOWN |
934 DOCG4_BCH_SIZE,
935 docptr + DOC_ECCCONF0);
936 write_nop(docptr);
937
938 /* write the page data */
939 docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
940
941 /* oob bytes 0 through 5 are written to I/O reg */
942 docg4_write_buf16(mtd, nand->oob_poi, 6);
943
944 /* oob byte 6 written to a separate reg */
945 writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
946
947 write_nop(docptr);
948 write_nop(docptr);
949
950 /* write hw-generated ecc bytes to oob */
951 if (likely(use_ecc == true)) {
952 /* oob byte 7 is hamming code */
953 uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
954 hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
955 writew(hamming, docptr + DOCG4_OOB_6_7);
956 write_nop(docptr);
957
958 /* read the 7 bch bytes from ecc regs */
959 read_hw_ecc(docptr, ecc_buf);
960 ecc_buf[7] = 0; /* clear the "page written" flag */
961 }
962
963 /* write user-supplied bytes to oob */
964 else {
965 writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
966 write_nop(docptr);
967 memcpy(ecc_buf, &nand->oob_poi[8], 8);
968 }
969
970 docg4_write_buf16(mtd, ecc_buf, 8);
971 write_nop(docptr);
972 write_nop(docptr);
973 writew(0, docptr + DOC_DATAEND);
974 write_nop(docptr);
975
976 return 0;
977 }
978
docg4_write_page_raw(struct mtd_info * mtd,struct nand_chip * nand,const uint8_t * buf,int oob_required,int page)979 static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
980 const uint8_t *buf, int oob_required, int page)
981 {
982 return write_page(mtd, nand, buf, false);
983 }
984
docg4_write_page(struct mtd_info * mtd,struct nand_chip * nand,const uint8_t * buf,int oob_required,int page)985 static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
986 const uint8_t *buf, int oob_required, int page)
987 {
988 return write_page(mtd, nand, buf, true);
989 }
990
docg4_write_oob(struct mtd_info * mtd,struct nand_chip * nand,int page)991 static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
992 int page)
993 {
994 /*
995 * Writing oob-only is not really supported, because MLC nand must write
996 * oob bytes at the same time as page data. Nonetheless, we save the
997 * oob buffer contents here, and then write it along with the page data
998 * if the same page is subsequently written. This allows user space
999 * utilities that write the oob data prior to the page data to work
1000 * (e.g., nandwrite). The disdvantage is that, if the intention was to
1001 * write oob only, the operation is quietly ignored. Also, oob can get
1002 * corrupted if two concurrent processes are running nandwrite.
1003 */
1004
1005 /* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
1006 struct docg4_priv *doc = nand->priv;
1007 doc->oob_page = page;
1008 memcpy(doc->oob_buf, nand->oob_poi, 16);
1009 return 0;
1010 }
1011
read_factory_bbt(struct mtd_info * mtd)1012 static int __init read_factory_bbt(struct mtd_info *mtd)
1013 {
1014 /*
1015 * The device contains a read-only factory bad block table. Read it and
1016 * update the memory-based bbt accordingly.
1017 */
1018
1019 struct nand_chip *nand = mtd->priv;
1020 struct docg4_priv *doc = nand->priv;
1021 uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
1022 uint8_t *buf;
1023 int i, block;
1024 __u32 eccfailed_stats = mtd->ecc_stats.failed;
1025
1026 buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
1027 if (buf == NULL)
1028 return -ENOMEM;
1029
1030 read_page_prologue(mtd, g4_addr);
1031 docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
1032
1033 /*
1034 * If no memory-based bbt was created, exit. This will happen if module
1035 * parameter ignore_badblocks is set. Then why even call this function?
1036 * For an unknown reason, block erase always fails if it's the first
1037 * operation after device power-up. The above read ensures it never is.
1038 * Ugly, I know.
1039 */
1040 if (nand->bbt == NULL) /* no memory-based bbt */
1041 goto exit;
1042
1043 if (mtd->ecc_stats.failed > eccfailed_stats) {
1044 /*
1045 * Whoops, an ecc failure ocurred reading the factory bbt.
1046 * It is stored redundantly, so we get another chance.
1047 */
1048 eccfailed_stats = mtd->ecc_stats.failed;
1049 docg4_read_page(mtd, nand, buf, 0, DOCG4_REDUNDANT_BBT_PAGE);
1050 if (mtd->ecc_stats.failed > eccfailed_stats) {
1051 dev_warn(doc->dev,
1052 "The factory bbt could not be read!\n");
1053 goto exit;
1054 }
1055 }
1056
1057 /*
1058 * Parse factory bbt and update memory-based bbt. Factory bbt format is
1059 * simple: one bit per block, block numbers increase left to right (msb
1060 * to lsb). Bit clear means bad block.
1061 */
1062 for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
1063 int bitnum;
1064 unsigned long bits = ~buf[i];
1065 for_each_set_bit(bitnum, &bits, 8) {
1066 int badblock = block + 7 - bitnum;
1067 nand->bbt[badblock / 4] |=
1068 0x03 << ((badblock % 4) * 2);
1069 mtd->ecc_stats.badblocks++;
1070 dev_notice(doc->dev, "factory-marked bad block: %d\n",
1071 badblock);
1072 }
1073 }
1074 exit:
1075 kfree(buf);
1076 return 0;
1077 }
1078
docg4_block_markbad(struct mtd_info * mtd,loff_t ofs)1079 static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
1080 {
1081 /*
1082 * Mark a block as bad. Bad blocks are marked in the oob area of the
1083 * first page of the block. The default scan_bbt() in the nand
1084 * infrastructure code works fine for building the memory-based bbt
1085 * during initialization, as does the nand infrastructure function that
1086 * checks if a block is bad by reading the bbt. This function replaces
1087 * the nand default because writes to oob-only are not supported.
1088 */
1089
1090 int ret, i;
1091 uint8_t *buf;
1092 struct nand_chip *nand = mtd->priv;
1093 struct docg4_priv *doc = nand->priv;
1094 struct nand_bbt_descr *bbtd = nand->badblock_pattern;
1095 int page = (int)(ofs >> nand->page_shift);
1096 uint32_t g4_addr = mtd_to_docg4_address(page, 0);
1097
1098 dev_dbg(doc->dev, "%s: %08llx\n", __func__, ofs);
1099
1100 if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
1101 dev_warn(doc->dev, "%s: ofs %llx not start of block!\n",
1102 __func__, ofs);
1103
1104 /* allocate blank buffer for page data */
1105 buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
1106 if (buf == NULL)
1107 return -ENOMEM;
1108
1109 /* write bit-wise negation of pattern to oob buffer */
1110 memset(nand->oob_poi, 0xff, mtd->oobsize);
1111 for (i = 0; i < bbtd->len; i++)
1112 nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
1113
1114 /* write first page of block */
1115 write_page_prologue(mtd, g4_addr);
1116 docg4_write_page(mtd, nand, buf, 1, page);
1117 ret = pageprog(mtd);
1118
1119 kfree(buf);
1120
1121 return ret;
1122 }
1123
docg4_block_neverbad(struct mtd_info * mtd,loff_t ofs,int getchip)1124 static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs, int getchip)
1125 {
1126 /* only called when module_param ignore_badblocks is set */
1127 return 0;
1128 }
1129
docg4_suspend(struct platform_device * pdev,pm_message_t state)1130 static int docg4_suspend(struct platform_device *pdev, pm_message_t state)
1131 {
1132 /*
1133 * Put the device into "deep power-down" mode. Note that CE# must be
1134 * deasserted for this to take effect. The xscale, e.g., can be
1135 * configured to float this signal when the processor enters power-down,
1136 * and a suitable pull-up ensures its deassertion.
1137 */
1138
1139 int i;
1140 uint8_t pwr_down;
1141 struct docg4_priv *doc = platform_get_drvdata(pdev);
1142 void __iomem *docptr = doc->virtadr;
1143
1144 dev_dbg(doc->dev, "%s...\n", __func__);
1145
1146 /* poll the register that tells us we're ready to go to sleep */
1147 for (i = 0; i < 10; i++) {
1148 pwr_down = readb(docptr + DOC_POWERMODE);
1149 if (pwr_down & DOC_POWERDOWN_READY)
1150 break;
1151 usleep_range(1000, 4000);
1152 }
1153
1154 if (pwr_down & DOC_POWERDOWN_READY) {
1155 dev_err(doc->dev, "suspend failed; "
1156 "timeout polling DOC_POWERDOWN_READY\n");
1157 return -EIO;
1158 }
1159
1160 writew(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN,
1161 docptr + DOC_ASICMODE);
1162 writew(~(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN),
1163 docptr + DOC_ASICMODECONFIRM);
1164
1165 write_nop(docptr);
1166
1167 return 0;
1168 }
1169
docg4_resume(struct platform_device * pdev)1170 static int docg4_resume(struct platform_device *pdev)
1171 {
1172
1173 /*
1174 * Exit power-down. Twelve consecutive reads of the address below
1175 * accomplishes this, assuming CE# has been asserted.
1176 */
1177
1178 struct docg4_priv *doc = platform_get_drvdata(pdev);
1179 void __iomem *docptr = doc->virtadr;
1180 int i;
1181
1182 dev_dbg(doc->dev, "%s...\n", __func__);
1183
1184 for (i = 0; i < 12; i++)
1185 readb(docptr + 0x1fff);
1186
1187 return 0;
1188 }
1189
init_mtd_structs(struct mtd_info * mtd)1190 static void __init init_mtd_structs(struct mtd_info *mtd)
1191 {
1192 /* initialize mtd and nand data structures */
1193
1194 /*
1195 * Note that some of the following initializations are not usually
1196 * required within a nand driver because they are performed by the nand
1197 * infrastructure code as part of nand_scan(). In this case they need
1198 * to be initialized here because we skip call to nand_scan_ident() (the
1199 * first half of nand_scan()). The call to nand_scan_ident() is skipped
1200 * because for this device the chip id is not read in the manner of a
1201 * standard nand device. Unfortunately, nand_scan_ident() does other
1202 * things as well, such as call nand_set_defaults().
1203 */
1204
1205 struct nand_chip *nand = mtd->priv;
1206 struct docg4_priv *doc = nand->priv;
1207
1208 mtd->size = DOCG4_CHIP_SIZE;
1209 mtd->name = "Msys_Diskonchip_G4";
1210 mtd->writesize = DOCG4_PAGE_SIZE;
1211 mtd->erasesize = DOCG4_BLOCK_SIZE;
1212 mtd->oobsize = DOCG4_OOB_SIZE;
1213 nand->chipsize = DOCG4_CHIP_SIZE;
1214 nand->chip_shift = DOCG4_CHIP_SHIFT;
1215 nand->bbt_erase_shift = nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
1216 nand->chip_delay = 20;
1217 nand->page_shift = DOCG4_PAGE_SHIFT;
1218 nand->pagemask = 0x3ffff;
1219 nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
1220 nand->badblockbits = 8;
1221 nand->ecc.layout = &docg4_oobinfo;
1222 nand->ecc.mode = NAND_ECC_HW_SYNDROME;
1223 nand->ecc.size = DOCG4_PAGE_SIZE;
1224 nand->ecc.prepad = 8;
1225 nand->ecc.bytes = 8;
1226 nand->ecc.strength = DOCG4_T;
1227 nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
1228 nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA;
1229 nand->controller = &nand->hwcontrol;
1230 spin_lock_init(&nand->controller->lock);
1231 init_waitqueue_head(&nand->controller->wq);
1232
1233 /* methods */
1234 nand->cmdfunc = docg4_command;
1235 nand->waitfunc = docg4_wait;
1236 nand->select_chip = docg4_select_chip;
1237 nand->read_byte = docg4_read_byte;
1238 nand->block_markbad = docg4_block_markbad;
1239 nand->read_buf = docg4_read_buf;
1240 nand->write_buf = docg4_write_buf16;
1241 nand->erase = docg4_erase_block;
1242 nand->ecc.read_page = docg4_read_page;
1243 nand->ecc.write_page = docg4_write_page;
1244 nand->ecc.read_page_raw = docg4_read_page_raw;
1245 nand->ecc.write_page_raw = docg4_write_page_raw;
1246 nand->ecc.read_oob = docg4_read_oob;
1247 nand->ecc.write_oob = docg4_write_oob;
1248
1249 /*
1250 * The way the nand infrastructure code is written, a memory-based bbt
1251 * is not created if NAND_SKIP_BBTSCAN is set. With no memory bbt,
1252 * nand->block_bad() is used. So when ignoring bad blocks, we skip the
1253 * scan and define a dummy block_bad() which always returns 0.
1254 */
1255 if (ignore_badblocks) {
1256 nand->options |= NAND_SKIP_BBTSCAN;
1257 nand->block_bad = docg4_block_neverbad;
1258 }
1259
1260 }
1261
read_id_reg(struct mtd_info * mtd)1262 static int __init read_id_reg(struct mtd_info *mtd)
1263 {
1264 struct nand_chip *nand = mtd->priv;
1265 struct docg4_priv *doc = nand->priv;
1266 void __iomem *docptr = doc->virtadr;
1267 uint16_t id1, id2;
1268
1269 /* check for presence of g4 chip by reading id registers */
1270 id1 = readw(docptr + DOC_CHIPID);
1271 id1 = readw(docptr + DOCG4_MYSTERY_REG);
1272 id2 = readw(docptr + DOC_CHIPID_INV);
1273 id2 = readw(docptr + DOCG4_MYSTERY_REG);
1274
1275 if (id1 == DOCG4_IDREG1_VALUE && id2 == DOCG4_IDREG2_VALUE) {
1276 dev_info(doc->dev,
1277 "NAND device: 128MiB Diskonchip G4 detected\n");
1278 return 0;
1279 }
1280
1281 return -ENODEV;
1282 }
1283
1284 static char const *part_probes[] = { "cmdlinepart", "saftlpart", NULL };
1285
probe_docg4(struct platform_device * pdev)1286 static int __init probe_docg4(struct platform_device *pdev)
1287 {
1288 struct mtd_info *mtd;
1289 struct nand_chip *nand;
1290 void __iomem *virtadr;
1291 struct docg4_priv *doc;
1292 int len, retval;
1293 struct resource *r;
1294 struct device *dev = &pdev->dev;
1295
1296 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 if (r == NULL) {
1298 dev_err(dev, "no io memory resource defined!\n");
1299 return -ENODEV;
1300 }
1301
1302 virtadr = ioremap(r->start, resource_size(r));
1303 if (!virtadr) {
1304 dev_err(dev, "Diskonchip ioremap failed: %pR\n", r);
1305 return -EIO;
1306 }
1307
1308 len = sizeof(struct mtd_info) + sizeof(struct nand_chip) +
1309 sizeof(struct docg4_priv);
1310 mtd = kzalloc(len, GFP_KERNEL);
1311 if (mtd == NULL) {
1312 retval = -ENOMEM;
1313 goto fail;
1314 }
1315 nand = (struct nand_chip *) (mtd + 1);
1316 doc = (struct docg4_priv *) (nand + 1);
1317 mtd->priv = nand;
1318 nand->priv = doc;
1319 mtd->dev.parent = &pdev->dev;
1320 doc->virtadr = virtadr;
1321 doc->dev = dev;
1322
1323 init_mtd_structs(mtd);
1324
1325 /* initialize kernel bch algorithm */
1326 doc->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
1327 if (doc->bch == NULL) {
1328 retval = -EINVAL;
1329 goto fail;
1330 }
1331
1332 platform_set_drvdata(pdev, doc);
1333
1334 reset(mtd);
1335 retval = read_id_reg(mtd);
1336 if (retval == -ENODEV) {
1337 dev_warn(dev, "No diskonchip G4 device found.\n");
1338 goto fail;
1339 }
1340
1341 retval = nand_scan_tail(mtd);
1342 if (retval)
1343 goto fail;
1344
1345 retval = read_factory_bbt(mtd);
1346 if (retval)
1347 goto fail;
1348
1349 retval = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
1350 if (retval)
1351 goto fail;
1352
1353 doc->mtd = mtd;
1354 return 0;
1355
1356 fail:
1357 iounmap(virtadr);
1358 if (mtd) {
1359 /* re-declarations avoid compiler warning */
1360 struct nand_chip *nand = mtd->priv;
1361 struct docg4_priv *doc = nand->priv;
1362 nand_release(mtd); /* deletes partitions and mtd devices */
1363 free_bch(doc->bch);
1364 kfree(mtd);
1365 }
1366
1367 return retval;
1368 }
1369
cleanup_docg4(struct platform_device * pdev)1370 static int __exit cleanup_docg4(struct platform_device *pdev)
1371 {
1372 struct docg4_priv *doc = platform_get_drvdata(pdev);
1373 nand_release(doc->mtd);
1374 free_bch(doc->bch);
1375 kfree(doc->mtd);
1376 iounmap(doc->virtadr);
1377 return 0;
1378 }
1379
1380 static struct platform_driver docg4_driver = {
1381 .driver = {
1382 .name = "docg4",
1383 },
1384 .suspend = docg4_suspend,
1385 .resume = docg4_resume,
1386 .remove = __exit_p(cleanup_docg4),
1387 };
1388
1389 module_platform_driver_probe(docg4_driver, probe_docg4);
1390
1391 MODULE_LICENSE("GPL");
1392 MODULE_AUTHOR("Mike Dunn");
1393 MODULE_DESCRIPTION("M-Systems DiskOnChip G4 device driver");
1394