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1 /*
2  * Freescale Integrated Flash Controller NAND driver
3  *
4  * Copyright 2011-2012 Freescale Semiconductor, Inc
5  *
6  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21  */
22 
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/of_address.h>
27 #include <linux/slab.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/mtd/nand_ecc.h>
32 #include <linux/fsl_ifc.h>
33 
34 #define ERR_BYTE		0xFF /* Value returned for read
35 					bytes when read failed	*/
36 #define IFC_TIMEOUT_MSECS	500  /* Maximum number of mSecs to wait
37 					for IFC NAND Machine	*/
38 
39 struct fsl_ifc_ctrl;
40 
41 /* mtd information per set */
42 struct fsl_ifc_mtd {
43 	struct mtd_info mtd;
44 	struct nand_chip chip;
45 	struct fsl_ifc_ctrl *ctrl;
46 
47 	struct device *dev;
48 	int bank;		/* Chip select bank number		*/
49 	unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
50 	u8 __iomem *vbase;      /* Chip select base virtual address	*/
51 };
52 
53 /* overview of the fsl ifc controller */
54 struct fsl_ifc_nand_ctrl {
55 	struct nand_hw_control controller;
56 	struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
57 
58 	void __iomem *addr;	/* Address of assigned IFC buffer	*/
59 	unsigned int page;	/* Last page written to / read from	*/
60 	unsigned int read_bytes;/* Number of bytes read during command	*/
61 	unsigned int column;	/* Saved column from SEQIN		*/
62 	unsigned int index;	/* Pointer to next byte to 'read'	*/
63 	unsigned int oob;	/* Non zero if operating on OOB data	*/
64 	unsigned int eccread;	/* Non zero for a full-page ECC read	*/
65 	unsigned int counter;	/* counter for the initializations	*/
66 	unsigned int max_bitflips;  /* Saved during READ0 cmd		*/
67 };
68 
69 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
70 
71 /* 512-byte page with 4-bit ECC, 8-bit */
72 static struct nand_ecclayout oob_512_8bit_ecc4 = {
73 	.eccbytes = 8,
74 	.eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
75 	.oobfree = { {0, 5}, {6, 2} },
76 };
77 
78 /* 512-byte page with 4-bit ECC, 16-bit */
79 static struct nand_ecclayout oob_512_16bit_ecc4 = {
80 	.eccbytes = 8,
81 	.eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
82 	.oobfree = { {2, 6}, },
83 };
84 
85 /* 2048-byte page size with 4-bit ECC */
86 static struct nand_ecclayout oob_2048_ecc4 = {
87 	.eccbytes = 32,
88 	.eccpos = {
89 		8, 9, 10, 11, 12, 13, 14, 15,
90 		16, 17, 18, 19, 20, 21, 22, 23,
91 		24, 25, 26, 27, 28, 29, 30, 31,
92 		32, 33, 34, 35, 36, 37, 38, 39,
93 	},
94 	.oobfree = { {2, 6}, {40, 24} },
95 };
96 
97 /* 4096-byte page size with 4-bit ECC */
98 static struct nand_ecclayout oob_4096_ecc4 = {
99 	.eccbytes = 64,
100 	.eccpos = {
101 		8, 9, 10, 11, 12, 13, 14, 15,
102 		16, 17, 18, 19, 20, 21, 22, 23,
103 		24, 25, 26, 27, 28, 29, 30, 31,
104 		32, 33, 34, 35, 36, 37, 38, 39,
105 		40, 41, 42, 43, 44, 45, 46, 47,
106 		48, 49, 50, 51, 52, 53, 54, 55,
107 		56, 57, 58, 59, 60, 61, 62, 63,
108 		64, 65, 66, 67, 68, 69, 70, 71,
109 	},
110 	.oobfree = { {2, 6}, {72, 56} },
111 };
112 
113 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
114 static struct nand_ecclayout oob_4096_ecc8 = {
115 	.eccbytes = 128,
116 	.eccpos = {
117 		8, 9, 10, 11, 12, 13, 14, 15,
118 		16, 17, 18, 19, 20, 21, 22, 23,
119 		24, 25, 26, 27, 28, 29, 30, 31,
120 		32, 33, 34, 35, 36, 37, 38, 39,
121 		40, 41, 42, 43, 44, 45, 46, 47,
122 		48, 49, 50, 51, 52, 53, 54, 55,
123 		56, 57, 58, 59, 60, 61, 62, 63,
124 		64, 65, 66, 67, 68, 69, 70, 71,
125 		72, 73, 74, 75, 76, 77, 78, 79,
126 		80, 81, 82, 83, 84, 85, 86, 87,
127 		88, 89, 90, 91, 92, 93, 94, 95,
128 		96, 97, 98, 99, 100, 101, 102, 103,
129 		104, 105, 106, 107, 108, 109, 110, 111,
130 		112, 113, 114, 115, 116, 117, 118, 119,
131 		120, 121, 122, 123, 124, 125, 126, 127,
132 		128, 129, 130, 131, 132, 133, 134, 135,
133 	},
134 	.oobfree = { {2, 6}, {136, 82} },
135 };
136 
137 /* 8192-byte page size with 4-bit ECC */
138 static struct nand_ecclayout oob_8192_ecc4 = {
139 	.eccbytes = 128,
140 	.eccpos = {
141 		8, 9, 10, 11, 12, 13, 14, 15,
142 		16, 17, 18, 19, 20, 21, 22, 23,
143 		24, 25, 26, 27, 28, 29, 30, 31,
144 		32, 33, 34, 35, 36, 37, 38, 39,
145 		40, 41, 42, 43, 44, 45, 46, 47,
146 		48, 49, 50, 51, 52, 53, 54, 55,
147 		56, 57, 58, 59, 60, 61, 62, 63,
148 		64, 65, 66, 67, 68, 69, 70, 71,
149 		72, 73, 74, 75, 76, 77, 78, 79,
150 		80, 81, 82, 83, 84, 85, 86, 87,
151 		88, 89, 90, 91, 92, 93, 94, 95,
152 		96, 97, 98, 99, 100, 101, 102, 103,
153 		104, 105, 106, 107, 108, 109, 110, 111,
154 		112, 113, 114, 115, 116, 117, 118, 119,
155 		120, 121, 122, 123, 124, 125, 126, 127,
156 		128, 129, 130, 131, 132, 133, 134, 135,
157 	},
158 	.oobfree = { {2, 6}, {136, 208} },
159 };
160 
161 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
162 static struct nand_ecclayout oob_8192_ecc8 = {
163 	.eccbytes = 256,
164 	.eccpos = {
165 		8, 9, 10, 11, 12, 13, 14, 15,
166 		16, 17, 18, 19, 20, 21, 22, 23,
167 		24, 25, 26, 27, 28, 29, 30, 31,
168 		32, 33, 34, 35, 36, 37, 38, 39,
169 		40, 41, 42, 43, 44, 45, 46, 47,
170 		48, 49, 50, 51, 52, 53, 54, 55,
171 		56, 57, 58, 59, 60, 61, 62, 63,
172 		64, 65, 66, 67, 68, 69, 70, 71,
173 		72, 73, 74, 75, 76, 77, 78, 79,
174 		80, 81, 82, 83, 84, 85, 86, 87,
175 		88, 89, 90, 91, 92, 93, 94, 95,
176 		96, 97, 98, 99, 100, 101, 102, 103,
177 		104, 105, 106, 107, 108, 109, 110, 111,
178 		112, 113, 114, 115, 116, 117, 118, 119,
179 		120, 121, 122, 123, 124, 125, 126, 127,
180 		128, 129, 130, 131, 132, 133, 134, 135,
181 		136, 137, 138, 139, 140, 141, 142, 143,
182 		144, 145, 146, 147, 148, 149, 150, 151,
183 		152, 153, 154, 155, 156, 157, 158, 159,
184 		160, 161, 162, 163, 164, 165, 166, 167,
185 		168, 169, 170, 171, 172, 173, 174, 175,
186 		176, 177, 178, 179, 180, 181, 182, 183,
187 		184, 185, 186, 187, 188, 189, 190, 191,
188 		192, 193, 194, 195, 196, 197, 198, 199,
189 		200, 201, 202, 203, 204, 205, 206, 207,
190 		208, 209, 210, 211, 212, 213, 214, 215,
191 		216, 217, 218, 219, 220, 221, 222, 223,
192 		224, 225, 226, 227, 228, 229, 230, 231,
193 		232, 233, 234, 235, 236, 237, 238, 239,
194 		240, 241, 242, 243, 244, 245, 246, 247,
195 		248, 249, 250, 251, 252, 253, 254, 255,
196 		256, 257, 258, 259, 260, 261, 262, 263,
197 	},
198 	.oobfree = { {2, 6}, {264, 80} },
199 };
200 
201 /*
202  * Generic flash bbt descriptors
203  */
204 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
205 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
206 
207 static struct nand_bbt_descr bbt_main_descr = {
208 	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
209 		   NAND_BBT_2BIT | NAND_BBT_VERSION,
210 	.offs =	2, /* 0 on 8-bit small page */
211 	.len = 4,
212 	.veroffs = 6,
213 	.maxblocks = 4,
214 	.pattern = bbt_pattern,
215 };
216 
217 static struct nand_bbt_descr bbt_mirror_descr = {
218 	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
219 		   NAND_BBT_2BIT | NAND_BBT_VERSION,
220 	.offs =	2, /* 0 on 8-bit small page */
221 	.len = 4,
222 	.veroffs = 6,
223 	.maxblocks = 4,
224 	.pattern = mirror_pattern,
225 };
226 
227 /*
228  * Set up the IFC hardware block and page address fields, and the ifc nand
229  * structure addr field to point to the correct IFC buffer in memory
230  */
set_addr(struct mtd_info * mtd,int column,int page_addr,int oob)231 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
232 {
233 	struct nand_chip *chip = mtd->priv;
234 	struct fsl_ifc_mtd *priv = chip->priv;
235 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
236 	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
237 	int buf_num;
238 
239 	ifc_nand_ctrl->page = page_addr;
240 	/* Program ROW0/COL0 */
241 	ifc_out32(page_addr, &ifc->ifc_nand.row0);
242 	ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
243 
244 	buf_num = page_addr & priv->bufnum_mask;
245 
246 	ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
247 	ifc_nand_ctrl->index = column;
248 
249 	/* for OOB data point to the second half of the buffer */
250 	if (oob)
251 		ifc_nand_ctrl->index += mtd->writesize;
252 }
253 
is_blank(struct mtd_info * mtd,unsigned int bufnum)254 static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
255 {
256 	struct nand_chip *chip = mtd->priv;
257 	struct fsl_ifc_mtd *priv = chip->priv;
258 	u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
259 	u32 __iomem *mainarea = (u32 __iomem *)addr;
260 	u8 __iomem *oob = addr + mtd->writesize;
261 	int i;
262 
263 	for (i = 0; i < mtd->writesize / 4; i++) {
264 		if (__raw_readl(&mainarea[i]) != 0xffffffff)
265 			return 0;
266 	}
267 
268 	for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
269 		int pos = chip->ecc.layout->eccpos[i];
270 
271 		if (__raw_readb(&oob[pos]) != 0xff)
272 			return 0;
273 	}
274 
275 	return 1;
276 }
277 
278 /* returns nonzero if entire page is blank */
check_read_ecc(struct mtd_info * mtd,struct fsl_ifc_ctrl * ctrl,u32 * eccstat,unsigned int bufnum)279 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
280 			  u32 *eccstat, unsigned int bufnum)
281 {
282 	u32 reg = eccstat[bufnum / 4];
283 	int errors;
284 
285 	errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
286 
287 	return errors;
288 }
289 
290 /*
291  * execute IFC NAND command and wait for it to complete
292  */
fsl_ifc_run_command(struct mtd_info * mtd)293 static void fsl_ifc_run_command(struct mtd_info *mtd)
294 {
295 	struct nand_chip *chip = mtd->priv;
296 	struct fsl_ifc_mtd *priv = chip->priv;
297 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
298 	struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
299 	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
300 	u32 eccstat[4];
301 	int i;
302 
303 	/* set the chip select for NAND Transaction */
304 	ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
305 		  &ifc->ifc_nand.nand_csel);
306 
307 	dev_vdbg(priv->dev,
308 			"%s: fir0=%08x fcr0=%08x\n",
309 			__func__,
310 			ifc_in32(&ifc->ifc_nand.nand_fir0),
311 			ifc_in32(&ifc->ifc_nand.nand_fcr0));
312 
313 	ctrl->nand_stat = 0;
314 
315 	/* start read/write seq */
316 	ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
317 
318 	/* wait for command complete flag or timeout */
319 	wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
320 			   msecs_to_jiffies(IFC_TIMEOUT_MSECS));
321 
322 	/* ctrl->nand_stat will be updated from IRQ context */
323 	if (!ctrl->nand_stat)
324 		dev_err(priv->dev, "Controller is not responding\n");
325 	if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
326 		dev_err(priv->dev, "NAND Flash Timeout Error\n");
327 	if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
328 		dev_err(priv->dev, "NAND Flash Write Protect Error\n");
329 
330 	nctrl->max_bitflips = 0;
331 
332 	if (nctrl->eccread) {
333 		int errors;
334 		int bufnum = nctrl->page & priv->bufnum_mask;
335 		int sector = bufnum * chip->ecc.steps;
336 		int sector_end = sector + chip->ecc.steps - 1;
337 
338 		for (i = sector / 4; i <= sector_end / 4; i++)
339 			eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
340 
341 		for (i = sector; i <= sector_end; i++) {
342 			errors = check_read_ecc(mtd, ctrl, eccstat, i);
343 
344 			if (errors == 15) {
345 				/*
346 				 * Uncorrectable error.
347 				 * OK only if the whole page is blank.
348 				 *
349 				 * We disable ECCER reporting due to...
350 				 * erratum IFC-A002770 -- so report it now if we
351 				 * see an uncorrectable error in ECCSTAT.
352 				 */
353 				if (!is_blank(mtd, bufnum))
354 					ctrl->nand_stat |=
355 						IFC_NAND_EVTER_STAT_ECCER;
356 				break;
357 			}
358 
359 			mtd->ecc_stats.corrected += errors;
360 			nctrl->max_bitflips = max_t(unsigned int,
361 						    nctrl->max_bitflips,
362 						    errors);
363 		}
364 
365 		nctrl->eccread = 0;
366 	}
367 }
368 
fsl_ifc_do_read(struct nand_chip * chip,int oob,struct mtd_info * mtd)369 static void fsl_ifc_do_read(struct nand_chip *chip,
370 			    int oob,
371 			    struct mtd_info *mtd)
372 {
373 	struct fsl_ifc_mtd *priv = chip->priv;
374 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
375 	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
376 
377 	/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
378 	if (mtd->writesize > 512) {
379 		ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
380 			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
381 			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
382 			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
383 			  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
384 			  &ifc->ifc_nand.nand_fir0);
385 		ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
386 
387 		ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
388 			  (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
389 			  &ifc->ifc_nand.nand_fcr0);
390 	} else {
391 		ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
392 			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
393 			  (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
394 			  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
395 			  &ifc->ifc_nand.nand_fir0);
396 		ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
397 
398 		if (oob)
399 			ifc_out32(NAND_CMD_READOOB <<
400 				  IFC_NAND_FCR0_CMD0_SHIFT,
401 				  &ifc->ifc_nand.nand_fcr0);
402 		else
403 			ifc_out32(NAND_CMD_READ0 <<
404 				  IFC_NAND_FCR0_CMD0_SHIFT,
405 				  &ifc->ifc_nand.nand_fcr0);
406 	}
407 }
408 
409 /* cmdfunc send commands to the IFC NAND Machine */
fsl_ifc_cmdfunc(struct mtd_info * mtd,unsigned int command,int column,int page_addr)410 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
411 			     int column, int page_addr) {
412 	struct nand_chip *chip = mtd->priv;
413 	struct fsl_ifc_mtd *priv = chip->priv;
414 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
415 	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
416 
417 	/* clear the read buffer */
418 	ifc_nand_ctrl->read_bytes = 0;
419 	if (command != NAND_CMD_PAGEPROG)
420 		ifc_nand_ctrl->index = 0;
421 
422 	switch (command) {
423 	/* READ0 read the entire buffer to use hardware ECC. */
424 	case NAND_CMD_READ0:
425 		ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
426 		set_addr(mtd, 0, page_addr, 0);
427 
428 		ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
429 		ifc_nand_ctrl->index += column;
430 
431 		if (chip->ecc.mode == NAND_ECC_HW)
432 			ifc_nand_ctrl->eccread = 1;
433 
434 		fsl_ifc_do_read(chip, 0, mtd);
435 		fsl_ifc_run_command(mtd);
436 		return;
437 
438 	/* READOOB reads only the OOB because no ECC is performed. */
439 	case NAND_CMD_READOOB:
440 		ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
441 		set_addr(mtd, column, page_addr, 1);
442 
443 		ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
444 
445 		fsl_ifc_do_read(chip, 1, mtd);
446 		fsl_ifc_run_command(mtd);
447 
448 		return;
449 
450 	case NAND_CMD_READID:
451 	case NAND_CMD_PARAM: {
452 		/*
453 		 * For READID, read 8 bytes that are currently used.
454 		 * For PARAM, read all 3 copies of 256-bytes pages.
455 		 */
456 		int len = 8;
457 		int timing = IFC_FIR_OP_RB;
458 		if (command == NAND_CMD_PARAM) {
459 			timing = IFC_FIR_OP_RBCD;
460 			len = 256 * 3;
461 		}
462 
463 		ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
464 			  (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
465 			  (timing << IFC_NAND_FIR0_OP2_SHIFT),
466 			  &ifc->ifc_nand.nand_fir0);
467 		ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
468 			  &ifc->ifc_nand.nand_fcr0);
469 		ifc_out32(column, &ifc->ifc_nand.row3);
470 
471 		ifc_out32(len, &ifc->ifc_nand.nand_fbcr);
472 		ifc_nand_ctrl->read_bytes = len;
473 
474 		set_addr(mtd, 0, 0, 0);
475 		fsl_ifc_run_command(mtd);
476 		return;
477 	}
478 
479 	/* ERASE1 stores the block and page address */
480 	case NAND_CMD_ERASE1:
481 		set_addr(mtd, 0, page_addr, 0);
482 		return;
483 
484 	/* ERASE2 uses the block and page address from ERASE1 */
485 	case NAND_CMD_ERASE2:
486 		ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
487 			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
488 			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
489 			  &ifc->ifc_nand.nand_fir0);
490 
491 		ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
492 			  (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
493 			  &ifc->ifc_nand.nand_fcr0);
494 
495 		ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
496 		ifc_nand_ctrl->read_bytes = 0;
497 		fsl_ifc_run_command(mtd);
498 		return;
499 
500 	/* SEQIN sets up the addr buffer and all registers except the length */
501 	case NAND_CMD_SEQIN: {
502 		u32 nand_fcr0;
503 		ifc_nand_ctrl->column = column;
504 		ifc_nand_ctrl->oob = 0;
505 
506 		if (mtd->writesize > 512) {
507 			nand_fcr0 =
508 				(NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
509 				(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
510 				(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
511 
512 			ifc_out32(
513 				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
514 				(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
515 				(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
516 				(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
517 				(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
518 				&ifc->ifc_nand.nand_fir0);
519 			ifc_out32(
520 				(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
521 				(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
522 				(IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
523 				&ifc->ifc_nand.nand_fir1);
524 		} else {
525 			nand_fcr0 = ((NAND_CMD_PAGEPROG <<
526 					IFC_NAND_FCR0_CMD1_SHIFT) |
527 				    (NAND_CMD_SEQIN <<
528 					IFC_NAND_FCR0_CMD2_SHIFT) |
529 				    (NAND_CMD_STATUS <<
530 					IFC_NAND_FCR0_CMD3_SHIFT));
531 
532 			ifc_out32(
533 				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
534 				(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
535 				(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
536 				(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
537 				(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
538 				&ifc->ifc_nand.nand_fir0);
539 			ifc_out32(
540 				(IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
541 				(IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
542 				(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
543 				(IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
544 				&ifc->ifc_nand.nand_fir1);
545 
546 			if (column >= mtd->writesize)
547 				nand_fcr0 |=
548 				NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
549 			else
550 				nand_fcr0 |=
551 				NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
552 		}
553 
554 		if (column >= mtd->writesize) {
555 			/* OOB area --> READOOB */
556 			column -= mtd->writesize;
557 			ifc_nand_ctrl->oob = 1;
558 		}
559 		ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
560 		set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
561 		return;
562 	}
563 
564 	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
565 	case NAND_CMD_PAGEPROG: {
566 		if (ifc_nand_ctrl->oob) {
567 			ifc_out32(ifc_nand_ctrl->index -
568 				  ifc_nand_ctrl->column,
569 				  &ifc->ifc_nand.nand_fbcr);
570 		} else {
571 			ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
572 		}
573 
574 		fsl_ifc_run_command(mtd);
575 		return;
576 	}
577 
578 	case NAND_CMD_STATUS: {
579 		void __iomem *addr;
580 
581 		ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
582 			  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
583 			  &ifc->ifc_nand.nand_fir0);
584 		ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
585 			  &ifc->ifc_nand.nand_fcr0);
586 		ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
587 		set_addr(mtd, 0, 0, 0);
588 		ifc_nand_ctrl->read_bytes = 1;
589 
590 		fsl_ifc_run_command(mtd);
591 
592 		/*
593 		 * The chip always seems to report that it is
594 		 * write-protected, even when it is not.
595 		 */
596 		addr = ifc_nand_ctrl->addr;
597 		if (chip->options & NAND_BUSWIDTH_16)
598 			ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
599 		else
600 			ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
601 		return;
602 	}
603 
604 	case NAND_CMD_RESET:
605 		ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
606 			  &ifc->ifc_nand.nand_fir0);
607 		ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
608 			  &ifc->ifc_nand.nand_fcr0);
609 		fsl_ifc_run_command(mtd);
610 		return;
611 
612 	default:
613 		dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
614 					__func__, command);
615 	}
616 }
617 
fsl_ifc_select_chip(struct mtd_info * mtd,int chip)618 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
619 {
620 	/* The hardware does not seem to support multiple
621 	 * chips per bank.
622 	 */
623 }
624 
625 /*
626  * Write buf to the IFC NAND Controller Data Buffer
627  */
fsl_ifc_write_buf(struct mtd_info * mtd,const u8 * buf,int len)628 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
629 {
630 	struct nand_chip *chip = mtd->priv;
631 	struct fsl_ifc_mtd *priv = chip->priv;
632 	unsigned int bufsize = mtd->writesize + mtd->oobsize;
633 
634 	if (len <= 0) {
635 		dev_err(priv->dev, "%s: len %d bytes", __func__, len);
636 		return;
637 	}
638 
639 	if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
640 		dev_err(priv->dev,
641 			"%s: beyond end of buffer (%d requested, %u available)\n",
642 			__func__, len, bufsize - ifc_nand_ctrl->index);
643 		len = bufsize - ifc_nand_ctrl->index;
644 	}
645 
646 	memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
647 	ifc_nand_ctrl->index += len;
648 }
649 
650 /*
651  * Read a byte from either the IFC hardware buffer
652  * read function for 8-bit buswidth
653  */
fsl_ifc_read_byte(struct mtd_info * mtd)654 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
655 {
656 	struct nand_chip *chip = mtd->priv;
657 	struct fsl_ifc_mtd *priv = chip->priv;
658 	unsigned int offset;
659 
660 	/*
661 	 * If there are still bytes in the IFC buffer, then use the
662 	 * next byte.
663 	 */
664 	if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
665 		offset = ifc_nand_ctrl->index++;
666 		return ifc_in8(ifc_nand_ctrl->addr + offset);
667 	}
668 
669 	dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
670 	return ERR_BYTE;
671 }
672 
673 /*
674  * Read two bytes from the IFC hardware buffer
675  * read function for 16-bit buswith
676  */
fsl_ifc_read_byte16(struct mtd_info * mtd)677 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
678 {
679 	struct nand_chip *chip = mtd->priv;
680 	struct fsl_ifc_mtd *priv = chip->priv;
681 	uint16_t data;
682 
683 	/*
684 	 * If there are still bytes in the IFC buffer, then use the
685 	 * next byte.
686 	 */
687 	if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
688 		data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
689 		ifc_nand_ctrl->index += 2;
690 		return (uint8_t) data;
691 	}
692 
693 	dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
694 	return ERR_BYTE;
695 }
696 
697 /*
698  * Read from the IFC Controller Data Buffer
699  */
fsl_ifc_read_buf(struct mtd_info * mtd,u8 * buf,int len)700 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
701 {
702 	struct nand_chip *chip = mtd->priv;
703 	struct fsl_ifc_mtd *priv = chip->priv;
704 	int avail;
705 
706 	if (len < 0) {
707 		dev_err(priv->dev, "%s: len %d bytes", __func__, len);
708 		return;
709 	}
710 
711 	avail = min((unsigned int)len,
712 			ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
713 	memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
714 	ifc_nand_ctrl->index += avail;
715 
716 	if (len > avail)
717 		dev_err(priv->dev,
718 			"%s: beyond end of buffer (%d requested, %d available)\n",
719 			__func__, len, avail);
720 }
721 
722 /*
723  * This function is called after Program and Erase Operations to
724  * check for success or failure.
725  */
fsl_ifc_wait(struct mtd_info * mtd,struct nand_chip * chip)726 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
727 {
728 	struct fsl_ifc_mtd *priv = chip->priv;
729 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
730 	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
731 	u32 nand_fsr;
732 	int status;
733 
734 	/* Use READ_STATUS command, but wait for the device to be ready */
735 	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
736 		  (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
737 		  &ifc->ifc_nand.nand_fir0);
738 	ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
739 		  &ifc->ifc_nand.nand_fcr0);
740 	ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
741 	set_addr(mtd, 0, 0, 0);
742 	ifc_nand_ctrl->read_bytes = 1;
743 
744 	fsl_ifc_run_command(mtd);
745 
746 	nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
747 	status = nand_fsr >> 24;
748 	/*
749 	 * The chip always seems to report that it is
750 	 * write-protected, even when it is not.
751 	 */
752 	return status | NAND_STATUS_WP;
753 }
754 
fsl_ifc_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)755 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
756 			     uint8_t *buf, int oob_required, int page)
757 {
758 	struct fsl_ifc_mtd *priv = chip->priv;
759 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
760 	struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
761 
762 	fsl_ifc_read_buf(mtd, buf, mtd->writesize);
763 	if (oob_required)
764 		fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
765 
766 	if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
767 		dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
768 
769 	if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
770 		mtd->ecc_stats.failed++;
771 
772 	return nctrl->max_bitflips;
773 }
774 
775 /* ECC will be calculated automatically, and errors will be detected in
776  * waitfunc.
777  */
fsl_ifc_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)778 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
779 			       const uint8_t *buf, int oob_required, int page)
780 {
781 	fsl_ifc_write_buf(mtd, buf, mtd->writesize);
782 	fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
783 
784 	return 0;
785 }
786 
fsl_ifc_chip_init_tail(struct mtd_info * mtd)787 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
788 {
789 	struct nand_chip *chip = mtd->priv;
790 	struct fsl_ifc_mtd *priv = chip->priv;
791 
792 	dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
793 							chip->numchips);
794 	dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
795 							chip->chipsize);
796 	dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
797 							chip->pagemask);
798 	dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
799 							chip->chip_delay);
800 	dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
801 							chip->badblockpos);
802 	dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
803 							chip->chip_shift);
804 	dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
805 							chip->page_shift);
806 	dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
807 							chip->phys_erase_shift);
808 	dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
809 							chip->ecc.mode);
810 	dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
811 							chip->ecc.steps);
812 	dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
813 							chip->ecc.bytes);
814 	dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
815 							chip->ecc.total);
816 	dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
817 							chip->ecc.layout);
818 	dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
819 	dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
820 	dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
821 							mtd->erasesize);
822 	dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
823 							mtd->writesize);
824 	dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
825 							mtd->oobsize);
826 
827 	return 0;
828 }
829 
fsl_ifc_sram_init(struct fsl_ifc_mtd * priv)830 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
831 {
832 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
833 	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
834 	uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
835 	uint32_t cs = priv->bank;
836 
837 	/* Save CSOR and CSOR_ext */
838 	csor = ifc_in32(&ifc->csor_cs[cs].csor);
839 	csor_ext = ifc_in32(&ifc->csor_cs[cs].csor_ext);
840 
841 	/* chage PageSize 8K and SpareSize 1K*/
842 	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
843 	ifc_out32(csor_8k, &ifc->csor_cs[cs].csor);
844 	ifc_out32(0x0000400, &ifc->csor_cs[cs].csor_ext);
845 
846 	/* READID */
847 	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
848 		  (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
849 		  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
850 		  &ifc->ifc_nand.nand_fir0);
851 	ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
852 		  &ifc->ifc_nand.nand_fcr0);
853 	ifc_out32(0x0, &ifc->ifc_nand.row3);
854 
855 	ifc_out32(0x0, &ifc->ifc_nand.nand_fbcr);
856 
857 	/* Program ROW0/COL0 */
858 	ifc_out32(0x0, &ifc->ifc_nand.row0);
859 	ifc_out32(0x0, &ifc->ifc_nand.col0);
860 
861 	/* set the chip select for NAND Transaction */
862 	ifc_out32(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
863 
864 	/* start read seq */
865 	ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
866 
867 	/* wait for command complete flag or timeout */
868 	wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
869 			   msecs_to_jiffies(IFC_TIMEOUT_MSECS));
870 
871 	if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
872 		printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
873 
874 	/* Restore CSOR and CSOR_ext */
875 	ifc_out32(csor, &ifc->csor_cs[cs].csor);
876 	ifc_out32(csor_ext, &ifc->csor_cs[cs].csor_ext);
877 }
878 
fsl_ifc_chip_init(struct fsl_ifc_mtd * priv)879 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
880 {
881 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
882 	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
883 	struct nand_chip *chip = &priv->chip;
884 	struct nand_ecclayout *layout;
885 	u32 csor;
886 
887 	/* Fill in fsl_ifc_mtd structure */
888 	priv->mtd.priv = chip;
889 	priv->mtd.dev.parent = priv->dev;
890 
891 	/* fill in nand_chip structure */
892 	/* set up function call table */
893 	if ((ifc_in32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
894 		chip->read_byte = fsl_ifc_read_byte16;
895 	else
896 		chip->read_byte = fsl_ifc_read_byte;
897 
898 	chip->write_buf = fsl_ifc_write_buf;
899 	chip->read_buf = fsl_ifc_read_buf;
900 	chip->select_chip = fsl_ifc_select_chip;
901 	chip->cmdfunc = fsl_ifc_cmdfunc;
902 	chip->waitfunc = fsl_ifc_wait;
903 
904 	chip->bbt_td = &bbt_main_descr;
905 	chip->bbt_md = &bbt_mirror_descr;
906 
907 	ifc_out32(0x0, &ifc->ifc_nand.ncfgr);
908 
909 	/* set up nand options */
910 	chip->bbt_options = NAND_BBT_USE_FLASH;
911 	chip->options = NAND_NO_SUBPAGE_WRITE;
912 
913 	if (ifc_in32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
914 		chip->read_byte = fsl_ifc_read_byte16;
915 		chip->options |= NAND_BUSWIDTH_16;
916 	} else {
917 		chip->read_byte = fsl_ifc_read_byte;
918 	}
919 
920 	chip->controller = &ifc_nand_ctrl->controller;
921 	chip->priv = priv;
922 
923 	chip->ecc.read_page = fsl_ifc_read_page;
924 	chip->ecc.write_page = fsl_ifc_write_page;
925 
926 	csor = ifc_in32(&ifc->csor_cs[priv->bank].csor);
927 
928 	/* Hardware generates ECC per 512 Bytes */
929 	chip->ecc.size = 512;
930 	chip->ecc.bytes = 8;
931 	chip->ecc.strength = 4;
932 
933 	switch (csor & CSOR_NAND_PGS_MASK) {
934 	case CSOR_NAND_PGS_512:
935 		if (chip->options & NAND_BUSWIDTH_16) {
936 			layout = &oob_512_16bit_ecc4;
937 		} else {
938 			layout = &oob_512_8bit_ecc4;
939 
940 			/* Avoid conflict with bad block marker */
941 			bbt_main_descr.offs = 0;
942 			bbt_mirror_descr.offs = 0;
943 		}
944 
945 		priv->bufnum_mask = 15;
946 		break;
947 
948 	case CSOR_NAND_PGS_2K:
949 		layout = &oob_2048_ecc4;
950 		priv->bufnum_mask = 3;
951 		break;
952 
953 	case CSOR_NAND_PGS_4K:
954 		if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
955 		    CSOR_NAND_ECC_MODE_4) {
956 			layout = &oob_4096_ecc4;
957 		} else {
958 			layout = &oob_4096_ecc8;
959 			chip->ecc.bytes = 16;
960 			chip->ecc.strength = 8;
961 		}
962 
963 		priv->bufnum_mask = 1;
964 		break;
965 
966 	case CSOR_NAND_PGS_8K:
967 		if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
968 		    CSOR_NAND_ECC_MODE_4) {
969 			layout = &oob_8192_ecc4;
970 		} else {
971 			layout = &oob_8192_ecc8;
972 			chip->ecc.bytes = 16;
973 			chip->ecc.strength = 8;
974 		}
975 
976 		priv->bufnum_mask = 0;
977 	break;
978 
979 	default:
980 		dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
981 		return -ENODEV;
982 	}
983 
984 	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
985 	if (csor & CSOR_NAND_ECC_DEC_EN) {
986 		chip->ecc.mode = NAND_ECC_HW;
987 		chip->ecc.layout = layout;
988 	} else {
989 		chip->ecc.mode = NAND_ECC_SOFT;
990 	}
991 
992 	if (ctrl->version == FSL_IFC_VERSION_1_1_0)
993 		fsl_ifc_sram_init(priv);
994 
995 	return 0;
996 }
997 
fsl_ifc_chip_remove(struct fsl_ifc_mtd * priv)998 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
999 {
1000 	nand_release(&priv->mtd);
1001 
1002 	kfree(priv->mtd.name);
1003 
1004 	if (priv->vbase)
1005 		iounmap(priv->vbase);
1006 
1007 	ifc_nand_ctrl->chips[priv->bank] = NULL;
1008 
1009 	return 0;
1010 }
1011 
match_bank(struct fsl_ifc_regs __iomem * ifc,int bank,phys_addr_t addr)1012 static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
1013 		      phys_addr_t addr)
1014 {
1015 	u32 cspr = ifc_in32(&ifc->cspr_cs[bank].cspr);
1016 
1017 	if (!(cspr & CSPR_V))
1018 		return 0;
1019 	if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
1020 		return 0;
1021 
1022 	return (cspr & CSPR_BA) == convert_ifc_address(addr);
1023 }
1024 
1025 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
1026 
fsl_ifc_nand_probe(struct platform_device * dev)1027 static int fsl_ifc_nand_probe(struct platform_device *dev)
1028 {
1029 	struct fsl_ifc_regs __iomem *ifc;
1030 	struct fsl_ifc_mtd *priv;
1031 	struct resource res;
1032 	static const char *part_probe_types[]
1033 		= { "cmdlinepart", "RedBoot", "ofpart", NULL };
1034 	int ret;
1035 	int bank;
1036 	struct device_node *node = dev->dev.of_node;
1037 	struct mtd_part_parser_data ppdata;
1038 
1039 	ppdata.of_node = dev->dev.of_node;
1040 	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
1041 		return -ENODEV;
1042 	ifc = fsl_ifc_ctrl_dev->regs;
1043 
1044 	/* get, allocate and map the memory resource */
1045 	ret = of_address_to_resource(node, 0, &res);
1046 	if (ret) {
1047 		dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
1048 		return ret;
1049 	}
1050 
1051 	/* find which chip select it is connected to */
1052 	for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
1053 		if (match_bank(ifc, bank, res.start))
1054 			break;
1055 	}
1056 
1057 	if (bank >= fsl_ifc_ctrl_dev->banks) {
1058 		dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1059 			__func__);
1060 		return -ENODEV;
1061 	}
1062 
1063 	priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1064 	if (!priv)
1065 		return -ENOMEM;
1066 
1067 	mutex_lock(&fsl_ifc_nand_mutex);
1068 	if (!fsl_ifc_ctrl_dev->nand) {
1069 		ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
1070 		if (!ifc_nand_ctrl) {
1071 			mutex_unlock(&fsl_ifc_nand_mutex);
1072 			return -ENOMEM;
1073 		}
1074 
1075 		ifc_nand_ctrl->read_bytes = 0;
1076 		ifc_nand_ctrl->index = 0;
1077 		ifc_nand_ctrl->addr = NULL;
1078 		fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1079 
1080 		spin_lock_init(&ifc_nand_ctrl->controller.lock);
1081 		init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
1082 	} else {
1083 		ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1084 	}
1085 	mutex_unlock(&fsl_ifc_nand_mutex);
1086 
1087 	ifc_nand_ctrl->chips[bank] = priv;
1088 	priv->bank = bank;
1089 	priv->ctrl = fsl_ifc_ctrl_dev;
1090 	priv->dev = &dev->dev;
1091 
1092 	priv->vbase = ioremap(res.start, resource_size(&res));
1093 	if (!priv->vbase) {
1094 		dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1095 		ret = -ENOMEM;
1096 		goto err;
1097 	}
1098 
1099 	dev_set_drvdata(priv->dev, priv);
1100 
1101 	ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1102 		  IFC_NAND_EVTER_EN_FTOER_EN |
1103 		  IFC_NAND_EVTER_EN_WPER_EN,
1104 		  &ifc->ifc_nand.nand_evter_en);
1105 
1106 	/* enable NAND Machine Interrupts */
1107 	ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1108 		  IFC_NAND_EVTER_INTR_FTOERIR_EN |
1109 		  IFC_NAND_EVTER_INTR_WPERIR_EN,
1110 		  &ifc->ifc_nand.nand_evter_intr_en);
1111 	priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1112 	if (!priv->mtd.name) {
1113 		ret = -ENOMEM;
1114 		goto err;
1115 	}
1116 
1117 	ret = fsl_ifc_chip_init(priv);
1118 	if (ret)
1119 		goto err;
1120 
1121 	ret = nand_scan_ident(&priv->mtd, 1, NULL);
1122 	if (ret)
1123 		goto err;
1124 
1125 	ret = fsl_ifc_chip_init_tail(&priv->mtd);
1126 	if (ret)
1127 		goto err;
1128 
1129 	ret = nand_scan_tail(&priv->mtd);
1130 	if (ret)
1131 		goto err;
1132 
1133 	/* First look for RedBoot table or partitions on the command
1134 	 * line, these take precedence over device tree information */
1135 	mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
1136 						NULL, 0);
1137 
1138 	dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1139 		 (unsigned long long)res.start, priv->bank);
1140 	return 0;
1141 
1142 err:
1143 	fsl_ifc_chip_remove(priv);
1144 	return ret;
1145 }
1146 
fsl_ifc_nand_remove(struct platform_device * dev)1147 static int fsl_ifc_nand_remove(struct platform_device *dev)
1148 {
1149 	struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1150 
1151 	fsl_ifc_chip_remove(priv);
1152 
1153 	mutex_lock(&fsl_ifc_nand_mutex);
1154 	ifc_nand_ctrl->counter--;
1155 	if (!ifc_nand_ctrl->counter) {
1156 		fsl_ifc_ctrl_dev->nand = NULL;
1157 		kfree(ifc_nand_ctrl);
1158 	}
1159 	mutex_unlock(&fsl_ifc_nand_mutex);
1160 
1161 	return 0;
1162 }
1163 
1164 static const struct of_device_id fsl_ifc_nand_match[] = {
1165 	{
1166 		.compatible = "fsl,ifc-nand",
1167 	},
1168 	{}
1169 };
1170 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1171 
1172 static struct platform_driver fsl_ifc_nand_driver = {
1173 	.driver = {
1174 		.name	= "fsl,ifc-nand",
1175 		.of_match_table = fsl_ifc_nand_match,
1176 	},
1177 	.probe       = fsl_ifc_nand_probe,
1178 	.remove      = fsl_ifc_nand_remove,
1179 };
1180 
1181 module_platform_driver(fsl_ifc_nand_driver);
1182 
1183 MODULE_LICENSE("GPL");
1184 MODULE_AUTHOR("Freescale");
1185 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
1186