1 /*
2 * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
3 *
4 * This file is free software: you may copy, redistribute and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation, either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * This file incorporates work covered by the following copyright and
18 * permission notice:
19 *
20 * Copyright (c) 2012 Qualcomm Atheros, Inc.
21 *
22 * Permission to use, copy, modify, and/or distribute this software for any
23 * purpose with or without fee is hereby granted, provided that the above
24 * copyright notice and this permission notice appear in all copies.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
33 */
34
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/ip.h>
39 #include <linux/ipv6.h>
40 #include <linux/if_vlan.h>
41 #include <linux/mdio.h>
42 #include <linux/aer.h>
43 #include <linux/bitops.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <net/ip6_checksum.h>
47 #include <linux/crc32.h>
48 #include "alx.h"
49 #include "hw.h"
50 #include "reg.h"
51
52 const char alx_drv_name[] = "alx";
53
54
alx_free_txbuf(struct alx_priv * alx,int entry)55 static void alx_free_txbuf(struct alx_priv *alx, int entry)
56 {
57 struct alx_buffer *txb = &alx->txq.bufs[entry];
58
59 if (dma_unmap_len(txb, size)) {
60 dma_unmap_single(&alx->hw.pdev->dev,
61 dma_unmap_addr(txb, dma),
62 dma_unmap_len(txb, size),
63 DMA_TO_DEVICE);
64 dma_unmap_len_set(txb, size, 0);
65 }
66
67 if (txb->skb) {
68 dev_kfree_skb_any(txb->skb);
69 txb->skb = NULL;
70 }
71 }
72
alx_refill_rx_ring(struct alx_priv * alx,gfp_t gfp)73 static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp)
74 {
75 struct alx_rx_queue *rxq = &alx->rxq;
76 struct sk_buff *skb;
77 struct alx_buffer *cur_buf;
78 dma_addr_t dma;
79 u16 cur, next, count = 0;
80
81 next = cur = rxq->write_idx;
82 if (++next == alx->rx_ringsz)
83 next = 0;
84 cur_buf = &rxq->bufs[cur];
85
86 while (!cur_buf->skb && next != rxq->read_idx) {
87 struct alx_rfd *rfd = &rxq->rfd[cur];
88
89 skb = __netdev_alloc_skb(alx->dev, alx->rxbuf_size + 64, gfp);
90 if (!skb)
91 break;
92
93 /* Workround for the HW RX DMA overflow issue */
94 if (((unsigned long)skb->data & 0xfff) == 0xfc0)
95 skb_reserve(skb, 64);
96
97 dma = dma_map_single(&alx->hw.pdev->dev,
98 skb->data, alx->rxbuf_size,
99 DMA_FROM_DEVICE);
100 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) {
101 dev_kfree_skb(skb);
102 break;
103 }
104
105 /* Unfortunately, RX descriptor buffers must be 4-byte
106 * aligned, so we can't use IP alignment.
107 */
108 if (WARN_ON(dma & 3)) {
109 dev_kfree_skb(skb);
110 break;
111 }
112
113 cur_buf->skb = skb;
114 dma_unmap_len_set(cur_buf, size, alx->rxbuf_size);
115 dma_unmap_addr_set(cur_buf, dma, dma);
116 rfd->addr = cpu_to_le64(dma);
117
118 cur = next;
119 if (++next == alx->rx_ringsz)
120 next = 0;
121 cur_buf = &rxq->bufs[cur];
122 count++;
123 }
124
125 if (count) {
126 /* flush all updates before updating hardware */
127 wmb();
128 rxq->write_idx = cur;
129 alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur);
130 }
131
132 return count;
133 }
134
alx_tpd_avail(struct alx_priv * alx)135 static inline int alx_tpd_avail(struct alx_priv *alx)
136 {
137 struct alx_tx_queue *txq = &alx->txq;
138
139 if (txq->write_idx >= txq->read_idx)
140 return alx->tx_ringsz + txq->read_idx - txq->write_idx - 1;
141 return txq->read_idx - txq->write_idx - 1;
142 }
143
alx_clean_tx_irq(struct alx_priv * alx)144 static bool alx_clean_tx_irq(struct alx_priv *alx)
145 {
146 struct alx_tx_queue *txq = &alx->txq;
147 u16 hw_read_idx, sw_read_idx;
148 unsigned int total_bytes = 0, total_packets = 0;
149 int budget = ALX_DEFAULT_TX_WORK;
150
151 sw_read_idx = txq->read_idx;
152 hw_read_idx = alx_read_mem16(&alx->hw, ALX_TPD_PRI0_CIDX);
153
154 if (sw_read_idx != hw_read_idx) {
155 while (sw_read_idx != hw_read_idx && budget > 0) {
156 struct sk_buff *skb;
157
158 skb = txq->bufs[sw_read_idx].skb;
159 if (skb) {
160 total_bytes += skb->len;
161 total_packets++;
162 budget--;
163 }
164
165 alx_free_txbuf(alx, sw_read_idx);
166
167 if (++sw_read_idx == alx->tx_ringsz)
168 sw_read_idx = 0;
169 }
170 txq->read_idx = sw_read_idx;
171
172 netdev_completed_queue(alx->dev, total_packets, total_bytes);
173 }
174
175 if (netif_queue_stopped(alx->dev) && netif_carrier_ok(alx->dev) &&
176 alx_tpd_avail(alx) > alx->tx_ringsz/4)
177 netif_wake_queue(alx->dev);
178
179 return sw_read_idx == hw_read_idx;
180 }
181
alx_schedule_link_check(struct alx_priv * alx)182 static void alx_schedule_link_check(struct alx_priv *alx)
183 {
184 schedule_work(&alx->link_check_wk);
185 }
186
alx_schedule_reset(struct alx_priv * alx)187 static void alx_schedule_reset(struct alx_priv *alx)
188 {
189 schedule_work(&alx->reset_wk);
190 }
191
alx_clean_rx_irq(struct alx_priv * alx,int budget)192 static int alx_clean_rx_irq(struct alx_priv *alx, int budget)
193 {
194 struct alx_rx_queue *rxq = &alx->rxq;
195 struct alx_rrd *rrd;
196 struct alx_buffer *rxb;
197 struct sk_buff *skb;
198 u16 length, rfd_cleaned = 0;
199 int work = 0;
200
201 while (work < budget) {
202 rrd = &rxq->rrd[rxq->rrd_read_idx];
203 if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT)))
204 break;
205 rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT);
206
207 if (ALX_GET_FIELD(le32_to_cpu(rrd->word0),
208 RRD_SI) != rxq->read_idx ||
209 ALX_GET_FIELD(le32_to_cpu(rrd->word0),
210 RRD_NOR) != 1) {
211 alx_schedule_reset(alx);
212 return work;
213 }
214
215 rxb = &rxq->bufs[rxq->read_idx];
216 dma_unmap_single(&alx->hw.pdev->dev,
217 dma_unmap_addr(rxb, dma),
218 dma_unmap_len(rxb, size),
219 DMA_FROM_DEVICE);
220 dma_unmap_len_set(rxb, size, 0);
221 skb = rxb->skb;
222 rxb->skb = NULL;
223
224 if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) ||
225 rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) {
226 rrd->word3 = 0;
227 dev_kfree_skb_any(skb);
228 goto next_pkt;
229 }
230
231 length = ALX_GET_FIELD(le32_to_cpu(rrd->word3),
232 RRD_PKTLEN) - ETH_FCS_LEN;
233 skb_put(skb, length);
234 skb->protocol = eth_type_trans(skb, alx->dev);
235
236 skb_checksum_none_assert(skb);
237 if (alx->dev->features & NETIF_F_RXCSUM &&
238 !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) |
239 cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) {
240 switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2),
241 RRD_PID)) {
242 case RRD_PID_IPV6UDP:
243 case RRD_PID_IPV4UDP:
244 case RRD_PID_IPV4TCP:
245 case RRD_PID_IPV6TCP:
246 skb->ip_summed = CHECKSUM_UNNECESSARY;
247 break;
248 }
249 }
250
251 napi_gro_receive(&alx->napi, skb);
252 work++;
253
254 next_pkt:
255 if (++rxq->read_idx == alx->rx_ringsz)
256 rxq->read_idx = 0;
257 if (++rxq->rrd_read_idx == alx->rx_ringsz)
258 rxq->rrd_read_idx = 0;
259
260 if (++rfd_cleaned > ALX_RX_ALLOC_THRESH)
261 rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC);
262 }
263
264 if (rfd_cleaned)
265 alx_refill_rx_ring(alx, GFP_ATOMIC);
266
267 return work;
268 }
269
alx_poll(struct napi_struct * napi,int budget)270 static int alx_poll(struct napi_struct *napi, int budget)
271 {
272 struct alx_priv *alx = container_of(napi, struct alx_priv, napi);
273 struct alx_hw *hw = &alx->hw;
274 unsigned long flags;
275 bool tx_complete;
276 int work;
277
278 tx_complete = alx_clean_tx_irq(alx);
279 work = alx_clean_rx_irq(alx, budget);
280
281 if (!tx_complete || work == budget)
282 return budget;
283
284 napi_complete(&alx->napi);
285
286 /* enable interrupt */
287 spin_lock_irqsave(&alx->irq_lock, flags);
288 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
289 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
290 spin_unlock_irqrestore(&alx->irq_lock, flags);
291
292 alx_post_write(hw);
293
294 return work;
295 }
296
alx_intr_handle(struct alx_priv * alx,u32 intr)297 static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
298 {
299 struct alx_hw *hw = &alx->hw;
300 bool write_int_mask = false;
301
302 spin_lock(&alx->irq_lock);
303
304 /* ACK interrupt */
305 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
306 intr &= alx->int_mask;
307
308 if (intr & ALX_ISR_FATAL) {
309 netif_warn(alx, hw, alx->dev,
310 "fatal interrupt 0x%x, resetting\n", intr);
311 alx_schedule_reset(alx);
312 goto out;
313 }
314
315 if (intr & ALX_ISR_ALERT)
316 netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr);
317
318 if (intr & ALX_ISR_PHY) {
319 /* suppress PHY interrupt, because the source
320 * is from PHY internal. only the internal status
321 * is cleared, the interrupt status could be cleared.
322 */
323 alx->int_mask &= ~ALX_ISR_PHY;
324 write_int_mask = true;
325 alx_schedule_link_check(alx);
326 }
327
328 if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
329 napi_schedule(&alx->napi);
330 /* mask rx/tx interrupt, enable them when napi complete */
331 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
332 write_int_mask = true;
333 }
334
335 if (write_int_mask)
336 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
337
338 alx_write_mem32(hw, ALX_ISR, 0);
339
340 out:
341 spin_unlock(&alx->irq_lock);
342 return IRQ_HANDLED;
343 }
344
alx_intr_msi(int irq,void * data)345 static irqreturn_t alx_intr_msi(int irq, void *data)
346 {
347 struct alx_priv *alx = data;
348
349 return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR));
350 }
351
alx_intr_legacy(int irq,void * data)352 static irqreturn_t alx_intr_legacy(int irq, void *data)
353 {
354 struct alx_priv *alx = data;
355 struct alx_hw *hw = &alx->hw;
356 u32 intr;
357
358 intr = alx_read_mem32(hw, ALX_ISR);
359
360 if (intr & ALX_ISR_DIS || !(intr & alx->int_mask))
361 return IRQ_NONE;
362
363 return alx_intr_handle(alx, intr);
364 }
365
alx_init_ring_ptrs(struct alx_priv * alx)366 static void alx_init_ring_ptrs(struct alx_priv *alx)
367 {
368 struct alx_hw *hw = &alx->hw;
369 u32 addr_hi = ((u64)alx->descmem.dma) >> 32;
370
371 alx->rxq.read_idx = 0;
372 alx->rxq.write_idx = 0;
373 alx->rxq.rrd_read_idx = 0;
374 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
375 alx_write_mem32(hw, ALX_RRD_ADDR_LO, alx->rxq.rrd_dma);
376 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
377 alx_write_mem32(hw, ALX_RFD_ADDR_LO, alx->rxq.rfd_dma);
378 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz);
379 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size);
380
381 alx->txq.read_idx = 0;
382 alx->txq.write_idx = 0;
383 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
384 alx_write_mem32(hw, ALX_TPD_PRI0_ADDR_LO, alx->txq.tpd_dma);
385 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
386
387 /* load these pointers into the chip */
388 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
389 }
390
alx_free_txring_buf(struct alx_priv * alx)391 static void alx_free_txring_buf(struct alx_priv *alx)
392 {
393 struct alx_tx_queue *txq = &alx->txq;
394 int i;
395
396 if (!txq->bufs)
397 return;
398
399 for (i = 0; i < alx->tx_ringsz; i++)
400 alx_free_txbuf(alx, i);
401
402 memset(txq->bufs, 0, alx->tx_ringsz * sizeof(struct alx_buffer));
403 memset(txq->tpd, 0, alx->tx_ringsz * sizeof(struct alx_txd));
404 txq->write_idx = 0;
405 txq->read_idx = 0;
406
407 netdev_reset_queue(alx->dev);
408 }
409
alx_free_rxring_buf(struct alx_priv * alx)410 static void alx_free_rxring_buf(struct alx_priv *alx)
411 {
412 struct alx_rx_queue *rxq = &alx->rxq;
413 struct alx_buffer *cur_buf;
414 u16 i;
415
416 if (rxq == NULL)
417 return;
418
419 for (i = 0; i < alx->rx_ringsz; i++) {
420 cur_buf = rxq->bufs + i;
421 if (cur_buf->skb) {
422 dma_unmap_single(&alx->hw.pdev->dev,
423 dma_unmap_addr(cur_buf, dma),
424 dma_unmap_len(cur_buf, size),
425 DMA_FROM_DEVICE);
426 dev_kfree_skb(cur_buf->skb);
427 cur_buf->skb = NULL;
428 dma_unmap_len_set(cur_buf, size, 0);
429 dma_unmap_addr_set(cur_buf, dma, 0);
430 }
431 }
432
433 rxq->write_idx = 0;
434 rxq->read_idx = 0;
435 rxq->rrd_read_idx = 0;
436 }
437
alx_free_buffers(struct alx_priv * alx)438 static void alx_free_buffers(struct alx_priv *alx)
439 {
440 alx_free_txring_buf(alx);
441 alx_free_rxring_buf(alx);
442 }
443
alx_reinit_rings(struct alx_priv * alx)444 static int alx_reinit_rings(struct alx_priv *alx)
445 {
446 alx_free_buffers(alx);
447
448 alx_init_ring_ptrs(alx);
449
450 if (!alx_refill_rx_ring(alx, GFP_KERNEL))
451 return -ENOMEM;
452
453 return 0;
454 }
455
alx_add_mc_addr(struct alx_hw * hw,const u8 * addr,u32 * mc_hash)456 static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash)
457 {
458 u32 crc32, bit, reg;
459
460 crc32 = ether_crc(ETH_ALEN, addr);
461 reg = (crc32 >> 31) & 0x1;
462 bit = (crc32 >> 26) & 0x1F;
463
464 mc_hash[reg] |= BIT(bit);
465 }
466
__alx_set_rx_mode(struct net_device * netdev)467 static void __alx_set_rx_mode(struct net_device *netdev)
468 {
469 struct alx_priv *alx = netdev_priv(netdev);
470 struct alx_hw *hw = &alx->hw;
471 struct netdev_hw_addr *ha;
472 u32 mc_hash[2] = {};
473
474 if (!(netdev->flags & IFF_ALLMULTI)) {
475 netdev_for_each_mc_addr(ha, netdev)
476 alx_add_mc_addr(hw, ha->addr, mc_hash);
477
478 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]);
479 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]);
480 }
481
482 hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
483 if (netdev->flags & IFF_PROMISC)
484 hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
485 if (netdev->flags & IFF_ALLMULTI)
486 hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
487
488 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
489 }
490
alx_set_rx_mode(struct net_device * netdev)491 static void alx_set_rx_mode(struct net_device *netdev)
492 {
493 __alx_set_rx_mode(netdev);
494 }
495
alx_set_mac_address(struct net_device * netdev,void * data)496 static int alx_set_mac_address(struct net_device *netdev, void *data)
497 {
498 struct alx_priv *alx = netdev_priv(netdev);
499 struct alx_hw *hw = &alx->hw;
500 struct sockaddr *addr = data;
501
502 if (!is_valid_ether_addr(addr->sa_data))
503 return -EADDRNOTAVAIL;
504
505 if (netdev->addr_assign_type & NET_ADDR_RANDOM)
506 netdev->addr_assign_type ^= NET_ADDR_RANDOM;
507
508 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
509 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
510 alx_set_macaddr(hw, hw->mac_addr);
511
512 return 0;
513 }
514
alx_alloc_descriptors(struct alx_priv * alx)515 static int alx_alloc_descriptors(struct alx_priv *alx)
516 {
517 alx->txq.bufs = kcalloc(alx->tx_ringsz,
518 sizeof(struct alx_buffer),
519 GFP_KERNEL);
520 if (!alx->txq.bufs)
521 return -ENOMEM;
522
523 alx->rxq.bufs = kcalloc(alx->rx_ringsz,
524 sizeof(struct alx_buffer),
525 GFP_KERNEL);
526 if (!alx->rxq.bufs)
527 goto out_free;
528
529 /* physical tx/rx ring descriptors
530 *
531 * Allocate them as a single chunk because they must not cross a
532 * 4G boundary (hardware has a single register for high 32 bits
533 * of addresses only)
534 */
535 alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz +
536 sizeof(struct alx_rrd) * alx->rx_ringsz +
537 sizeof(struct alx_rfd) * alx->rx_ringsz;
538 alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev,
539 alx->descmem.size,
540 &alx->descmem.dma,
541 GFP_KERNEL);
542 if (!alx->descmem.virt)
543 goto out_free;
544
545 alx->txq.tpd = alx->descmem.virt;
546 alx->txq.tpd_dma = alx->descmem.dma;
547
548 /* alignment requirement for next block */
549 BUILD_BUG_ON(sizeof(struct alx_txd) % 8);
550
551 alx->rxq.rrd =
552 (void *)((u8 *)alx->descmem.virt +
553 sizeof(struct alx_txd) * alx->tx_ringsz);
554 alx->rxq.rrd_dma = alx->descmem.dma +
555 sizeof(struct alx_txd) * alx->tx_ringsz;
556
557 /* alignment requirement for next block */
558 BUILD_BUG_ON(sizeof(struct alx_rrd) % 8);
559
560 alx->rxq.rfd =
561 (void *)((u8 *)alx->descmem.virt +
562 sizeof(struct alx_txd) * alx->tx_ringsz +
563 sizeof(struct alx_rrd) * alx->rx_ringsz);
564 alx->rxq.rfd_dma = alx->descmem.dma +
565 sizeof(struct alx_txd) * alx->tx_ringsz +
566 sizeof(struct alx_rrd) * alx->rx_ringsz;
567
568 return 0;
569 out_free:
570 kfree(alx->txq.bufs);
571 kfree(alx->rxq.bufs);
572 return -ENOMEM;
573 }
574
alx_alloc_rings(struct alx_priv * alx)575 static int alx_alloc_rings(struct alx_priv *alx)
576 {
577 int err;
578
579 err = alx_alloc_descriptors(alx);
580 if (err)
581 return err;
582
583 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
584 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
585 alx->tx_ringsz = alx->tx_ringsz;
586
587 netif_napi_add(alx->dev, &alx->napi, alx_poll, 64);
588
589 alx_reinit_rings(alx);
590 return 0;
591 }
592
alx_free_rings(struct alx_priv * alx)593 static void alx_free_rings(struct alx_priv *alx)
594 {
595 netif_napi_del(&alx->napi);
596 alx_free_buffers(alx);
597
598 kfree(alx->txq.bufs);
599 kfree(alx->rxq.bufs);
600
601 dma_free_coherent(&alx->hw.pdev->dev,
602 alx->descmem.size,
603 alx->descmem.virt,
604 alx->descmem.dma);
605 }
606
alx_config_vector_mapping(struct alx_priv * alx)607 static void alx_config_vector_mapping(struct alx_priv *alx)
608 {
609 struct alx_hw *hw = &alx->hw;
610
611 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, 0);
612 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, 0);
613 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0);
614 }
615
alx_irq_enable(struct alx_priv * alx)616 static void alx_irq_enable(struct alx_priv *alx)
617 {
618 struct alx_hw *hw = &alx->hw;
619
620 /* level-1 interrupt switch */
621 alx_write_mem32(hw, ALX_ISR, 0);
622 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
623 alx_post_write(hw);
624 }
625
alx_irq_disable(struct alx_priv * alx)626 static void alx_irq_disable(struct alx_priv *alx)
627 {
628 struct alx_hw *hw = &alx->hw;
629
630 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
631 alx_write_mem32(hw, ALX_IMR, 0);
632 alx_post_write(hw);
633
634 synchronize_irq(alx->hw.pdev->irq);
635 }
636
alx_request_irq(struct alx_priv * alx)637 static int alx_request_irq(struct alx_priv *alx)
638 {
639 struct pci_dev *pdev = alx->hw.pdev;
640 struct alx_hw *hw = &alx->hw;
641 int err;
642 u32 msi_ctrl;
643
644 msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT;
645
646 if (!pci_enable_msi(alx->hw.pdev)) {
647 alx->msi = true;
648
649 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER,
650 msi_ctrl | ALX_MSI_MASK_SEL_LINE);
651 err = request_irq(pdev->irq, alx_intr_msi, 0,
652 alx->dev->name, alx);
653 if (!err)
654 goto out;
655 /* fall back to legacy interrupt */
656 pci_disable_msi(alx->hw.pdev);
657 }
658
659 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0);
660 err = request_irq(pdev->irq, alx_intr_legacy, IRQF_SHARED,
661 alx->dev->name, alx);
662 out:
663 if (!err)
664 alx_config_vector_mapping(alx);
665 return err;
666 }
667
alx_free_irq(struct alx_priv * alx)668 static void alx_free_irq(struct alx_priv *alx)
669 {
670 struct pci_dev *pdev = alx->hw.pdev;
671
672 free_irq(pdev->irq, alx);
673
674 if (alx->msi) {
675 pci_disable_msi(alx->hw.pdev);
676 alx->msi = false;
677 }
678 }
679
alx_identify_hw(struct alx_priv * alx)680 static int alx_identify_hw(struct alx_priv *alx)
681 {
682 struct alx_hw *hw = &alx->hw;
683 int rev = alx_hw_revision(hw);
684
685 if (rev > ALX_REV_C0)
686 return -EINVAL;
687
688 hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2;
689
690 return 0;
691 }
692
alx_init_sw(struct alx_priv * alx)693 static int alx_init_sw(struct alx_priv *alx)
694 {
695 struct pci_dev *pdev = alx->hw.pdev;
696 struct alx_hw *hw = &alx->hw;
697 int err;
698
699 err = alx_identify_hw(alx);
700 if (err) {
701 dev_err(&pdev->dev, "unrecognized chip, aborting\n");
702 return err;
703 }
704
705 alx->hw.lnk_patch =
706 pdev->device == ALX_DEV_ID_AR8161 &&
707 pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC &&
708 pdev->subsystem_device == 0x0091 &&
709 pdev->revision == 0;
710
711 hw->smb_timer = 400;
712 hw->mtu = alx->dev->mtu;
713 alx->rxbuf_size = ALIGN(ALX_RAW_MTU(hw->mtu), 8);
714 alx->tx_ringsz = 256;
715 alx->rx_ringsz = 512;
716 hw->imt = 200;
717 alx->int_mask = ALX_ISR_MISC;
718 hw->dma_chnl = hw->max_dma_chnl;
719 hw->ith_tpd = alx->tx_ringsz / 3;
720 hw->link_speed = SPEED_UNKNOWN;
721 hw->duplex = DUPLEX_UNKNOWN;
722 hw->adv_cfg = ADVERTISED_Autoneg |
723 ADVERTISED_10baseT_Half |
724 ADVERTISED_10baseT_Full |
725 ADVERTISED_100baseT_Full |
726 ADVERTISED_100baseT_Half |
727 ADVERTISED_1000baseT_Full;
728 hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
729
730 hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
731 ALX_MAC_CTRL_MHASH_ALG_HI5B |
732 ALX_MAC_CTRL_BRD_EN |
733 ALX_MAC_CTRL_PCRCE |
734 ALX_MAC_CTRL_CRCE |
735 ALX_MAC_CTRL_RXFC_EN |
736 ALX_MAC_CTRL_TXFC_EN |
737 7 << ALX_MAC_CTRL_PRMBLEN_SHIFT;
738
739 return err;
740 }
741
742
alx_fix_features(struct net_device * netdev,netdev_features_t features)743 static netdev_features_t alx_fix_features(struct net_device *netdev,
744 netdev_features_t features)
745 {
746 if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE)
747 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
748
749 return features;
750 }
751
alx_netif_stop(struct alx_priv * alx)752 static void alx_netif_stop(struct alx_priv *alx)
753 {
754 alx->dev->trans_start = jiffies;
755 if (netif_carrier_ok(alx->dev)) {
756 netif_carrier_off(alx->dev);
757 netif_tx_disable(alx->dev);
758 napi_disable(&alx->napi);
759 }
760 }
761
alx_halt(struct alx_priv * alx)762 static void alx_halt(struct alx_priv *alx)
763 {
764 struct alx_hw *hw = &alx->hw;
765
766 alx_netif_stop(alx);
767 hw->link_speed = SPEED_UNKNOWN;
768 hw->duplex = DUPLEX_UNKNOWN;
769
770 alx_reset_mac(hw);
771
772 /* disable l0s/l1 */
773 alx_enable_aspm(hw, false, false);
774 alx_irq_disable(alx);
775 alx_free_buffers(alx);
776 }
777
alx_configure(struct alx_priv * alx)778 static void alx_configure(struct alx_priv *alx)
779 {
780 struct alx_hw *hw = &alx->hw;
781
782 alx_configure_basic(hw);
783 alx_disable_rss(hw);
784 __alx_set_rx_mode(alx->dev);
785
786 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
787 }
788
alx_activate(struct alx_priv * alx)789 static void alx_activate(struct alx_priv *alx)
790 {
791 /* hardware setting lost, restore it */
792 alx_reinit_rings(alx);
793 alx_configure(alx);
794
795 /* clear old interrupts */
796 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
797
798 alx_irq_enable(alx);
799
800 alx_schedule_link_check(alx);
801 }
802
alx_reinit(struct alx_priv * alx)803 static void alx_reinit(struct alx_priv *alx)
804 {
805 ASSERT_RTNL();
806
807 alx_halt(alx);
808 alx_activate(alx);
809 }
810
alx_change_mtu(struct net_device * netdev,int mtu)811 static int alx_change_mtu(struct net_device *netdev, int mtu)
812 {
813 struct alx_priv *alx = netdev_priv(netdev);
814 int max_frame = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
815
816 if ((max_frame < ALX_MIN_FRAME_SIZE) ||
817 (max_frame > ALX_MAX_FRAME_SIZE))
818 return -EINVAL;
819
820 if (netdev->mtu == mtu)
821 return 0;
822
823 netdev->mtu = mtu;
824 alx->hw.mtu = mtu;
825 alx->rxbuf_size = mtu > ALX_DEF_RXBUF_SIZE ?
826 ALIGN(max_frame, 8) : ALX_DEF_RXBUF_SIZE;
827 netdev_update_features(netdev);
828 if (netif_running(netdev))
829 alx_reinit(alx);
830 return 0;
831 }
832
alx_netif_start(struct alx_priv * alx)833 static void alx_netif_start(struct alx_priv *alx)
834 {
835 netif_tx_wake_all_queues(alx->dev);
836 napi_enable(&alx->napi);
837 netif_carrier_on(alx->dev);
838 }
839
__alx_open(struct alx_priv * alx,bool resume)840 static int __alx_open(struct alx_priv *alx, bool resume)
841 {
842 int err;
843
844 if (!resume)
845 netif_carrier_off(alx->dev);
846
847 err = alx_alloc_rings(alx);
848 if (err)
849 return err;
850
851 alx_configure(alx);
852
853 err = alx_request_irq(alx);
854 if (err)
855 goto out_free_rings;
856
857 /* clear old interrupts */
858 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
859
860 alx_irq_enable(alx);
861
862 if (!resume)
863 netif_tx_start_all_queues(alx->dev);
864
865 alx_schedule_link_check(alx);
866 return 0;
867
868 out_free_rings:
869 alx_free_rings(alx);
870 return err;
871 }
872
__alx_stop(struct alx_priv * alx)873 static void __alx_stop(struct alx_priv *alx)
874 {
875 alx_free_irq(alx);
876
877 cancel_work_sync(&alx->link_check_wk);
878 cancel_work_sync(&alx->reset_wk);
879
880 alx_halt(alx);
881 alx_free_rings(alx);
882 }
883
alx_speed_desc(struct alx_hw * hw)884 static const char *alx_speed_desc(struct alx_hw *hw)
885 {
886 switch (alx_speed_to_ethadv(hw->link_speed, hw->duplex)) {
887 case ADVERTISED_1000baseT_Full:
888 return "1 Gbps Full";
889 case ADVERTISED_100baseT_Full:
890 return "100 Mbps Full";
891 case ADVERTISED_100baseT_Half:
892 return "100 Mbps Half";
893 case ADVERTISED_10baseT_Full:
894 return "10 Mbps Full";
895 case ADVERTISED_10baseT_Half:
896 return "10 Mbps Half";
897 default:
898 return "Unknown speed";
899 }
900 }
901
alx_check_link(struct alx_priv * alx)902 static void alx_check_link(struct alx_priv *alx)
903 {
904 struct alx_hw *hw = &alx->hw;
905 unsigned long flags;
906 int old_speed;
907 u8 old_duplex;
908 int err;
909
910 /* clear PHY internal interrupt status, otherwise the main
911 * interrupt status will be asserted forever
912 */
913 alx_clear_phy_intr(hw);
914
915 old_speed = hw->link_speed;
916 old_duplex = hw->duplex;
917 err = alx_read_phy_link(hw);
918 if (err < 0)
919 goto reset;
920
921 spin_lock_irqsave(&alx->irq_lock, flags);
922 alx->int_mask |= ALX_ISR_PHY;
923 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
924 spin_unlock_irqrestore(&alx->irq_lock, flags);
925
926 if (old_speed == hw->link_speed)
927 return;
928
929 if (hw->link_speed != SPEED_UNKNOWN) {
930 netif_info(alx, link, alx->dev,
931 "NIC Up: %s\n", alx_speed_desc(hw));
932 alx_post_phy_link(hw);
933 alx_enable_aspm(hw, true, true);
934 alx_start_mac(hw);
935
936 if (old_speed == SPEED_UNKNOWN)
937 alx_netif_start(alx);
938 } else {
939 /* link is now down */
940 alx_netif_stop(alx);
941 netif_info(alx, link, alx->dev, "Link Down\n");
942 err = alx_reset_mac(hw);
943 if (err)
944 goto reset;
945 alx_irq_disable(alx);
946
947 /* MAC reset causes all HW settings to be lost, restore all */
948 err = alx_reinit_rings(alx);
949 if (err)
950 goto reset;
951 alx_configure(alx);
952 alx_enable_aspm(hw, false, true);
953 alx_post_phy_link(hw);
954 alx_irq_enable(alx);
955 }
956
957 return;
958
959 reset:
960 alx_schedule_reset(alx);
961 }
962
alx_open(struct net_device * netdev)963 static int alx_open(struct net_device *netdev)
964 {
965 return __alx_open(netdev_priv(netdev), false);
966 }
967
alx_stop(struct net_device * netdev)968 static int alx_stop(struct net_device *netdev)
969 {
970 __alx_stop(netdev_priv(netdev));
971 return 0;
972 }
973
alx_link_check(struct work_struct * work)974 static void alx_link_check(struct work_struct *work)
975 {
976 struct alx_priv *alx;
977
978 alx = container_of(work, struct alx_priv, link_check_wk);
979
980 rtnl_lock();
981 alx_check_link(alx);
982 rtnl_unlock();
983 }
984
alx_reset(struct work_struct * work)985 static void alx_reset(struct work_struct *work)
986 {
987 struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk);
988
989 rtnl_lock();
990 alx_reinit(alx);
991 rtnl_unlock();
992 }
993
alx_tx_csum(struct sk_buff * skb,struct alx_txd * first)994 static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first)
995 {
996 u8 cso, css;
997
998 if (skb->ip_summed != CHECKSUM_PARTIAL)
999 return 0;
1000
1001 cso = skb_checksum_start_offset(skb);
1002 if (cso & 1)
1003 return -EINVAL;
1004
1005 css = cso + skb->csum_offset;
1006 first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT);
1007 first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT);
1008 first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT);
1009
1010 return 0;
1011 }
1012
alx_map_tx_skb(struct alx_priv * alx,struct sk_buff * skb)1013 static int alx_map_tx_skb(struct alx_priv *alx, struct sk_buff *skb)
1014 {
1015 struct alx_tx_queue *txq = &alx->txq;
1016 struct alx_txd *tpd, *first_tpd;
1017 dma_addr_t dma;
1018 int maplen, f, first_idx = txq->write_idx;
1019
1020 first_tpd = &txq->tpd[txq->write_idx];
1021 tpd = first_tpd;
1022
1023 maplen = skb_headlen(skb);
1024 dma = dma_map_single(&alx->hw.pdev->dev, skb->data, maplen,
1025 DMA_TO_DEVICE);
1026 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1027 goto err_dma;
1028
1029 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1030 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1031
1032 tpd->adrl.addr = cpu_to_le64(dma);
1033 tpd->len = cpu_to_le16(maplen);
1034
1035 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
1036 struct skb_frag_struct *frag;
1037
1038 frag = &skb_shinfo(skb)->frags[f];
1039
1040 if (++txq->write_idx == alx->tx_ringsz)
1041 txq->write_idx = 0;
1042 tpd = &txq->tpd[txq->write_idx];
1043
1044 tpd->word1 = first_tpd->word1;
1045
1046 maplen = skb_frag_size(frag);
1047 dma = skb_frag_dma_map(&alx->hw.pdev->dev, frag, 0,
1048 maplen, DMA_TO_DEVICE);
1049 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1050 goto err_dma;
1051 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1052 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1053
1054 tpd->adrl.addr = cpu_to_le64(dma);
1055 tpd->len = cpu_to_le16(maplen);
1056 }
1057
1058 /* last TPD, set EOP flag and store skb */
1059 tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT);
1060 txq->bufs[txq->write_idx].skb = skb;
1061
1062 if (++txq->write_idx == alx->tx_ringsz)
1063 txq->write_idx = 0;
1064
1065 return 0;
1066
1067 err_dma:
1068 f = first_idx;
1069 while (f != txq->write_idx) {
1070 alx_free_txbuf(alx, f);
1071 if (++f == alx->tx_ringsz)
1072 f = 0;
1073 }
1074 return -ENOMEM;
1075 }
1076
alx_start_xmit(struct sk_buff * skb,struct net_device * netdev)1077 static netdev_tx_t alx_start_xmit(struct sk_buff *skb,
1078 struct net_device *netdev)
1079 {
1080 struct alx_priv *alx = netdev_priv(netdev);
1081 struct alx_tx_queue *txq = &alx->txq;
1082 struct alx_txd *first;
1083 int tpdreq = skb_shinfo(skb)->nr_frags + 1;
1084
1085 if (alx_tpd_avail(alx) < tpdreq) {
1086 netif_stop_queue(alx->dev);
1087 goto drop;
1088 }
1089
1090 first = &txq->tpd[txq->write_idx];
1091 memset(first, 0, sizeof(*first));
1092
1093 if (alx_tx_csum(skb, first))
1094 goto drop;
1095
1096 if (alx_map_tx_skb(alx, skb) < 0)
1097 goto drop;
1098
1099 netdev_sent_queue(alx->dev, skb->len);
1100
1101 /* flush updates before updating hardware */
1102 wmb();
1103 alx_write_mem16(&alx->hw, ALX_TPD_PRI0_PIDX, txq->write_idx);
1104
1105 if (alx_tpd_avail(alx) < alx->tx_ringsz/8)
1106 netif_stop_queue(alx->dev);
1107
1108 return NETDEV_TX_OK;
1109
1110 drop:
1111 dev_kfree_skb_any(skb);
1112 return NETDEV_TX_OK;
1113 }
1114
alx_tx_timeout(struct net_device * dev)1115 static void alx_tx_timeout(struct net_device *dev)
1116 {
1117 struct alx_priv *alx = netdev_priv(dev);
1118
1119 alx_schedule_reset(alx);
1120 }
1121
alx_mdio_read(struct net_device * netdev,int prtad,int devad,u16 addr)1122 static int alx_mdio_read(struct net_device *netdev,
1123 int prtad, int devad, u16 addr)
1124 {
1125 struct alx_priv *alx = netdev_priv(netdev);
1126 struct alx_hw *hw = &alx->hw;
1127 u16 val;
1128 int err;
1129
1130 if (prtad != hw->mdio.prtad)
1131 return -EINVAL;
1132
1133 if (devad == MDIO_DEVAD_NONE)
1134 err = alx_read_phy_reg(hw, addr, &val);
1135 else
1136 err = alx_read_phy_ext(hw, devad, addr, &val);
1137
1138 if (err)
1139 return err;
1140 return val;
1141 }
1142
alx_mdio_write(struct net_device * netdev,int prtad,int devad,u16 addr,u16 val)1143 static int alx_mdio_write(struct net_device *netdev,
1144 int prtad, int devad, u16 addr, u16 val)
1145 {
1146 struct alx_priv *alx = netdev_priv(netdev);
1147 struct alx_hw *hw = &alx->hw;
1148
1149 if (prtad != hw->mdio.prtad)
1150 return -EINVAL;
1151
1152 if (devad == MDIO_DEVAD_NONE)
1153 return alx_write_phy_reg(hw, addr, val);
1154
1155 return alx_write_phy_ext(hw, devad, addr, val);
1156 }
1157
alx_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)1158 static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1159 {
1160 struct alx_priv *alx = netdev_priv(netdev);
1161
1162 if (!netif_running(netdev))
1163 return -EAGAIN;
1164
1165 return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd);
1166 }
1167
1168 #ifdef CONFIG_NET_POLL_CONTROLLER
alx_poll_controller(struct net_device * netdev)1169 static void alx_poll_controller(struct net_device *netdev)
1170 {
1171 struct alx_priv *alx = netdev_priv(netdev);
1172
1173 if (alx->msi)
1174 alx_intr_msi(0, alx);
1175 else
1176 alx_intr_legacy(0, alx);
1177 }
1178 #endif
1179
alx_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * net_stats)1180 static struct rtnl_link_stats64 *alx_get_stats64(struct net_device *dev,
1181 struct rtnl_link_stats64 *net_stats)
1182 {
1183 struct alx_priv *alx = netdev_priv(dev);
1184 struct alx_hw_stats *hw_stats = &alx->hw.stats;
1185
1186 spin_lock(&alx->stats_lock);
1187
1188 alx_update_hw_stats(&alx->hw);
1189
1190 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1191 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1192 net_stats->multicast = hw_stats->rx_mcast;
1193 net_stats->collisions = hw_stats->tx_single_col +
1194 hw_stats->tx_multi_col +
1195 hw_stats->tx_late_col +
1196 hw_stats->tx_abort_col;
1197
1198 net_stats->rx_errors = hw_stats->rx_frag +
1199 hw_stats->rx_fcs_err +
1200 hw_stats->rx_len_err +
1201 hw_stats->rx_ov_sz +
1202 hw_stats->rx_ov_rrd +
1203 hw_stats->rx_align_err +
1204 hw_stats->rx_ov_rxf;
1205
1206 net_stats->rx_fifo_errors = hw_stats->rx_ov_rxf;
1207 net_stats->rx_length_errors = hw_stats->rx_len_err;
1208 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1209 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1210 net_stats->rx_dropped = hw_stats->rx_ov_rrd;
1211
1212 net_stats->tx_errors = hw_stats->tx_late_col +
1213 hw_stats->tx_abort_col +
1214 hw_stats->tx_underrun +
1215 hw_stats->tx_trunc;
1216
1217 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1218 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1219 net_stats->tx_window_errors = hw_stats->tx_late_col;
1220
1221 net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
1222 net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
1223
1224 spin_unlock(&alx->stats_lock);
1225
1226 return net_stats;
1227 }
1228
1229 static const struct net_device_ops alx_netdev_ops = {
1230 .ndo_open = alx_open,
1231 .ndo_stop = alx_stop,
1232 .ndo_start_xmit = alx_start_xmit,
1233 .ndo_get_stats64 = alx_get_stats64,
1234 .ndo_set_rx_mode = alx_set_rx_mode,
1235 .ndo_validate_addr = eth_validate_addr,
1236 .ndo_set_mac_address = alx_set_mac_address,
1237 .ndo_change_mtu = alx_change_mtu,
1238 .ndo_do_ioctl = alx_ioctl,
1239 .ndo_tx_timeout = alx_tx_timeout,
1240 .ndo_fix_features = alx_fix_features,
1241 #ifdef CONFIG_NET_POLL_CONTROLLER
1242 .ndo_poll_controller = alx_poll_controller,
1243 #endif
1244 };
1245
alx_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1246 static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1247 {
1248 struct net_device *netdev;
1249 struct alx_priv *alx;
1250 struct alx_hw *hw;
1251 bool phy_configured;
1252 int bars, err;
1253
1254 err = pci_enable_device_mem(pdev);
1255 if (err)
1256 return err;
1257
1258 /* The alx chip can DMA to 64-bit addresses, but it uses a single
1259 * shared register for the high 32 bits, so only a single, aligned,
1260 * 4 GB physical address range can be used for descriptors.
1261 */
1262 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
1263 dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
1264 } else {
1265 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1266 if (err) {
1267 dev_err(&pdev->dev, "No usable DMA config, aborting\n");
1268 goto out_pci_disable;
1269 }
1270 }
1271
1272 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1273 err = pci_request_selected_regions(pdev, bars, alx_drv_name);
1274 if (err) {
1275 dev_err(&pdev->dev,
1276 "pci_request_selected_regions failed(bars:%d)\n", bars);
1277 goto out_pci_disable;
1278 }
1279
1280 pci_enable_pcie_error_reporting(pdev);
1281 pci_set_master(pdev);
1282
1283 if (!pdev->pm_cap) {
1284 dev_err(&pdev->dev,
1285 "Can't find power management capability, aborting\n");
1286 err = -EIO;
1287 goto out_pci_release;
1288 }
1289
1290 netdev = alloc_etherdev(sizeof(*alx));
1291 if (!netdev) {
1292 err = -ENOMEM;
1293 goto out_pci_release;
1294 }
1295
1296 SET_NETDEV_DEV(netdev, &pdev->dev);
1297 alx = netdev_priv(netdev);
1298 spin_lock_init(&alx->hw.mdio_lock);
1299 spin_lock_init(&alx->irq_lock);
1300 spin_lock_init(&alx->stats_lock);
1301 alx->dev = netdev;
1302 alx->hw.pdev = pdev;
1303 alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP |
1304 NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL;
1305 hw = &alx->hw;
1306 pci_set_drvdata(pdev, alx);
1307
1308 hw->hw_addr = pci_ioremap_bar(pdev, 0);
1309 if (!hw->hw_addr) {
1310 dev_err(&pdev->dev, "cannot map device registers\n");
1311 err = -EIO;
1312 goto out_free_netdev;
1313 }
1314
1315 netdev->netdev_ops = &alx_netdev_ops;
1316 netdev->ethtool_ops = &alx_ethtool_ops;
1317 netdev->irq = pdev->irq;
1318 netdev->watchdog_timeo = ALX_WATCHDOG_TIME;
1319
1320 if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG)
1321 pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1322
1323 err = alx_init_sw(alx);
1324 if (err) {
1325 dev_err(&pdev->dev, "net device private data init failed\n");
1326 goto out_unmap;
1327 }
1328
1329 alx_reset_pcie(hw);
1330
1331 phy_configured = alx_phy_configured(hw);
1332
1333 if (!phy_configured)
1334 alx_reset_phy(hw);
1335
1336 err = alx_reset_mac(hw);
1337 if (err) {
1338 dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err);
1339 goto out_unmap;
1340 }
1341
1342 /* setup link to put it in a known good starting state */
1343 if (!phy_configured) {
1344 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
1345 if (err) {
1346 dev_err(&pdev->dev,
1347 "failed to configure PHY speed/duplex (err=%d)\n",
1348 err);
1349 goto out_unmap;
1350 }
1351 }
1352
1353 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
1354
1355 if (alx_get_perm_macaddr(hw, hw->perm_addr)) {
1356 dev_warn(&pdev->dev,
1357 "Invalid permanent address programmed, using random one\n");
1358 eth_hw_addr_random(netdev);
1359 memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len);
1360 }
1361
1362 memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN);
1363 memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN);
1364 memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN);
1365
1366 hw->mdio.prtad = 0;
1367 hw->mdio.mmds = 0;
1368 hw->mdio.dev = netdev;
1369 hw->mdio.mode_support = MDIO_SUPPORTS_C45 |
1370 MDIO_SUPPORTS_C22 |
1371 MDIO_EMULATE_C22;
1372 hw->mdio.mdio_read = alx_mdio_read;
1373 hw->mdio.mdio_write = alx_mdio_write;
1374
1375 if (!alx_get_phy_info(hw)) {
1376 dev_err(&pdev->dev, "failed to identify PHY\n");
1377 err = -EIO;
1378 goto out_unmap;
1379 }
1380
1381 INIT_WORK(&alx->link_check_wk, alx_link_check);
1382 INIT_WORK(&alx->reset_wk, alx_reset);
1383 netif_carrier_off(netdev);
1384
1385 err = register_netdev(netdev);
1386 if (err) {
1387 dev_err(&pdev->dev, "register netdevice failed\n");
1388 goto out_unmap;
1389 }
1390
1391 netdev_info(netdev,
1392 "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n",
1393 netdev->dev_addr);
1394
1395 return 0;
1396
1397 out_unmap:
1398 iounmap(hw->hw_addr);
1399 out_free_netdev:
1400 free_netdev(netdev);
1401 out_pci_release:
1402 pci_release_selected_regions(pdev, bars);
1403 out_pci_disable:
1404 pci_disable_device(pdev);
1405 return err;
1406 }
1407
alx_remove(struct pci_dev * pdev)1408 static void alx_remove(struct pci_dev *pdev)
1409 {
1410 struct alx_priv *alx = pci_get_drvdata(pdev);
1411 struct alx_hw *hw = &alx->hw;
1412
1413 /* restore permanent mac address */
1414 alx_set_macaddr(hw, hw->perm_addr);
1415
1416 unregister_netdev(alx->dev);
1417 iounmap(hw->hw_addr);
1418 pci_release_selected_regions(pdev,
1419 pci_select_bars(pdev, IORESOURCE_MEM));
1420
1421 pci_disable_pcie_error_reporting(pdev);
1422 pci_disable_device(pdev);
1423
1424 free_netdev(alx->dev);
1425 }
1426
1427 #ifdef CONFIG_PM_SLEEP
alx_suspend(struct device * dev)1428 static int alx_suspend(struct device *dev)
1429 {
1430 struct pci_dev *pdev = to_pci_dev(dev);
1431 struct alx_priv *alx = pci_get_drvdata(pdev);
1432
1433 if (!netif_running(alx->dev))
1434 return 0;
1435 netif_device_detach(alx->dev);
1436 __alx_stop(alx);
1437 return 0;
1438 }
1439
alx_resume(struct device * dev)1440 static int alx_resume(struct device *dev)
1441 {
1442 struct pci_dev *pdev = to_pci_dev(dev);
1443 struct alx_priv *alx = pci_get_drvdata(pdev);
1444 struct alx_hw *hw = &alx->hw;
1445
1446 alx_reset_phy(hw);
1447
1448 if (!netif_running(alx->dev))
1449 return 0;
1450 netif_device_attach(alx->dev);
1451 return __alx_open(alx, true);
1452 }
1453
1454 static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
1455 #define ALX_PM_OPS (&alx_pm_ops)
1456 #else
1457 #define ALX_PM_OPS NULL
1458 #endif
1459
1460
alx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)1461 static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev,
1462 pci_channel_state_t state)
1463 {
1464 struct alx_priv *alx = pci_get_drvdata(pdev);
1465 struct net_device *netdev = alx->dev;
1466 pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET;
1467
1468 dev_info(&pdev->dev, "pci error detected\n");
1469
1470 rtnl_lock();
1471
1472 if (netif_running(netdev)) {
1473 netif_device_detach(netdev);
1474 alx_halt(alx);
1475 }
1476
1477 if (state == pci_channel_io_perm_failure)
1478 rc = PCI_ERS_RESULT_DISCONNECT;
1479 else
1480 pci_disable_device(pdev);
1481
1482 rtnl_unlock();
1483
1484 return rc;
1485 }
1486
alx_pci_error_slot_reset(struct pci_dev * pdev)1487 static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
1488 {
1489 struct alx_priv *alx = pci_get_drvdata(pdev);
1490 struct alx_hw *hw = &alx->hw;
1491 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
1492
1493 dev_info(&pdev->dev, "pci error slot reset\n");
1494
1495 rtnl_lock();
1496
1497 if (pci_enable_device(pdev)) {
1498 dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n");
1499 goto out;
1500 }
1501
1502 pci_set_master(pdev);
1503
1504 alx_reset_pcie(hw);
1505 if (!alx_reset_mac(hw))
1506 rc = PCI_ERS_RESULT_RECOVERED;
1507 out:
1508 pci_cleanup_aer_uncorrect_error_status(pdev);
1509
1510 rtnl_unlock();
1511
1512 return rc;
1513 }
1514
alx_pci_error_resume(struct pci_dev * pdev)1515 static void alx_pci_error_resume(struct pci_dev *pdev)
1516 {
1517 struct alx_priv *alx = pci_get_drvdata(pdev);
1518 struct net_device *netdev = alx->dev;
1519
1520 dev_info(&pdev->dev, "pci error resume\n");
1521
1522 rtnl_lock();
1523
1524 if (netif_running(netdev)) {
1525 alx_activate(alx);
1526 netif_device_attach(netdev);
1527 }
1528
1529 rtnl_unlock();
1530 }
1531
1532 static const struct pci_error_handlers alx_err_handlers = {
1533 .error_detected = alx_pci_error_detected,
1534 .slot_reset = alx_pci_error_slot_reset,
1535 .resume = alx_pci_error_resume,
1536 };
1537
1538 static const struct pci_device_id alx_pci_tbl[] = {
1539 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161),
1540 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1541 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200),
1542 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1543 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2400),
1544 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1545 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162),
1546 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1547 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) },
1548 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) },
1549 {}
1550 };
1551
1552 static struct pci_driver alx_driver = {
1553 .name = alx_drv_name,
1554 .id_table = alx_pci_tbl,
1555 .probe = alx_probe,
1556 .remove = alx_remove,
1557 .err_handler = &alx_err_handlers,
1558 .driver.pm = ALX_PM_OPS,
1559 };
1560
1561 module_pci_driver(alx_driver);
1562 MODULE_DEVICE_TABLE(pci, alx_pci_tbl);
1563 MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
1564 MODULE_AUTHOR("Qualcomm Corporation, <nic-devel@qualcomm.com>");
1565 MODULE_DESCRIPTION(
1566 "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver");
1567 MODULE_LICENSE("GPL");
1568