1 /*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9 #include "bgmac.h"
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/bcm47xx_nvram.h>
21
22 static const struct bcma_device_id bgmac_bcma_tbl[] = {
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
25 {},
26 };
27 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
28
bgmac_wait_value(struct bcma_device * core,u16 reg,u32 mask,u32 value,int timeout)29 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
30 u32 value, int timeout)
31 {
32 u32 val;
33 int i;
34
35 for (i = 0; i < timeout / 10; i++) {
36 val = bcma_read32(core, reg);
37 if ((val & mask) == value)
38 return true;
39 udelay(10);
40 }
41 pr_err("Timeout waiting for reg 0x%X\n", reg);
42 return false;
43 }
44
45 /**************************************************
46 * DMA
47 **************************************************/
48
bgmac_dma_tx_reset(struct bgmac * bgmac,struct bgmac_dma_ring * ring)49 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
50 {
51 u32 val;
52 int i;
53
54 if (!ring->mmio_base)
55 return;
56
57 /* Suspend DMA TX ring first.
58 * bgmac_wait_value doesn't support waiting for any of few values, so
59 * implement whole loop here.
60 */
61 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
62 BGMAC_DMA_TX_SUSPEND);
63 for (i = 0; i < 10000 / 10; i++) {
64 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
65 val &= BGMAC_DMA_TX_STAT;
66 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
67 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
68 val == BGMAC_DMA_TX_STAT_STOPPED) {
69 i = 0;
70 break;
71 }
72 udelay(10);
73 }
74 if (i)
75 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
76 ring->mmio_base, val);
77
78 /* Remove SUSPEND bit */
79 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
80 if (!bgmac_wait_value(bgmac->core,
81 ring->mmio_base + BGMAC_DMA_TX_STATUS,
82 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
83 10000)) {
84 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
85 ring->mmio_base);
86 udelay(300);
87 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
88 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
89 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
90 ring->mmio_base);
91 }
92 }
93
bgmac_dma_tx_enable(struct bgmac * bgmac,struct bgmac_dma_ring * ring)94 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
95 struct bgmac_dma_ring *ring)
96 {
97 u32 ctl;
98
99 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
100 if (bgmac->core->id.rev >= 4) {
101 ctl &= ~BGMAC_DMA_TX_BL_MASK;
102 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
103
104 ctl &= ~BGMAC_DMA_TX_MR_MASK;
105 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
106
107 ctl &= ~BGMAC_DMA_TX_PC_MASK;
108 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
109
110 ctl &= ~BGMAC_DMA_TX_PT_MASK;
111 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
112 }
113 ctl |= BGMAC_DMA_TX_ENABLE;
114 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
115 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
116 }
117
118 static void
bgmac_dma_tx_add_buf(struct bgmac * bgmac,struct bgmac_dma_ring * ring,int i,int len,u32 ctl0)119 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
120 int i, int len, u32 ctl0)
121 {
122 struct bgmac_slot_info *slot;
123 struct bgmac_dma_desc *dma_desc;
124 u32 ctl1;
125
126 if (i == BGMAC_TX_RING_SLOTS - 1)
127 ctl0 |= BGMAC_DESC_CTL0_EOT;
128
129 ctl1 = len & BGMAC_DESC_CTL1_LEN;
130
131 slot = &ring->slots[i];
132 dma_desc = &ring->cpu_base[i];
133 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
134 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
135 dma_desc->ctl0 = cpu_to_le32(ctl0);
136 dma_desc->ctl1 = cpu_to_le32(ctl1);
137 }
138
bgmac_dma_tx_add(struct bgmac * bgmac,struct bgmac_dma_ring * ring,struct sk_buff * skb)139 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
140 struct bgmac_dma_ring *ring,
141 struct sk_buff *skb)
142 {
143 struct device *dma_dev = bgmac->core->dma_dev;
144 struct net_device *net_dev = bgmac->net_dev;
145 int index = ring->end % BGMAC_TX_RING_SLOTS;
146 struct bgmac_slot_info *slot = &ring->slots[index];
147 int nr_frags;
148 u32 flags;
149 int i;
150
151 if (skb->len > BGMAC_DESC_CTL1_LEN) {
152 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
153 goto err_drop;
154 }
155
156 if (skb->ip_summed == CHECKSUM_PARTIAL)
157 skb_checksum_help(skb);
158
159 nr_frags = skb_shinfo(skb)->nr_frags;
160
161 /* ring->end - ring->start will return the number of valid slots,
162 * even when ring->end overflows
163 */
164 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
165 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
166 netif_stop_queue(net_dev);
167 return NETDEV_TX_BUSY;
168 }
169
170 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
171 DMA_TO_DEVICE);
172 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
173 goto err_dma_head;
174
175 flags = BGMAC_DESC_CTL0_SOF;
176 if (!nr_frags)
177 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
178
179 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
180 flags = 0;
181
182 for (i = 0; i < nr_frags; i++) {
183 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
184 int len = skb_frag_size(frag);
185
186 index = (index + 1) % BGMAC_TX_RING_SLOTS;
187 slot = &ring->slots[index];
188 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
189 len, DMA_TO_DEVICE);
190 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
191 goto err_dma;
192
193 if (i == nr_frags - 1)
194 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
195
196 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
197 }
198
199 slot->skb = skb;
200 ring->end += nr_frags + 1;
201 netdev_sent_queue(net_dev, skb->len);
202
203 wmb();
204
205 /* Increase ring->end to point empty slot. We tell hardware the first
206 * slot it should *not* read.
207 */
208 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
209 ring->index_base +
210 (ring->end % BGMAC_TX_RING_SLOTS) *
211 sizeof(struct bgmac_dma_desc));
212
213 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
214 netif_stop_queue(net_dev);
215
216 return NETDEV_TX_OK;
217
218 err_dma:
219 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
220 DMA_TO_DEVICE);
221
222 while (i-- > 0) {
223 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
224 struct bgmac_slot_info *slot = &ring->slots[index];
225 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
226 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
227
228 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
229 }
230
231 err_dma_head:
232 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
233 ring->mmio_base);
234
235 err_drop:
236 dev_kfree_skb(skb);
237 return NETDEV_TX_OK;
238 }
239
240 /* Free transmitted packets */
bgmac_dma_tx_free(struct bgmac * bgmac,struct bgmac_dma_ring * ring)241 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
242 {
243 struct device *dma_dev = bgmac->core->dma_dev;
244 int empty_slot;
245 bool freed = false;
246 unsigned bytes_compl = 0, pkts_compl = 0;
247
248 /* The last slot that hardware didn't consume yet */
249 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
250 empty_slot &= BGMAC_DMA_TX_STATDPTR;
251 empty_slot -= ring->index_base;
252 empty_slot &= BGMAC_DMA_TX_STATDPTR;
253 empty_slot /= sizeof(struct bgmac_dma_desc);
254
255 while (ring->start != ring->end) {
256 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
257 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
258 u32 ctl0, ctl1;
259 int len;
260
261 if (slot_idx == empty_slot)
262 break;
263
264 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
265 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
266 len = ctl1 & BGMAC_DESC_CTL1_LEN;
267 if (ctl0 & BGMAC_DESC_CTL0_SOF)
268 /* Unmap no longer used buffer */
269 dma_unmap_single(dma_dev, slot->dma_addr, len,
270 DMA_TO_DEVICE);
271 else
272 dma_unmap_page(dma_dev, slot->dma_addr, len,
273 DMA_TO_DEVICE);
274
275 if (slot->skb) {
276 bytes_compl += slot->skb->len;
277 pkts_compl++;
278
279 /* Free memory! :) */
280 dev_kfree_skb(slot->skb);
281 slot->skb = NULL;
282 }
283
284 slot->dma_addr = 0;
285 ring->start++;
286 freed = true;
287 }
288
289 if (!pkts_compl)
290 return;
291
292 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
293
294 if (netif_queue_stopped(bgmac->net_dev))
295 netif_wake_queue(bgmac->net_dev);
296 }
297
bgmac_dma_rx_reset(struct bgmac * bgmac,struct bgmac_dma_ring * ring)298 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
299 {
300 if (!ring->mmio_base)
301 return;
302
303 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
304 if (!bgmac_wait_value(bgmac->core,
305 ring->mmio_base + BGMAC_DMA_RX_STATUS,
306 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
307 10000))
308 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
309 ring->mmio_base);
310 }
311
bgmac_dma_rx_enable(struct bgmac * bgmac,struct bgmac_dma_ring * ring)312 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
313 struct bgmac_dma_ring *ring)
314 {
315 u32 ctl;
316
317 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
318
319 /* preserve ONLY bits 16-17 from current hardware value */
320 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
321
322 if (bgmac->core->id.rev >= 4) {
323 ctl &= ~BGMAC_DMA_RX_BL_MASK;
324 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
325
326 ctl &= ~BGMAC_DMA_RX_PC_MASK;
327 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
328
329 ctl &= ~BGMAC_DMA_RX_PT_MASK;
330 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
331 }
332 ctl |= BGMAC_DMA_RX_ENABLE;
333 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
334 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
335 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
336 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
337 }
338
bgmac_dma_rx_skb_for_slot(struct bgmac * bgmac,struct bgmac_slot_info * slot)339 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
340 struct bgmac_slot_info *slot)
341 {
342 struct device *dma_dev = bgmac->core->dma_dev;
343 dma_addr_t dma_addr;
344 struct bgmac_rx_header *rx;
345 void *buf;
346
347 /* Alloc skb */
348 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
349 if (!buf)
350 return -ENOMEM;
351
352 /* Poison - if everything goes fine, hardware will overwrite it */
353 rx = buf + BGMAC_RX_BUF_OFFSET;
354 rx->len = cpu_to_le16(0xdead);
355 rx->flags = cpu_to_le16(0xbeef);
356
357 /* Map skb for the DMA */
358 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
359 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
360 if (dma_mapping_error(dma_dev, dma_addr)) {
361 bgmac_err(bgmac, "DMA mapping error\n");
362 put_page(virt_to_head_page(buf));
363 return -ENOMEM;
364 }
365
366 /* Update the slot */
367 slot->buf = buf;
368 slot->dma_addr = dma_addr;
369
370 return 0;
371 }
372
bgmac_dma_rx_update_index(struct bgmac * bgmac,struct bgmac_dma_ring * ring)373 static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
374 struct bgmac_dma_ring *ring)
375 {
376 dma_wmb();
377
378 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
379 ring->index_base +
380 ring->end * sizeof(struct bgmac_dma_desc));
381 }
382
bgmac_dma_rx_setup_desc(struct bgmac * bgmac,struct bgmac_dma_ring * ring,int desc_idx)383 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
384 struct bgmac_dma_ring *ring, int desc_idx)
385 {
386 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
387 u32 ctl0 = 0, ctl1 = 0;
388
389 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
390 ctl0 |= BGMAC_DESC_CTL0_EOT;
391 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
392 /* Is there any BGMAC device that requires extension? */
393 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
394 * B43_DMA64_DCTL1_ADDREXT_MASK;
395 */
396
397 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
398 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
399 dma_desc->ctl0 = cpu_to_le32(ctl0);
400 dma_desc->ctl1 = cpu_to_le32(ctl1);
401
402 ring->end = desc_idx;
403 }
404
bgmac_dma_rx_poison_buf(struct device * dma_dev,struct bgmac_slot_info * slot)405 static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
406 struct bgmac_slot_info *slot)
407 {
408 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
409
410 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
411 DMA_FROM_DEVICE);
412 rx->len = cpu_to_le16(0xdead);
413 rx->flags = cpu_to_le16(0xbeef);
414 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
415 DMA_FROM_DEVICE);
416 }
417
bgmac_dma_rx_read(struct bgmac * bgmac,struct bgmac_dma_ring * ring,int weight)418 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
419 int weight)
420 {
421 u32 end_slot;
422 int handled = 0;
423
424 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
425 end_slot &= BGMAC_DMA_RX_STATDPTR;
426 end_slot -= ring->index_base;
427 end_slot &= BGMAC_DMA_RX_STATDPTR;
428 end_slot /= sizeof(struct bgmac_dma_desc);
429
430 while (ring->start != end_slot) {
431 struct device *dma_dev = bgmac->core->dma_dev;
432 struct bgmac_slot_info *slot = &ring->slots[ring->start];
433 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
434 struct sk_buff *skb;
435 void *buf = slot->buf;
436 dma_addr_t dma_addr = slot->dma_addr;
437 u16 len, flags;
438
439 do {
440 /* Prepare new skb as replacement */
441 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
442 bgmac_dma_rx_poison_buf(dma_dev, slot);
443 break;
444 }
445
446 /* Unmap buffer to make it accessible to the CPU */
447 dma_unmap_single(dma_dev, dma_addr,
448 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
449
450 /* Get info from the header */
451 len = le16_to_cpu(rx->len);
452 flags = le16_to_cpu(rx->flags);
453
454 /* Check for poison and drop or pass the packet */
455 if (len == 0xdead && flags == 0xbeef) {
456 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
457 ring->start);
458 put_page(virt_to_head_page(buf));
459 break;
460 }
461
462 if (len > BGMAC_RX_ALLOC_SIZE) {
463 bgmac_err(bgmac, "Found oversized packet at slot %d, DMA issue!\n",
464 ring->start);
465 put_page(virt_to_head_page(buf));
466 break;
467 }
468
469 /* Omit CRC. */
470 len -= ETH_FCS_LEN;
471
472 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
473 if (unlikely(!skb)) {
474 bgmac_err(bgmac, "build_skb failed\n");
475 put_page(virt_to_head_page(buf));
476 break;
477 }
478 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
479 BGMAC_RX_BUF_OFFSET + len);
480 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
481 BGMAC_RX_BUF_OFFSET);
482
483 skb_checksum_none_assert(skb);
484 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
485 napi_gro_receive(&bgmac->napi, skb);
486 handled++;
487 } while (0);
488
489 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
490
491 if (++ring->start >= BGMAC_RX_RING_SLOTS)
492 ring->start = 0;
493
494 if (handled >= weight) /* Should never be greater */
495 break;
496 }
497
498 bgmac_dma_rx_update_index(bgmac, ring);
499
500 return handled;
501 }
502
503 /* Does ring support unaligned addressing? */
bgmac_dma_unaligned(struct bgmac * bgmac,struct bgmac_dma_ring * ring,enum bgmac_dma_ring_type ring_type)504 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
505 struct bgmac_dma_ring *ring,
506 enum bgmac_dma_ring_type ring_type)
507 {
508 switch (ring_type) {
509 case BGMAC_DMA_RING_TX:
510 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
511 0xff0);
512 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
513 return true;
514 break;
515 case BGMAC_DMA_RING_RX:
516 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
517 0xff0);
518 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
519 return true;
520 break;
521 }
522 return false;
523 }
524
bgmac_dma_tx_ring_free(struct bgmac * bgmac,struct bgmac_dma_ring * ring)525 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
526 struct bgmac_dma_ring *ring)
527 {
528 struct device *dma_dev = bgmac->core->dma_dev;
529 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
530 struct bgmac_slot_info *slot;
531 int i;
532
533 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
534 u32 ctl1 = le32_to_cpu(dma_desc[i].ctl1);
535 unsigned int len = ctl1 & BGMAC_DESC_CTL1_LEN;
536
537 slot = &ring->slots[i];
538 dev_kfree_skb(slot->skb);
539
540 if (!slot->dma_addr)
541 continue;
542
543 if (slot->skb)
544 dma_unmap_single(dma_dev, slot->dma_addr,
545 len, DMA_TO_DEVICE);
546 else
547 dma_unmap_page(dma_dev, slot->dma_addr,
548 len, DMA_TO_DEVICE);
549 }
550 }
551
bgmac_dma_rx_ring_free(struct bgmac * bgmac,struct bgmac_dma_ring * ring)552 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
553 struct bgmac_dma_ring *ring)
554 {
555 struct device *dma_dev = bgmac->core->dma_dev;
556 struct bgmac_slot_info *slot;
557 int i;
558
559 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
560 slot = &ring->slots[i];
561 if (!slot->dma_addr)
562 continue;
563
564 dma_unmap_single(dma_dev, slot->dma_addr,
565 BGMAC_RX_BUF_SIZE,
566 DMA_FROM_DEVICE);
567 put_page(virt_to_head_page(slot->buf));
568 slot->dma_addr = 0;
569 }
570 }
571
bgmac_dma_ring_desc_free(struct bgmac * bgmac,struct bgmac_dma_ring * ring,int num_slots)572 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
573 struct bgmac_dma_ring *ring,
574 int num_slots)
575 {
576 struct device *dma_dev = bgmac->core->dma_dev;
577 int size;
578
579 if (!ring->cpu_base)
580 return;
581
582 /* Free ring of descriptors */
583 size = num_slots * sizeof(struct bgmac_dma_desc);
584 dma_free_coherent(dma_dev, size, ring->cpu_base,
585 ring->dma_base);
586 }
587
bgmac_dma_cleanup(struct bgmac * bgmac)588 static void bgmac_dma_cleanup(struct bgmac *bgmac)
589 {
590 int i;
591
592 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
593 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
594
595 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
596 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
597 }
598
bgmac_dma_free(struct bgmac * bgmac)599 static void bgmac_dma_free(struct bgmac *bgmac)
600 {
601 int i;
602
603 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
604 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
605 BGMAC_TX_RING_SLOTS);
606
607 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
608 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
609 BGMAC_RX_RING_SLOTS);
610 }
611
bgmac_dma_alloc(struct bgmac * bgmac)612 static int bgmac_dma_alloc(struct bgmac *bgmac)
613 {
614 struct device *dma_dev = bgmac->core->dma_dev;
615 struct bgmac_dma_ring *ring;
616 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
617 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
618 int size; /* ring size: different for Tx and Rx */
619 int err;
620 int i;
621
622 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
623 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
624
625 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
626 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
627 return -ENOTSUPP;
628 }
629
630 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
631 ring = &bgmac->tx_ring[i];
632 ring->mmio_base = ring_base[i];
633
634 /* Alloc ring of descriptors */
635 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
636 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
637 &ring->dma_base,
638 GFP_KERNEL);
639 if (!ring->cpu_base) {
640 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
641 ring->mmio_base);
642 goto err_dma_free;
643 }
644
645 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
646 BGMAC_DMA_RING_TX);
647 if (ring->unaligned)
648 ring->index_base = lower_32_bits(ring->dma_base);
649 else
650 ring->index_base = 0;
651
652 /* No need to alloc TX slots yet */
653 }
654
655 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
656 ring = &bgmac->rx_ring[i];
657 ring->mmio_base = ring_base[i];
658
659 /* Alloc ring of descriptors */
660 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
661 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
662 &ring->dma_base,
663 GFP_KERNEL);
664 if (!ring->cpu_base) {
665 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
666 ring->mmio_base);
667 err = -ENOMEM;
668 goto err_dma_free;
669 }
670
671 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
672 BGMAC_DMA_RING_RX);
673 if (ring->unaligned)
674 ring->index_base = lower_32_bits(ring->dma_base);
675 else
676 ring->index_base = 0;
677 }
678
679 return 0;
680
681 err_dma_free:
682 bgmac_dma_free(bgmac);
683 return -ENOMEM;
684 }
685
bgmac_dma_init(struct bgmac * bgmac)686 static int bgmac_dma_init(struct bgmac *bgmac)
687 {
688 struct bgmac_dma_ring *ring;
689 int i, err;
690
691 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
692 ring = &bgmac->tx_ring[i];
693
694 if (!ring->unaligned)
695 bgmac_dma_tx_enable(bgmac, ring);
696 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
697 lower_32_bits(ring->dma_base));
698 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
699 upper_32_bits(ring->dma_base));
700 if (ring->unaligned)
701 bgmac_dma_tx_enable(bgmac, ring);
702
703 ring->start = 0;
704 ring->end = 0; /* Points the slot that should *not* be read */
705 }
706
707 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
708 int j;
709
710 ring = &bgmac->rx_ring[i];
711
712 if (!ring->unaligned)
713 bgmac_dma_rx_enable(bgmac, ring);
714 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
715 lower_32_bits(ring->dma_base));
716 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
717 upper_32_bits(ring->dma_base));
718 if (ring->unaligned)
719 bgmac_dma_rx_enable(bgmac, ring);
720
721 ring->start = 0;
722 ring->end = 0;
723 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
724 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
725 if (err)
726 goto error;
727
728 bgmac_dma_rx_setup_desc(bgmac, ring, j);
729 }
730
731 bgmac_dma_rx_update_index(bgmac, ring);
732 }
733
734 return 0;
735
736 error:
737 bgmac_dma_cleanup(bgmac);
738 return err;
739 }
740
741 /**************************************************
742 * PHY ops
743 **************************************************/
744
bgmac_phy_read(struct bgmac * bgmac,u8 phyaddr,u8 reg)745 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
746 {
747 struct bcma_device *core;
748 u16 phy_access_addr;
749 u16 phy_ctl_addr;
750 u32 tmp;
751
752 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
753 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
754 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
755 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
756 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
757 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
758 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
759 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
760 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
761 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
762 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
763
764 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
765 core = bgmac->core->bus->drv_gmac_cmn.core;
766 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
767 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
768 } else {
769 core = bgmac->core;
770 phy_access_addr = BGMAC_PHY_ACCESS;
771 phy_ctl_addr = BGMAC_PHY_CNTL;
772 }
773
774 tmp = bcma_read32(core, phy_ctl_addr);
775 tmp &= ~BGMAC_PC_EPA_MASK;
776 tmp |= phyaddr;
777 bcma_write32(core, phy_ctl_addr, tmp);
778
779 tmp = BGMAC_PA_START;
780 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
781 tmp |= reg << BGMAC_PA_REG_SHIFT;
782 bcma_write32(core, phy_access_addr, tmp);
783
784 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
785 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
786 phyaddr, reg);
787 return 0xffff;
788 }
789
790 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
791 }
792
793 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
bgmac_phy_write(struct bgmac * bgmac,u8 phyaddr,u8 reg,u16 value)794 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
795 {
796 struct bcma_device *core;
797 u16 phy_access_addr;
798 u16 phy_ctl_addr;
799 u32 tmp;
800
801 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
802 core = bgmac->core->bus->drv_gmac_cmn.core;
803 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
804 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
805 } else {
806 core = bgmac->core;
807 phy_access_addr = BGMAC_PHY_ACCESS;
808 phy_ctl_addr = BGMAC_PHY_CNTL;
809 }
810
811 tmp = bcma_read32(core, phy_ctl_addr);
812 tmp &= ~BGMAC_PC_EPA_MASK;
813 tmp |= phyaddr;
814 bcma_write32(core, phy_ctl_addr, tmp);
815
816 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
817 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
818 bgmac_warn(bgmac, "Error setting MDIO int\n");
819
820 tmp = BGMAC_PA_START;
821 tmp |= BGMAC_PA_WRITE;
822 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
823 tmp |= reg << BGMAC_PA_REG_SHIFT;
824 tmp |= value;
825 bcma_write32(core, phy_access_addr, tmp);
826
827 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
828 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
829 phyaddr, reg);
830 return -ETIMEDOUT;
831 }
832
833 return 0;
834 }
835
836 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
bgmac_phy_init(struct bgmac * bgmac)837 static void bgmac_phy_init(struct bgmac *bgmac)
838 {
839 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
840 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
841 u8 i;
842
843 if (ci->id == BCMA_CHIP_ID_BCM5356) {
844 for (i = 0; i < 5; i++) {
845 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
846 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
847 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
848 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
849 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
850 }
851 }
852 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
853 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
854 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
855 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
856 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
857 for (i = 0; i < 5; i++) {
858 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
859 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
860 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
861 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
862 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
863 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
864 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
865 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
866 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
867 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
868 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
869 }
870 }
871 }
872
873 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
bgmac_phy_reset(struct bgmac * bgmac)874 static void bgmac_phy_reset(struct bgmac *bgmac)
875 {
876 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
877 return;
878
879 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
880 udelay(100);
881 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
882 bgmac_err(bgmac, "PHY reset failed\n");
883 bgmac_phy_init(bgmac);
884 }
885
886 /**************************************************
887 * Chip ops
888 **************************************************/
889
890 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
891 * nothing to change? Try if after stabilizng driver.
892 */
bgmac_cmdcfg_maskset(struct bgmac * bgmac,u32 mask,u32 set,bool force)893 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
894 bool force)
895 {
896 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
897 u32 new_val = (cmdcfg & mask) | set;
898
899 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
900 udelay(2);
901
902 if (new_val != cmdcfg || force)
903 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
904
905 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
906 udelay(2);
907 }
908
bgmac_write_mac_address(struct bgmac * bgmac,u8 * addr)909 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
910 {
911 u32 tmp;
912
913 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
914 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
915 tmp = (addr[4] << 8) | addr[5];
916 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
917 }
918
bgmac_set_rx_mode(struct net_device * net_dev)919 static void bgmac_set_rx_mode(struct net_device *net_dev)
920 {
921 struct bgmac *bgmac = netdev_priv(net_dev);
922
923 if (net_dev->flags & IFF_PROMISC)
924 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
925 else
926 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
927 }
928
929 #if 0 /* We don't use that regs yet */
930 static void bgmac_chip_stats_update(struct bgmac *bgmac)
931 {
932 int i;
933
934 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
935 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
936 bgmac->mib_tx_regs[i] =
937 bgmac_read(bgmac,
938 BGMAC_TX_GOOD_OCTETS + (i * 4));
939 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
940 bgmac->mib_rx_regs[i] =
941 bgmac_read(bgmac,
942 BGMAC_RX_GOOD_OCTETS + (i * 4));
943 }
944
945 /* TODO: what else? how to handle BCM4706? Specs are needed */
946 }
947 #endif
948
bgmac_clear_mib(struct bgmac * bgmac)949 static void bgmac_clear_mib(struct bgmac *bgmac)
950 {
951 int i;
952
953 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
954 return;
955
956 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
957 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
958 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
959 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
960 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
961 }
962
963 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
bgmac_mac_speed(struct bgmac * bgmac)964 static void bgmac_mac_speed(struct bgmac *bgmac)
965 {
966 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
967 u32 set = 0;
968
969 switch (bgmac->mac_speed) {
970 case SPEED_10:
971 set |= BGMAC_CMDCFG_ES_10;
972 break;
973 case SPEED_100:
974 set |= BGMAC_CMDCFG_ES_100;
975 break;
976 case SPEED_1000:
977 set |= BGMAC_CMDCFG_ES_1000;
978 break;
979 case SPEED_2500:
980 set |= BGMAC_CMDCFG_ES_2500;
981 break;
982 default:
983 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
984 }
985
986 if (bgmac->mac_duplex == DUPLEX_HALF)
987 set |= BGMAC_CMDCFG_HD;
988
989 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
990 }
991
bgmac_miiconfig(struct bgmac * bgmac)992 static void bgmac_miiconfig(struct bgmac *bgmac)
993 {
994 struct bcma_device *core = bgmac->core;
995 struct bcma_chipinfo *ci = &core->bus->chipinfo;
996 u8 imode;
997
998 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
999 ci->id == BCMA_CHIP_ID_BCM53018) {
1000 bcma_awrite32(core, BCMA_IOCTL,
1001 bcma_aread32(core, BCMA_IOCTL) | 0x40 |
1002 BGMAC_BCMA_IOCTL_SW_CLKEN);
1003 bgmac->mac_speed = SPEED_2500;
1004 bgmac->mac_duplex = DUPLEX_FULL;
1005 bgmac_mac_speed(bgmac);
1006 } else {
1007 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
1008 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
1009 if (imode == 0 || imode == 1) {
1010 bgmac->mac_speed = SPEED_100;
1011 bgmac->mac_duplex = DUPLEX_FULL;
1012 bgmac_mac_speed(bgmac);
1013 }
1014 }
1015 }
1016
1017 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
bgmac_chip_reset(struct bgmac * bgmac)1018 static void bgmac_chip_reset(struct bgmac *bgmac)
1019 {
1020 struct bcma_device *core = bgmac->core;
1021 struct bcma_bus *bus = core->bus;
1022 struct bcma_chipinfo *ci = &bus->chipinfo;
1023 u32 flags;
1024 u32 iost;
1025 int i;
1026
1027 if (bcma_core_is_enabled(core)) {
1028 if (!bgmac->stats_grabbed) {
1029 /* bgmac_chip_stats_update(bgmac); */
1030 bgmac->stats_grabbed = true;
1031 }
1032
1033 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
1034 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
1035
1036 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1037 udelay(1);
1038
1039 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
1040 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
1041
1042 /* TODO: Clear software multicast filter list */
1043 }
1044
1045 iost = bcma_aread32(core, BCMA_IOST);
1046 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1047 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1048 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
1049 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
1050
1051 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
1052 if (ci->id != BCMA_CHIP_ID_BCM4707) {
1053 flags = 0;
1054 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
1055 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
1056 if (!bgmac->has_robosw)
1057 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
1058 }
1059 bcma_core_enable(core, flags);
1060 }
1061
1062 /* Request Misc PLL for corerev > 2 */
1063 if (core->id.rev > 2 &&
1064 ci->id != BCMA_CHIP_ID_BCM4707 &&
1065 ci->id != BCMA_CHIP_ID_BCM53018) {
1066 bgmac_set(bgmac, BCMA_CLKCTLST,
1067 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
1068 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
1069 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1070 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1071 1000);
1072 }
1073
1074 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1075 ci->id == BCMA_CHIP_ID_BCM4749 ||
1076 ci->id == BCMA_CHIP_ID_BCM53572) {
1077 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
1078 u8 et_swtype = 0;
1079 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
1080 BGMAC_CHIPCTL_1_IF_TYPE_MII;
1081 char buf[4];
1082
1083 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
1084 if (kstrtou8(buf, 0, &et_swtype))
1085 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
1086 buf);
1087 et_swtype &= 0x0f;
1088 et_swtype <<= 4;
1089 sw_type = et_swtype;
1090 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
1091 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
1092 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1093 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1094 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
1095 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
1096 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
1097 }
1098 bcma_chipco_chipctl_maskset(cc, 1,
1099 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
1100 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
1101 sw_type);
1102 }
1103
1104 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
1105 bcma_awrite32(core, BCMA_IOCTL,
1106 bcma_aread32(core, BCMA_IOCTL) &
1107 ~BGMAC_BCMA_IOCTL_SW_RESET);
1108
1109 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1110 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1111 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1112 * be keps until taking MAC out of the reset.
1113 */
1114 bgmac_cmdcfg_maskset(bgmac,
1115 ~(BGMAC_CMDCFG_TE |
1116 BGMAC_CMDCFG_RE |
1117 BGMAC_CMDCFG_RPI |
1118 BGMAC_CMDCFG_TAI |
1119 BGMAC_CMDCFG_HD |
1120 BGMAC_CMDCFG_ML |
1121 BGMAC_CMDCFG_CFE |
1122 BGMAC_CMDCFG_RL |
1123 BGMAC_CMDCFG_RED |
1124 BGMAC_CMDCFG_PE |
1125 BGMAC_CMDCFG_TPI |
1126 BGMAC_CMDCFG_PAD_EN |
1127 BGMAC_CMDCFG_PF),
1128 BGMAC_CMDCFG_PROM |
1129 BGMAC_CMDCFG_NLC |
1130 BGMAC_CMDCFG_CFE |
1131 BGMAC_CMDCFG_SR(core->id.rev),
1132 false);
1133 bgmac->mac_speed = SPEED_UNKNOWN;
1134 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1135
1136 bgmac_clear_mib(bgmac);
1137 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
1138 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
1139 BCMA_GMAC_CMN_PC_MTE);
1140 else
1141 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1142 bgmac_miiconfig(bgmac);
1143 bgmac_phy_init(bgmac);
1144
1145 netdev_reset_queue(bgmac->net_dev);
1146 }
1147
bgmac_chip_intrs_on(struct bgmac * bgmac)1148 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1149 {
1150 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1151 }
1152
bgmac_chip_intrs_off(struct bgmac * bgmac)1153 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1154 {
1155 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1156 bgmac_read(bgmac, BGMAC_INT_MASK);
1157 }
1158
1159 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
bgmac_enable(struct bgmac * bgmac)1160 static void bgmac_enable(struct bgmac *bgmac)
1161 {
1162 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1163 u32 cmdcfg;
1164 u32 mode;
1165 u32 rxq_ctl;
1166 u32 fl_ctl;
1167 u16 bp_clk;
1168 u8 mdp;
1169
1170 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1171 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1172 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
1173 udelay(2);
1174 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1175 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1176
1177 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1178 BGMAC_DS_MM_SHIFT;
1179 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1180 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1181 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1182 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1183 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1184
1185 switch (ci->id) {
1186 case BCMA_CHIP_ID_BCM5357:
1187 case BCMA_CHIP_ID_BCM4749:
1188 case BCMA_CHIP_ID_BCM53572:
1189 case BCMA_CHIP_ID_BCM4716:
1190 case BCMA_CHIP_ID_BCM47162:
1191 fl_ctl = 0x03cb04cb;
1192 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1193 ci->id == BCMA_CHIP_ID_BCM4749 ||
1194 ci->id == BCMA_CHIP_ID_BCM53572)
1195 fl_ctl = 0x2300e1;
1196 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1197 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1198 break;
1199 }
1200
1201 if (ci->id != BCMA_CHIP_ID_BCM4707 &&
1202 ci->id != BCMA_CHIP_ID_BCM53018) {
1203 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1204 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1205 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
1206 1000000;
1207 mdp = (bp_clk * 128 / 1000) - 3;
1208 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1209 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1210 }
1211 }
1212
1213 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
bgmac_chip_init(struct bgmac * bgmac)1214 static void bgmac_chip_init(struct bgmac *bgmac)
1215 {
1216 /* 1 interrupt per received frame */
1217 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1218
1219 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1220 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1221
1222 bgmac_set_rx_mode(bgmac->net_dev);
1223
1224 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1225
1226 if (bgmac->loopback)
1227 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1228 else
1229 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1230
1231 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1232
1233 bgmac_chip_intrs_on(bgmac);
1234
1235 bgmac_enable(bgmac);
1236 }
1237
bgmac_interrupt(int irq,void * dev_id)1238 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1239 {
1240 struct bgmac *bgmac = netdev_priv(dev_id);
1241
1242 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1243 int_status &= bgmac->int_mask;
1244
1245 if (!int_status)
1246 return IRQ_NONE;
1247
1248 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1249 if (int_status)
1250 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status);
1251
1252 /* Disable new interrupts until handling existing ones */
1253 bgmac_chip_intrs_off(bgmac);
1254
1255 napi_schedule(&bgmac->napi);
1256
1257 return IRQ_HANDLED;
1258 }
1259
bgmac_poll(struct napi_struct * napi,int weight)1260 static int bgmac_poll(struct napi_struct *napi, int weight)
1261 {
1262 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1263 int handled = 0;
1264
1265 /* Ack */
1266 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1267
1268 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1269 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1270
1271 /* Poll again if more events arrived in the meantime */
1272 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1273 return weight;
1274
1275 if (handled < weight) {
1276 napi_complete(napi);
1277 bgmac_chip_intrs_on(bgmac);
1278 }
1279
1280 return handled;
1281 }
1282
1283 /**************************************************
1284 * net_device_ops
1285 **************************************************/
1286
bgmac_open(struct net_device * net_dev)1287 static int bgmac_open(struct net_device *net_dev)
1288 {
1289 struct bgmac *bgmac = netdev_priv(net_dev);
1290 int err = 0;
1291
1292 bgmac_chip_reset(bgmac);
1293
1294 err = bgmac_dma_init(bgmac);
1295 if (err)
1296 return err;
1297
1298 /* Specs say about reclaiming rings here, but we do that in DMA init */
1299 bgmac_chip_init(bgmac);
1300
1301 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1302 KBUILD_MODNAME, net_dev);
1303 if (err < 0) {
1304 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
1305 bgmac_dma_cleanup(bgmac);
1306 return err;
1307 }
1308 napi_enable(&bgmac->napi);
1309
1310 phy_start(bgmac->phy_dev);
1311
1312 netif_start_queue(net_dev);
1313
1314 return 0;
1315 }
1316
bgmac_stop(struct net_device * net_dev)1317 static int bgmac_stop(struct net_device *net_dev)
1318 {
1319 struct bgmac *bgmac = netdev_priv(net_dev);
1320
1321 netif_carrier_off(net_dev);
1322
1323 phy_stop(bgmac->phy_dev);
1324
1325 napi_disable(&bgmac->napi);
1326 bgmac_chip_intrs_off(bgmac);
1327 free_irq(bgmac->core->irq, net_dev);
1328
1329 bgmac_chip_reset(bgmac);
1330 bgmac_dma_cleanup(bgmac);
1331
1332 return 0;
1333 }
1334
bgmac_start_xmit(struct sk_buff * skb,struct net_device * net_dev)1335 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1336 struct net_device *net_dev)
1337 {
1338 struct bgmac *bgmac = netdev_priv(net_dev);
1339 struct bgmac_dma_ring *ring;
1340
1341 /* No QOS support yet */
1342 ring = &bgmac->tx_ring[0];
1343 return bgmac_dma_tx_add(bgmac, ring, skb);
1344 }
1345
bgmac_set_mac_address(struct net_device * net_dev,void * addr)1346 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1347 {
1348 struct bgmac *bgmac = netdev_priv(net_dev);
1349 int ret;
1350
1351 ret = eth_prepare_mac_addr_change(net_dev, addr);
1352 if (ret < 0)
1353 return ret;
1354 bgmac_write_mac_address(bgmac, (u8 *)addr);
1355 eth_commit_mac_addr_change(net_dev, addr);
1356 return 0;
1357 }
1358
bgmac_ioctl(struct net_device * net_dev,struct ifreq * ifr,int cmd)1359 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1360 {
1361 struct bgmac *bgmac = netdev_priv(net_dev);
1362
1363 if (!netif_running(net_dev))
1364 return -EINVAL;
1365
1366 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
1367 }
1368
1369 static const struct net_device_ops bgmac_netdev_ops = {
1370 .ndo_open = bgmac_open,
1371 .ndo_stop = bgmac_stop,
1372 .ndo_start_xmit = bgmac_start_xmit,
1373 .ndo_set_rx_mode = bgmac_set_rx_mode,
1374 .ndo_set_mac_address = bgmac_set_mac_address,
1375 .ndo_validate_addr = eth_validate_addr,
1376 .ndo_do_ioctl = bgmac_ioctl,
1377 };
1378
1379 /**************************************************
1380 * ethtool_ops
1381 **************************************************/
1382
bgmac_get_settings(struct net_device * net_dev,struct ethtool_cmd * cmd)1383 static int bgmac_get_settings(struct net_device *net_dev,
1384 struct ethtool_cmd *cmd)
1385 {
1386 struct bgmac *bgmac = netdev_priv(net_dev);
1387
1388 return phy_ethtool_gset(bgmac->phy_dev, cmd);
1389 }
1390
bgmac_set_settings(struct net_device * net_dev,struct ethtool_cmd * cmd)1391 static int bgmac_set_settings(struct net_device *net_dev,
1392 struct ethtool_cmd *cmd)
1393 {
1394 struct bgmac *bgmac = netdev_priv(net_dev);
1395
1396 return phy_ethtool_sset(bgmac->phy_dev, cmd);
1397 }
1398
bgmac_get_drvinfo(struct net_device * net_dev,struct ethtool_drvinfo * info)1399 static void bgmac_get_drvinfo(struct net_device *net_dev,
1400 struct ethtool_drvinfo *info)
1401 {
1402 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1403 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1404 }
1405
1406 static const struct ethtool_ops bgmac_ethtool_ops = {
1407 .get_settings = bgmac_get_settings,
1408 .set_settings = bgmac_set_settings,
1409 .get_drvinfo = bgmac_get_drvinfo,
1410 };
1411
1412 /**************************************************
1413 * MII
1414 **************************************************/
1415
bgmac_mii_read(struct mii_bus * bus,int mii_id,int regnum)1416 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1417 {
1418 return bgmac_phy_read(bus->priv, mii_id, regnum);
1419 }
1420
bgmac_mii_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)1421 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1422 u16 value)
1423 {
1424 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1425 }
1426
bgmac_adjust_link(struct net_device * net_dev)1427 static void bgmac_adjust_link(struct net_device *net_dev)
1428 {
1429 struct bgmac *bgmac = netdev_priv(net_dev);
1430 struct phy_device *phy_dev = bgmac->phy_dev;
1431 bool update = false;
1432
1433 if (phy_dev->link) {
1434 if (phy_dev->speed != bgmac->mac_speed) {
1435 bgmac->mac_speed = phy_dev->speed;
1436 update = true;
1437 }
1438
1439 if (phy_dev->duplex != bgmac->mac_duplex) {
1440 bgmac->mac_duplex = phy_dev->duplex;
1441 update = true;
1442 }
1443 }
1444
1445 if (update) {
1446 bgmac_mac_speed(bgmac);
1447 phy_print_status(phy_dev);
1448 }
1449 }
1450
bgmac_fixed_phy_register(struct bgmac * bgmac)1451 static int bgmac_fixed_phy_register(struct bgmac *bgmac)
1452 {
1453 struct fixed_phy_status fphy_status = {
1454 .link = 1,
1455 .speed = SPEED_1000,
1456 .duplex = DUPLEX_FULL,
1457 };
1458 struct phy_device *phy_dev;
1459 int err;
1460
1461 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
1462 if (!phy_dev || IS_ERR(phy_dev)) {
1463 bgmac_err(bgmac, "Failed to register fixed PHY device\n");
1464 return -ENODEV;
1465 }
1466
1467 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1468 PHY_INTERFACE_MODE_MII);
1469 if (err) {
1470 bgmac_err(bgmac, "Connecting PHY failed\n");
1471 return err;
1472 }
1473
1474 bgmac->phy_dev = phy_dev;
1475
1476 return err;
1477 }
1478
bgmac_mii_register(struct bgmac * bgmac)1479 static int bgmac_mii_register(struct bgmac *bgmac)
1480 {
1481 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1482 struct mii_bus *mii_bus;
1483 struct phy_device *phy_dev;
1484 char bus_id[MII_BUS_ID_SIZE + 3];
1485 int i, err = 0;
1486
1487 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1488 ci->id == BCMA_CHIP_ID_BCM53018)
1489 return bgmac_fixed_phy_register(bgmac);
1490
1491 mii_bus = mdiobus_alloc();
1492 if (!mii_bus)
1493 return -ENOMEM;
1494
1495 mii_bus->name = "bgmac mii bus";
1496 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1497 bgmac->core->core_unit);
1498 mii_bus->priv = bgmac;
1499 mii_bus->read = bgmac_mii_read;
1500 mii_bus->write = bgmac_mii_write;
1501 mii_bus->parent = &bgmac->core->dev;
1502 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1503
1504 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1505 if (!mii_bus->irq) {
1506 err = -ENOMEM;
1507 goto err_free_bus;
1508 }
1509 for (i = 0; i < PHY_MAX_ADDR; i++)
1510 mii_bus->irq[i] = PHY_POLL;
1511
1512 err = mdiobus_register(mii_bus);
1513 if (err) {
1514 bgmac_err(bgmac, "Registration of mii bus failed\n");
1515 goto err_free_irq;
1516 }
1517
1518 bgmac->mii_bus = mii_bus;
1519
1520 /* Connect to the PHY */
1521 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
1522 bgmac->phyaddr);
1523 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1524 PHY_INTERFACE_MODE_MII);
1525 if (IS_ERR(phy_dev)) {
1526 bgmac_err(bgmac, "PHY connecton failed\n");
1527 err = PTR_ERR(phy_dev);
1528 goto err_unregister_bus;
1529 }
1530 bgmac->phy_dev = phy_dev;
1531
1532 return err;
1533
1534 err_unregister_bus:
1535 mdiobus_unregister(mii_bus);
1536 err_free_irq:
1537 kfree(mii_bus->irq);
1538 err_free_bus:
1539 mdiobus_free(mii_bus);
1540 return err;
1541 }
1542
bgmac_mii_unregister(struct bgmac * bgmac)1543 static void bgmac_mii_unregister(struct bgmac *bgmac)
1544 {
1545 struct mii_bus *mii_bus = bgmac->mii_bus;
1546
1547 mdiobus_unregister(mii_bus);
1548 kfree(mii_bus->irq);
1549 mdiobus_free(mii_bus);
1550 }
1551
1552 /**************************************************
1553 * BCMA bus ops
1554 **************************************************/
1555
1556 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
bgmac_probe(struct bcma_device * core)1557 static int bgmac_probe(struct bcma_device *core)
1558 {
1559 struct bcma_chipinfo *ci = &core->bus->chipinfo;
1560 struct net_device *net_dev;
1561 struct bgmac *bgmac;
1562 struct ssb_sprom *sprom = &core->bus->sprom;
1563 u8 *mac;
1564 int err;
1565
1566 switch (core->core_unit) {
1567 case 0:
1568 mac = sprom->et0mac;
1569 break;
1570 case 1:
1571 mac = sprom->et1mac;
1572 break;
1573 case 2:
1574 mac = sprom->et2mac;
1575 break;
1576 default:
1577 pr_err("Unsupported core_unit %d\n", core->core_unit);
1578 return -ENOTSUPP;
1579 }
1580
1581 if (!is_valid_ether_addr(mac)) {
1582 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1583 eth_random_addr(mac);
1584 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1585 }
1586
1587 /* This (reset &) enable is not preset in specs or reference driver but
1588 * Broadcom does it in arch PCI code when enabling fake PCI device.
1589 */
1590 bcma_core_enable(core, 0);
1591
1592 /* Allocation and references */
1593 net_dev = alloc_etherdev(sizeof(*bgmac));
1594 if (!net_dev)
1595 return -ENOMEM;
1596 net_dev->netdev_ops = &bgmac_netdev_ops;
1597 net_dev->irq = core->irq;
1598 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1599 bgmac = netdev_priv(net_dev);
1600 bgmac->net_dev = net_dev;
1601 bgmac->core = core;
1602 bcma_set_drvdata(core, bgmac);
1603
1604 /* Defaults */
1605 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1606
1607 /* On BCM4706 we need common core to access PHY */
1608 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1609 !core->bus->drv_gmac_cmn.core) {
1610 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1611 err = -ENODEV;
1612 goto err_netdev_free;
1613 }
1614 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1615
1616 switch (core->core_unit) {
1617 case 0:
1618 bgmac->phyaddr = sprom->et0phyaddr;
1619 break;
1620 case 1:
1621 bgmac->phyaddr = sprom->et1phyaddr;
1622 break;
1623 case 2:
1624 bgmac->phyaddr = sprom->et2phyaddr;
1625 break;
1626 }
1627 bgmac->phyaddr &= BGMAC_PHY_MASK;
1628 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1629 bgmac_err(bgmac, "No PHY found\n");
1630 err = -ENODEV;
1631 goto err_netdev_free;
1632 }
1633 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1634 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1635
1636 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1637 bgmac_err(bgmac, "PCI setup not implemented\n");
1638 err = -ENOTSUPP;
1639 goto err_netdev_free;
1640 }
1641
1642 bgmac_chip_reset(bgmac);
1643
1644 /* For Northstar, we have to take all GMAC core out of reset */
1645 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1646 ci->id == BCMA_CHIP_ID_BCM53018) {
1647 struct bcma_device *ns_core;
1648 int ns_gmac;
1649
1650 /* Northstar has 4 GMAC cores */
1651 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
1652 /* As Northstar requirement, we have to reset all GMACs
1653 * before accessing one. bgmac_chip_reset() call
1654 * bcma_core_enable() for this core. Then the other
1655 * three GMACs didn't reset. We do it here.
1656 */
1657 ns_core = bcma_find_core_unit(core->bus,
1658 BCMA_CORE_MAC_GBIT,
1659 ns_gmac);
1660 if (ns_core && !bcma_core_is_enabled(ns_core))
1661 bcma_core_enable(ns_core, 0);
1662 }
1663 }
1664
1665 err = bgmac_dma_alloc(bgmac);
1666 if (err) {
1667 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1668 goto err_netdev_free;
1669 }
1670
1671 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1672 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1673 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1674
1675 /* TODO: reset the external phy. Specs are needed */
1676 bgmac_phy_reset(bgmac);
1677
1678 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1679 BGMAC_BFL_ENETROBO);
1680 if (bgmac->has_robosw)
1681 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1682
1683 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1684 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1685
1686 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1687
1688 err = bgmac_mii_register(bgmac);
1689 if (err) {
1690 bgmac_err(bgmac, "Cannot register MDIO\n");
1691 goto err_dma_free;
1692 }
1693
1694 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1695 net_dev->hw_features = net_dev->features;
1696 net_dev->vlan_features = net_dev->features;
1697
1698 err = register_netdev(bgmac->net_dev);
1699 if (err) {
1700 bgmac_err(bgmac, "Cannot register net device\n");
1701 goto err_mii_unregister;
1702 }
1703
1704 netif_carrier_off(net_dev);
1705
1706 return 0;
1707
1708 err_mii_unregister:
1709 bgmac_mii_unregister(bgmac);
1710 err_dma_free:
1711 bgmac_dma_free(bgmac);
1712
1713 err_netdev_free:
1714 bcma_set_drvdata(core, NULL);
1715 free_netdev(net_dev);
1716
1717 return err;
1718 }
1719
bgmac_remove(struct bcma_device * core)1720 static void bgmac_remove(struct bcma_device *core)
1721 {
1722 struct bgmac *bgmac = bcma_get_drvdata(core);
1723
1724 unregister_netdev(bgmac->net_dev);
1725 bgmac_mii_unregister(bgmac);
1726 netif_napi_del(&bgmac->napi);
1727 bgmac_dma_free(bgmac);
1728 bcma_set_drvdata(core, NULL);
1729 free_netdev(bgmac->net_dev);
1730 }
1731
1732 static struct bcma_driver bgmac_bcma_driver = {
1733 .name = KBUILD_MODNAME,
1734 .id_table = bgmac_bcma_tbl,
1735 .probe = bgmac_probe,
1736 .remove = bgmac_remove,
1737 };
1738
bgmac_init(void)1739 static int __init bgmac_init(void)
1740 {
1741 int err;
1742
1743 err = bcma_driver_register(&bgmac_bcma_driver);
1744 if (err)
1745 return err;
1746 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1747
1748 return 0;
1749 }
1750
bgmac_exit(void)1751 static void __exit bgmac_exit(void)
1752 {
1753 bcma_driver_unregister(&bgmac_bcma_driver);
1754 }
1755
1756 module_init(bgmac_init)
1757 module_exit(bgmac_exit)
1758
1759 MODULE_AUTHOR("Rafał Miłecki");
1760 MODULE_LICENSE("GPL");
1761