1 /* bnx2x.h: QLogic Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 */
15
16 #ifndef BNX2X_H
17 #define BNX2X_H
18
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/types.h>
23 #include <linux/pci_regs.h>
24
25 #include <linux/ptp_clock_kernel.h>
26 #include <linux/net_tstamp.h>
27 #include <linux/timecounter.h>
28
29 /* compilation time flags */
30
31 /* define this to make the driver freeze on error to allow getting debug info
32 * (you will need to reboot afterwards) */
33 /* #define BNX2X_STOP_ON_ERROR */
34
35 #define DRV_MODULE_VERSION "1.712.30-0"
36 #define DRV_MODULE_RELDATE "2014/02/10"
37 #define BNX2X_BC_VER 0x040200
38
39 #if defined(CONFIG_DCB)
40 #define BCM_DCBNL
41 #endif
42
43 #include "bnx2x_hsi.h"
44
45 #include "../cnic_if.h"
46
47 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
48
49 #include <linux/mdio.h>
50
51 #include "bnx2x_reg.h"
52 #include "bnx2x_fw_defs.h"
53 #include "bnx2x_mfw_req.h"
54 #include "bnx2x_link.h"
55 #include "bnx2x_sp.h"
56 #include "bnx2x_dcb.h"
57 #include "bnx2x_stats.h"
58 #include "bnx2x_vfpf.h"
59
60 enum bnx2x_int_mode {
61 BNX2X_INT_MODE_MSIX,
62 BNX2X_INT_MODE_INTX,
63 BNX2X_INT_MODE_MSI
64 };
65
66 /* error/debug prints */
67
68 #define DRV_MODULE_NAME "bnx2x"
69
70 /* for messages that are currently off */
71 #define BNX2X_MSG_OFF 0x0
72 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
73 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
74 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
75 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
76 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
77 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
78 #define BNX2X_MSG_IOV 0x0800000
79 #define BNX2X_MSG_PTP 0x1000000
80 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
81 #define BNX2X_MSG_ETHTOOL 0x4000000
82 #define BNX2X_MSG_DCB 0x8000000
83
84 /* regular debug print */
85 #define DP_INNER(fmt, ...) \
86 pr_notice("[%s:%d(%s)]" fmt, \
87 __func__, __LINE__, \
88 bp->dev ? (bp->dev->name) : "?", \
89 ##__VA_ARGS__);
90
91 #define DP(__mask, fmt, ...) \
92 do { \
93 if (unlikely(bp->msg_enable & (__mask))) \
94 DP_INNER(fmt, ##__VA_ARGS__); \
95 } while (0)
96
97 #define DP_AND(__mask, fmt, ...) \
98 do { \
99 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \
100 DP_INNER(fmt, ##__VA_ARGS__); \
101 } while (0)
102
103 #define DP_CONT(__mask, fmt, ...) \
104 do { \
105 if (unlikely(bp->msg_enable & (__mask))) \
106 pr_cont(fmt, ##__VA_ARGS__); \
107 } while (0)
108
109 /* errors debug print */
110 #define BNX2X_DBG_ERR(fmt, ...) \
111 do { \
112 if (unlikely(netif_msg_probe(bp))) \
113 pr_err("[%s:%d(%s)]" fmt, \
114 __func__, __LINE__, \
115 bp->dev ? (bp->dev->name) : "?", \
116 ##__VA_ARGS__); \
117 } while (0)
118
119 /* for errors (never masked) */
120 #define BNX2X_ERR(fmt, ...) \
121 do { \
122 pr_err("[%s:%d(%s)]" fmt, \
123 __func__, __LINE__, \
124 bp->dev ? (bp->dev->name) : "?", \
125 ##__VA_ARGS__); \
126 } while (0)
127
128 #define BNX2X_ERROR(fmt, ...) \
129 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
130
131 /* before we have a dev->name use dev_info() */
132 #define BNX2X_DEV_INFO(fmt, ...) \
133 do { \
134 if (unlikely(netif_msg_probe(bp))) \
135 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
136 } while (0)
137
138 /* Error handling */
139 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
140 #ifdef BNX2X_STOP_ON_ERROR
141 #define bnx2x_panic() \
142 do { \
143 bp->panic = 1; \
144 BNX2X_ERR("driver assert\n"); \
145 bnx2x_panic_dump(bp, true); \
146 } while (0)
147 #else
148 #define bnx2x_panic() \
149 do { \
150 bp->panic = 1; \
151 BNX2X_ERR("driver assert\n"); \
152 bnx2x_panic_dump(bp, false); \
153 } while (0)
154 #endif
155
156 #define bnx2x_mc_addr(ha) ((ha)->addr)
157 #define bnx2x_uc_addr(ha) ((ha)->addr)
158
159 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
160 #define U64_HI(x) ((u32)(((u64)(x)) >> 32))
161 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
162
163 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
164
165 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
166 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
167 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
168
169 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
170 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
171 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
172
173 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
174 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
175
176 #define REG_RD_DMAE(bp, offset, valp, len32) \
177 do { \
178 bnx2x_read_dmae(bp, offset, len32);\
179 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
180 } while (0)
181
182 #define REG_WR_DMAE(bp, offset, valp, len32) \
183 do { \
184 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
185 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
186 offset, len32); \
187 } while (0)
188
189 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
190 REG_WR_DMAE(bp, offset, valp, len32)
191
192 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
193 do { \
194 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
195 bnx2x_write_big_buf_wb(bp, addr, len32); \
196 } while (0)
197
198 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
199 offsetof(struct shmem_region, field))
200 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
201 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
202
203 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
204 offsetof(struct shmem2_region, field))
205 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
206 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
207 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
208 offsetof(struct mf_cfg, field))
209 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
210 offsetof(struct mf2_cfg, field))
211
212 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
213 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
214 MF_CFG_ADDR(bp, field), (val))
215 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
216
217 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
218 (SHMEM2_RD((bp), size) > \
219 offsetof(struct shmem2_region, field)))
220
221 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
222 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
223
224 /* SP SB indices */
225
226 /* General SP events - stats query, cfc delete, etc */
227 #define HC_SP_INDEX_ETH_DEF_CONS 3
228
229 /* EQ completions */
230 #define HC_SP_INDEX_EQ_CONS 7
231
232 /* FCoE L2 connection completions */
233 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
234 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
235 /* iSCSI L2 */
236 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
237 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
238
239 /* Special clients parameters */
240
241 /* SB indices */
242 /* FCoE L2 */
243 #define BNX2X_FCOE_L2_RX_INDEX \
244 (&bp->def_status_blk->sp_sb.\
245 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
246
247 #define BNX2X_FCOE_L2_TX_INDEX \
248 (&bp->def_status_blk->sp_sb.\
249 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
250
251 /**
252 * CIDs and CLIDs:
253 * CLIDs below is a CLID for func 0, then the CLID for other
254 * functions will be calculated by the formula:
255 *
256 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
257 *
258 */
259 enum {
260 BNX2X_ISCSI_ETH_CL_ID_IDX,
261 BNX2X_FCOE_ETH_CL_ID_IDX,
262 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
263 };
264
265 /* use a value high enough to be above all the PFs, which has least significant
266 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to
267 * calculate doorbell address according to old doorbell configuration scheme
268 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
269 * We must avoid coming up with cid 8 for iscsi since according to this method
270 * the designated UIO cid will come out 0 and it has a special handling for that
271 * case which doesn't suit us. Therefore will will cieling to closes cid which
272 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
273 */
274
275 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
276 (bp)->max_cos)
277 /* amount of cids traversed by UIO's DPM addition to doorbell */
278 #define UIO_DPM 8
279 /* roundup to DPM offset */
280 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
281 UIO_DPM))
282 /* offset to nearest value which has lsb nibble matching DPM */
283 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \
284 (UIO_DPM * 2))
285 /* add offset to rounded-up cid to get a value which could be used with UIO */
286 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
287 /* but wait - avoid UIO special case for cid 0 */
288 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \
289 (UIO_DPM_ALIGN(bp) == UIO_DPM))
290 /* Properly DPM aligned CID dajusted to cid 0 secal case */
291 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \
292 (UIO_DPM_CID0_OFFSET(bp)))
293 /* how many cids were wasted - need this value for cid allocation */
294 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \
295 BNX2X_1st_NON_L2_ETH_CID(bp))
296 /* iSCSI L2 */
297 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
298 /* FCoE L2 */
299 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
300
301 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
302 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
303 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
304 #define FCOE_INIT(bp) ((bp)->fcoe_init)
305
306 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
307 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
308
309 #define SM_RX_ID 0
310 #define SM_TX_ID 1
311
312 /* defines for multiple tx priority indices */
313 #define FIRST_TX_ONLY_COS_INDEX 1
314 #define FIRST_TX_COS_INDEX 0
315
316 /* rules for calculating the cids of tx-only connections */
317 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
318 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
319 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
320
321 /* fp index inside class of service range */
322 #define FP_COS_TO_TXQ(fp, cos, bp) \
323 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
324
325 /* Indexes for transmission queues array:
326 * txdata for RSS i CoS j is at location i + (j * num of RSS)
327 * txdata for FCoE (if exist) is at location max cos * num of RSS
328 * txdata for FWD (if exist) is one location after FCoE
329 * txdata for OOO (if exist) is one location after FWD
330 */
331 enum {
332 FCOE_TXQ_IDX_OFFSET,
333 FWD_TXQ_IDX_OFFSET,
334 OOO_TXQ_IDX_OFFSET,
335 };
336 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
337 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
338
339 /* fast path */
340 /*
341 * This driver uses new build_skb() API :
342 * RX ring buffer contains pointer to kmalloc() data only,
343 * skb are built only after Hardware filled the frame.
344 */
345 struct sw_rx_bd {
346 u8 *data;
347 DEFINE_DMA_UNMAP_ADDR(mapping);
348 };
349
350 struct sw_tx_bd {
351 struct sk_buff *skb;
352 u16 first_bd;
353 u8 flags;
354 /* Set on the first BD descriptor when there is a split BD */
355 #define BNX2X_TSO_SPLIT_BD (1<<0)
356 #define BNX2X_HAS_SECOND_PBD (1<<1)
357 };
358
359 struct sw_rx_page {
360 struct page *page;
361 DEFINE_DMA_UNMAP_ADDR(mapping);
362 unsigned int offset;
363 };
364
365 union db_prod {
366 struct doorbell_set_prod data;
367 u32 raw;
368 };
369
370 /* dropless fc FW/HW related params */
371 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
372 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
373 ETH_MAX_AGGREGATION_QUEUES_E1 :\
374 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
375 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
376 #define FW_PREFETCH_CNT 16
377 #define DROPLESS_FC_HEADROOM 100
378
379 /* MC hsi */
380 #define BCM_PAGE_SHIFT 12
381 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
382 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
383 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
384
385 #define PAGES_PER_SGE_SHIFT 0
386 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
387 #define SGE_PAGE_SHIFT 12
388 #define SGE_PAGE_SIZE (1 << SGE_PAGE_SHIFT)
389 #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1))
390 #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK)
391 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
392 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
393 SGE_PAGES), 0xffff)
394
395 /* SGE ring related macros */
396 #define NUM_RX_SGE_PAGES 2
397 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
398 #define NEXT_PAGE_SGE_DESC_CNT 2
399 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
400 /* RX_SGE_CNT is promised to be a power of 2 */
401 #define RX_SGE_MASK (RX_SGE_CNT - 1)
402 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
403 #define MAX_RX_SGE (NUM_RX_SGE - 1)
404 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
405 (MAX_RX_SGE_CNT - 1)) ? \
406 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
407 (x) + 1)
408 #define RX_SGE(x) ((x) & MAX_RX_SGE)
409
410 /*
411 * Number of required SGEs is the sum of two:
412 * 1. Number of possible opened aggregations (next packet for
413 * these aggregations will probably consume SGE immediately)
414 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
415 * after placement on BD for new TPA aggregation)
416 *
417 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
418 */
419 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
420 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
421 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
422 MAX_RX_SGE_CNT)
423 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
424 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
425 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
426
427 /* Manipulate a bit vector defined as an array of u64 */
428
429 /* Number of bits in one sge_mask array element */
430 #define BIT_VEC64_ELEM_SZ 64
431 #define BIT_VEC64_ELEM_SHIFT 6
432 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
433
434 #define __BIT_VEC64_SET_BIT(el, bit) \
435 do { \
436 el = ((el) | ((u64)0x1 << (bit))); \
437 } while (0)
438
439 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
440 do { \
441 el = ((el) & (~((u64)0x1 << (bit)))); \
442 } while (0)
443
444 #define BIT_VEC64_SET_BIT(vec64, idx) \
445 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
446 (idx) & BIT_VEC64_ELEM_MASK)
447
448 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
449 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
450 (idx) & BIT_VEC64_ELEM_MASK)
451
452 #define BIT_VEC64_TEST_BIT(vec64, idx) \
453 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
454 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
455
456 /* Creates a bitmask of all ones in less significant bits.
457 idx - index of the most significant bit in the created mask */
458 #define BIT_VEC64_ONES_MASK(idx) \
459 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
460 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
461
462 /*******************************************************/
463
464 /* Number of u64 elements in SGE mask array */
465 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
466 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
467 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
468
469 union host_hc_status_block {
470 /* pointer to fp status block e1x */
471 struct host_hc_status_block_e1x *e1x_sb;
472 /* pointer to fp status block e2 */
473 struct host_hc_status_block_e2 *e2_sb;
474 };
475
476 struct bnx2x_agg_info {
477 /*
478 * First aggregation buffer is a data buffer, the following - are pages.
479 * We will preallocate the data buffer for each aggregation when
480 * we open the interface and will replace the BD at the consumer
481 * with this one when we receive the TPA_START CQE in order to
482 * keep the Rx BD ring consistent.
483 */
484 struct sw_rx_bd first_buf;
485 u8 tpa_state;
486 #define BNX2X_TPA_START 1
487 #define BNX2X_TPA_STOP 2
488 #define BNX2X_TPA_ERROR 3
489 u8 placement_offset;
490 u16 parsing_flags;
491 u16 vlan_tag;
492 u16 len_on_bd;
493 u32 rxhash;
494 enum pkt_hash_types rxhash_type;
495 u16 gro_size;
496 u16 full_page;
497 };
498
499 #define Q_STATS_OFFSET32(stat_name) \
500 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
501
502 struct bnx2x_fp_txdata {
503
504 struct sw_tx_bd *tx_buf_ring;
505
506 union eth_tx_bd_types *tx_desc_ring;
507 dma_addr_t tx_desc_mapping;
508
509 u32 cid;
510
511 union db_prod tx_db;
512
513 u16 tx_pkt_prod;
514 u16 tx_pkt_cons;
515 u16 tx_bd_prod;
516 u16 tx_bd_cons;
517
518 unsigned long tx_pkt;
519
520 __le16 *tx_cons_sb;
521
522 int txq_index;
523 struct bnx2x_fastpath *parent_fp;
524 int tx_ring_size;
525 };
526
527 enum bnx2x_tpa_mode_t {
528 TPA_MODE_DISABLED,
529 TPA_MODE_LRO,
530 TPA_MODE_GRO
531 };
532
533 struct bnx2x_alloc_pool {
534 struct page *page;
535 unsigned int offset;
536 };
537
538 struct bnx2x_fastpath {
539 struct bnx2x *bp; /* parent */
540
541 struct napi_struct napi;
542
543 #ifdef CONFIG_NET_RX_BUSY_POLL
544 unsigned long busy_poll_state;
545 #endif
546
547 union host_hc_status_block status_blk;
548 /* chip independent shortcuts into sb structure */
549 __le16 *sb_index_values;
550 __le16 *sb_running_index;
551 /* chip independent shortcut into rx_prods_offset memory */
552 u32 ustorm_rx_prods_offset;
553
554 u32 rx_buf_size;
555 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
556 dma_addr_t status_blk_mapping;
557
558 enum bnx2x_tpa_mode_t mode;
559
560 u8 max_cos; /* actual number of active tx coses */
561 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
562
563 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
564 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
565
566 struct eth_rx_bd *rx_desc_ring;
567 dma_addr_t rx_desc_mapping;
568
569 union eth_rx_cqe *rx_comp_ring;
570 dma_addr_t rx_comp_mapping;
571
572 /* SGE ring */
573 struct eth_rx_sge *rx_sge_ring;
574 dma_addr_t rx_sge_mapping;
575
576 u64 sge_mask[RX_SGE_MASK_LEN];
577
578 u32 cid;
579
580 __le16 fp_hc_idx;
581
582 u8 index; /* number in fp array */
583 u8 rx_queue; /* index for skb_record */
584 u8 cl_id; /* eth client id */
585 u8 cl_qzone_id;
586 u8 fw_sb_id; /* status block number in FW */
587 u8 igu_sb_id; /* status block number in HW */
588
589 u16 rx_bd_prod;
590 u16 rx_bd_cons;
591 u16 rx_comp_prod;
592 u16 rx_comp_cons;
593 u16 rx_sge_prod;
594 /* The last maximal completed SGE */
595 u16 last_max_sge;
596 __le16 *rx_cons_sb;
597 unsigned long rx_pkt,
598 rx_calls;
599
600 /* TPA related */
601 struct bnx2x_agg_info *tpa_info;
602 #ifdef BNX2X_STOP_ON_ERROR
603 u64 tpa_queue_used;
604 #endif
605 /* The size is calculated using the following:
606 sizeof name field from netdev structure +
607 4 ('-Xx-' string) +
608 4 (for the digits and to make it DWORD aligned) */
609 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
610 char name[FP_NAME_SIZE];
611
612 struct bnx2x_alloc_pool page_pool;
613 };
614
615 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
616 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
617 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
618 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
619
620 #ifdef CONFIG_NET_RX_BUSY_POLL
621
622 enum bnx2x_fp_state {
623 BNX2X_STATE_FP_NAPI = BIT(0), /* NAPI handler owns the queue */
624
625 BNX2X_STATE_FP_NAPI_REQ_BIT = 1, /* NAPI would like to own the queue */
626 BNX2X_STATE_FP_NAPI_REQ = BIT(1),
627
628 BNX2X_STATE_FP_POLL_BIT = 2,
629 BNX2X_STATE_FP_POLL = BIT(2), /* busy_poll owns the queue */
630
631 BNX2X_STATE_FP_DISABLE_BIT = 3, /* queue is dismantled */
632 };
633
bnx2x_fp_busy_poll_init(struct bnx2x_fastpath * fp)634 static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp)
635 {
636 WRITE_ONCE(fp->busy_poll_state, 0);
637 }
638
639 /* called from the device poll routine to get ownership of a FP */
bnx2x_fp_lock_napi(struct bnx2x_fastpath * fp)640 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
641 {
642 unsigned long prev, old = READ_ONCE(fp->busy_poll_state);
643
644 while (1) {
645 switch (old) {
646 case BNX2X_STATE_FP_POLL:
647 /* make sure bnx2x_fp_lock_poll() wont starve us */
648 set_bit(BNX2X_STATE_FP_NAPI_REQ_BIT,
649 &fp->busy_poll_state);
650 /* fallthrough */
651 case BNX2X_STATE_FP_POLL | BNX2X_STATE_FP_NAPI_REQ:
652 return false;
653 default:
654 break;
655 }
656 prev = cmpxchg(&fp->busy_poll_state, old, BNX2X_STATE_FP_NAPI);
657 if (unlikely(prev != old)) {
658 old = prev;
659 continue;
660 }
661 return true;
662 }
663 }
664
bnx2x_fp_unlock_napi(struct bnx2x_fastpath * fp)665 static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
666 {
667 smp_wmb();
668 fp->busy_poll_state = 0;
669 }
670
671 /* called from bnx2x_low_latency_poll() */
bnx2x_fp_lock_poll(struct bnx2x_fastpath * fp)672 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
673 {
674 return cmpxchg(&fp->busy_poll_state, 0, BNX2X_STATE_FP_POLL) == 0;
675 }
676
bnx2x_fp_unlock_poll(struct bnx2x_fastpath * fp)677 static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
678 {
679 smp_mb__before_atomic();
680 clear_bit(BNX2X_STATE_FP_POLL_BIT, &fp->busy_poll_state);
681 }
682
683 /* true if a socket is polling */
bnx2x_fp_ll_polling(struct bnx2x_fastpath * fp)684 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
685 {
686 return READ_ONCE(fp->busy_poll_state) & BNX2X_STATE_FP_POLL;
687 }
688
689 /* false if fp is currently owned */
bnx2x_fp_ll_disable(struct bnx2x_fastpath * fp)690 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
691 {
692 set_bit(BNX2X_STATE_FP_DISABLE_BIT, &fp->busy_poll_state);
693 return !bnx2x_fp_ll_polling(fp);
694
695 }
696 #else
bnx2x_fp_busy_poll_init(struct bnx2x_fastpath * fp)697 static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp)
698 {
699 }
700
bnx2x_fp_lock_napi(struct bnx2x_fastpath * fp)701 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
702 {
703 return true;
704 }
705
bnx2x_fp_unlock_napi(struct bnx2x_fastpath * fp)706 static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
707 {
708 }
709
bnx2x_fp_lock_poll(struct bnx2x_fastpath * fp)710 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
711 {
712 return false;
713 }
714
bnx2x_fp_unlock_poll(struct bnx2x_fastpath * fp)715 static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
716 {
717 }
718
bnx2x_fp_ll_polling(struct bnx2x_fastpath * fp)719 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
720 {
721 return false;
722 }
bnx2x_fp_ll_disable(struct bnx2x_fastpath * fp)723 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
724 {
725 return true;
726 }
727 #endif /* CONFIG_NET_RX_BUSY_POLL */
728
729 /* Use 2500 as a mini-jumbo MTU for FCoE */
730 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
731
732 #define FCOE_IDX_OFFSET 0
733
734 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
735 FCOE_IDX_OFFSET)
736 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
737 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
738 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
739 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
740 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
741 txdata_ptr[FIRST_TX_COS_INDEX] \
742 ->var)
743
744 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
745 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
746 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
747
748 /* MC hsi */
749 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
750 #define RX_COPY_THRESH 92
751
752 #define NUM_TX_RINGS 16
753 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
754 #define NEXT_PAGE_TX_DESC_CNT 1
755 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
756 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
757 #define MAX_TX_BD (NUM_TX_BD - 1)
758 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
759 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
760 (MAX_TX_DESC_CNT - 1)) ? \
761 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
762 (x) + 1)
763 #define TX_BD(x) ((x) & MAX_TX_BD)
764 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
765
766 /* number of NEXT_PAGE descriptors may be required during placement */
767 #define NEXT_CNT_PER_TX_PKT(bds) \
768 (((bds) + MAX_TX_DESC_CNT - 1) / \
769 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
770 /* max BDs per tx packet w/o next_pages:
771 * START_BD - describes packed
772 * START_BD(splitted) - includes unpaged data segment for GSO
773 * PARSING_BD - for TSO and CSUM data
774 * PARSING_BD2 - for encapsulation data
775 * Frag BDs - describes pages for frags
776 */
777 #define BDS_PER_TX_PKT 4
778 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
779 /* max BDs per tx packet including next pages */
780 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
781 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
782
783 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
784 #define NUM_RX_RINGS 8
785 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
786 #define NEXT_PAGE_RX_DESC_CNT 2
787 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
788 #define RX_DESC_MASK (RX_DESC_CNT - 1)
789 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
790 #define MAX_RX_BD (NUM_RX_BD - 1)
791 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
792
793 /* dropless fc calculations for BDs
794 *
795 * Number of BDs should as number of buffers in BRB:
796 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
797 * "next" elements on each page
798 */
799 #define NUM_BD_REQ BRB_SIZE(bp)
800 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
801 MAX_RX_DESC_CNT)
802 #define BD_TH_LO(bp) (NUM_BD_REQ + \
803 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
804 FW_DROP_LEVEL(bp))
805 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
806
807 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
808
809 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
810 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
811 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
812 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
813 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
814 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
815 MIN_RX_AVAIL))
816
817 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
818 (MAX_RX_DESC_CNT - 1)) ? \
819 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
820 (x) + 1)
821 #define RX_BD(x) ((x) & MAX_RX_BD)
822
823 /*
824 * As long as CQE is X times bigger than BD entry we have to allocate X times
825 * more pages for CQ ring in order to keep it balanced with BD ring
826 */
827 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
828 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
829 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
830 #define NEXT_PAGE_RCQ_DESC_CNT 1
831 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
832 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
833 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
834 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
835 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
836 (MAX_RCQ_DESC_CNT - 1)) ? \
837 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
838 (x) + 1)
839 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
840
841 /* dropless fc calculations for RCQs
842 *
843 * Number of RCQs should be as number of buffers in BRB:
844 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
845 * "next" elements on each page
846 */
847 #define NUM_RCQ_REQ BRB_SIZE(bp)
848 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
849 MAX_RCQ_DESC_CNT)
850 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
851 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
852 FW_DROP_LEVEL(bp))
853 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
854
855 /* This is needed for determining of last_max */
856 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
857 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
858
859 #define BNX2X_SWCID_SHIFT 17
860 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
861
862 /* used on a CID received from the HW */
863 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
864 #define CQE_CMD(x) (le32_to_cpu(x) >> \
865 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
866
867 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
868 le32_to_cpu((bd)->addr_lo))
869 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
870
871 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
872 #define BNX2X_DB_SHIFT 3 /* 8 bytes*/
873 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
874 #error "Min DB doorbell stride is 8"
875 #endif
876 #define DOORBELL(bp, cid, val) \
877 do { \
878 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \
879 } while (0)
880
881 /* TX CSUM helpers */
882 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
883 skb->csum_offset)
884 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
885 skb->csum_offset))
886
887 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
888
889 #define XMIT_PLAIN 0
890 #define XMIT_CSUM_V4 (1 << 0)
891 #define XMIT_CSUM_V6 (1 << 1)
892 #define XMIT_CSUM_TCP (1 << 2)
893 #define XMIT_GSO_V4 (1 << 3)
894 #define XMIT_GSO_V6 (1 << 4)
895 #define XMIT_CSUM_ENC_V4 (1 << 5)
896 #define XMIT_CSUM_ENC_V6 (1 << 6)
897 #define XMIT_GSO_ENC_V4 (1 << 7)
898 #define XMIT_GSO_ENC_V6 (1 << 8)
899
900 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
901 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
902
903 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
904 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
905
906 /* stuff added to make the code fit 80Col */
907 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
908 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
909 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
910 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
911 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
912
913 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
914
915 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
916 (((le16_to_cpu(flags) & \
917 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
918 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
919 == PRS_FLAG_OVERETH_IPV4)
920 #define BNX2X_RX_SUM_FIX(cqe) \
921 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
922
923 #define FP_USB_FUNC_OFF \
924 offsetof(struct cstorm_status_block_u, func)
925 #define FP_CSB_FUNC_OFF \
926 offsetof(struct cstorm_status_block_c, func)
927
928 #define HC_INDEX_ETH_RX_CQ_CONS 1
929
930 #define HC_INDEX_OOO_TX_CQ_CONS 4
931
932 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
933
934 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
935
936 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
937
938 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
939
940 #define BNX2X_RX_SB_INDEX \
941 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
942
943 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
944
945 #define BNX2X_TX_SB_INDEX_COS0 \
946 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
947
948 /* end of fast path */
949
950 /* common */
951
952 struct bnx2x_common {
953
954 u32 chip_id;
955 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
956 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
957
958 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
959 #define CHIP_NUM_57710 0x164e
960 #define CHIP_NUM_57711 0x164f
961 #define CHIP_NUM_57711E 0x1650
962 #define CHIP_NUM_57712 0x1662
963 #define CHIP_NUM_57712_MF 0x1663
964 #define CHIP_NUM_57712_VF 0x166f
965 #define CHIP_NUM_57713 0x1651
966 #define CHIP_NUM_57713E 0x1652
967 #define CHIP_NUM_57800 0x168a
968 #define CHIP_NUM_57800_MF 0x16a5
969 #define CHIP_NUM_57800_VF 0x16a9
970 #define CHIP_NUM_57810 0x168e
971 #define CHIP_NUM_57810_MF 0x16ae
972 #define CHIP_NUM_57810_VF 0x16af
973 #define CHIP_NUM_57811 0x163d
974 #define CHIP_NUM_57811_MF 0x163e
975 #define CHIP_NUM_57811_VF 0x163f
976 #define CHIP_NUM_57840_OBSOLETE 0x168d
977 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
978 #define CHIP_NUM_57840_4_10 0x16a1
979 #define CHIP_NUM_57840_2_20 0x16a2
980 #define CHIP_NUM_57840_MF 0x16a4
981 #define CHIP_NUM_57840_VF 0x16ad
982 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
983 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
984 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
985 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
986 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
987 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
988 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
989 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
990 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
991 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
992 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
993 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
994 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
995 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
996 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
997 #define CHIP_IS_57840(bp) \
998 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
999 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
1000 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
1001 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
1002 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
1003 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
1004 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
1005 CHIP_IS_57711E(bp))
1006 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
1007 CHIP_IS_57811_MF(bp) || \
1008 CHIP_IS_57811_VF(bp))
1009 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
1010 CHIP_IS_57712_MF(bp) || \
1011 CHIP_IS_57712_VF(bp))
1012 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
1013 CHIP_IS_57800_MF(bp) || \
1014 CHIP_IS_57800_VF(bp) || \
1015 CHIP_IS_57810(bp) || \
1016 CHIP_IS_57810_MF(bp) || \
1017 CHIP_IS_57810_VF(bp) || \
1018 CHIP_IS_57811xx(bp) || \
1019 CHIP_IS_57840(bp) || \
1020 CHIP_IS_57840_MF(bp) || \
1021 CHIP_IS_57840_VF(bp))
1022 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
1023 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
1024 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
1025
1026 #define CHIP_REV_SHIFT 12
1027 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1028 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
1029 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1030 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
1031 /* assume maximum 5 revisions */
1032 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
1033 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
1034 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
1035 !(CHIP_REV_VAL(bp) & 0x00001000))
1036 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
1037 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
1038 (CHIP_REV_VAL(bp) & 0x00001000))
1039
1040 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
1041 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
1042
1043 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
1044 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
1045 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
1046 (CHIP_REV_SHIFT + 1)) \
1047 << CHIP_REV_SHIFT)
1048 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
1049 CHIP_REV_SIM(bp) :\
1050 CHIP_REV_VAL(bp))
1051 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
1052 (CHIP_REV(bp) == CHIP_REV_Bx))
1053 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
1054 (CHIP_REV(bp) == CHIP_REV_Ax))
1055 /* This define is used in two main places:
1056 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
1057 * to nic-only mode or to offload mode. Offload mode is configured if either the
1058 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
1059 * registered for this port (which means that the user wants storage services).
1060 * 2. During cnic-related load, to know if offload mode is already configured in
1061 * the HW or needs to be configured.
1062 * Since the transition from nic-mode to offload-mode in HW causes traffic
1063 * corruption, nic-mode is configured only in ports on which storage services
1064 * where never requested.
1065 */
1066 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
1067
1068 int flash_size;
1069 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
1070 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
1071 #define BNX2X_NVRAM_PAGE_SIZE 256
1072
1073 u32 shmem_base;
1074 u32 shmem2_base;
1075 u32 mf_cfg_base;
1076 u32 mf2_cfg_base;
1077
1078 u32 hw_config;
1079
1080 u32 bc_ver;
1081
1082 u8 int_block;
1083 #define INT_BLOCK_HC 0
1084 #define INT_BLOCK_IGU 1
1085 #define INT_BLOCK_MODE_NORMAL 0
1086 #define INT_BLOCK_MODE_BW_COMP 2
1087 #define CHIP_INT_MODE_IS_NBC(bp) \
1088 (!CHIP_IS_E1x(bp) && \
1089 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
1090 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
1091
1092 u8 chip_port_mode;
1093 #define CHIP_4_PORT_MODE 0x0
1094 #define CHIP_2_PORT_MODE 0x1
1095 #define CHIP_PORT_MODE_NONE 0x2
1096 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
1097 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
1098
1099 u32 boot_mode;
1100 };
1101
1102 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
1103 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
1104 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
1105
1106 #define MAX_IGU_ATTN_ACK_TO 100
1107 /* end of common */
1108
1109 /* port */
1110
1111 struct bnx2x_port {
1112 u32 pmf;
1113
1114 u32 link_config[LINK_CONFIG_SIZE];
1115
1116 u32 supported[LINK_CONFIG_SIZE];
1117
1118 u32 advertising[LINK_CONFIG_SIZE];
1119
1120 u32 phy_addr;
1121
1122 /* used to synchronize phy accesses */
1123 struct mutex phy_mutex;
1124
1125 u32 port_stx;
1126
1127 struct nig_stats old_nig_stats;
1128 };
1129
1130 /* end of port */
1131
1132 #define STATS_OFFSET32(stat_name) \
1133 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1134
1135 /* slow path */
1136 #define BNX2X_MAX_NUM_OF_VFS 64
1137 #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */
1138 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
1139
1140 /* We need to reserve doorbell addresses for all VF and queue combinations */
1141 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1142
1143 /* The doorbell is configured to have the same number of CIDs for PFs and for
1144 * VFs. For this reason the PF CID zone is as large as the VF zone.
1145 */
1146 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS
1147 #define BNX2X_MAX_NUM_VF_QUEUES 64
1148 #define BNX2X_VF_ID_INVALID 0xFF
1149
1150 /* the number of VF CIDS multiplied by the amount of bytes reserved for each
1151 * cid must not exceed the size of the VF doorbell
1152 */
1153 #define BNX2X_VF_BAR_SIZE 512
1154 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1155 #error "VF doorbell bar size is 512"
1156 #endif
1157
1158 /*
1159 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1160 * control by the number of fast-path status blocks supported by the
1161 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1162 * status block represents an independent interrupts context that can
1163 * serve a regular L2 networking queue. However special L2 queues such
1164 * as the FCoE queue do not require a FP-SB and other components like
1165 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1166 *
1167 * If the maximum number of FP-SB available is X then:
1168 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1169 * regular L2 queues is Y=X-1
1170 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1171 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1172 * is Y+1
1173 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1174 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1175 * FP interrupt context for the CNIC).
1176 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1177 * L2 queue is supported. The cid for the FCoE L2 queue is always X.
1178 */
1179
1180 /* fast-path interrupt contexts E1x */
1181 #define FP_SB_MAX_E1x 16
1182 /* fast-path interrupt contexts E2 */
1183 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1184
1185 union cdu_context {
1186 struct eth_context eth;
1187 char pad[1024];
1188 };
1189
1190 /* CDU host DB constants */
1191 #define CDU_ILT_PAGE_SZ_HW 2
1192 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1193 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1194
1195 #define CNIC_ISCSI_CID_MAX 256
1196 #define CNIC_FCOE_CID_MAX 2048
1197 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1198 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1199
1200 #define QM_ILT_PAGE_SZ_HW 0
1201 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1202 #define QM_CID_ROUND 1024
1203
1204 /* TM (timers) host DB constants */
1205 #define TM_ILT_PAGE_SZ_HW 0
1206 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1207 #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \
1208 BNX2X_VF_CIDS + \
1209 CNIC_ISCSI_CID_MAX)
1210 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1211 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1212
1213 /* SRC (Searcher) host DB constants */
1214 #define SRC_ILT_PAGE_SZ_HW 0
1215 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1216 #define SRC_HASH_BITS 10
1217 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1218 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1219 #define SRC_T2_SZ SRC_ILT_SZ
1220 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1221
1222 #define MAX_DMAE_C 8
1223
1224 /* DMA memory not used in fastpath */
1225 struct bnx2x_slowpath {
1226 union {
1227 struct mac_configuration_cmd e1x;
1228 struct eth_classify_rules_ramrod_data e2;
1229 } mac_rdata;
1230
1231 union {
1232 struct eth_classify_rules_ramrod_data e2;
1233 } vlan_rdata;
1234
1235 union {
1236 struct tstorm_eth_mac_filter_config e1x;
1237 struct eth_filter_rules_ramrod_data e2;
1238 } rx_mode_rdata;
1239
1240 union {
1241 struct mac_configuration_cmd e1;
1242 struct eth_multicast_rules_ramrod_data e2;
1243 } mcast_rdata;
1244
1245 struct eth_rss_update_ramrod_data rss_rdata;
1246
1247 /* Queue State related ramrods are always sent under rtnl_lock */
1248 union {
1249 struct client_init_ramrod_data init_data;
1250 struct client_update_ramrod_data update_data;
1251 struct tpa_update_ramrod_data tpa_data;
1252 } q_rdata;
1253
1254 union {
1255 struct function_start_data func_start;
1256 /* pfc configuration for DCBX ramrod */
1257 struct flow_control_configuration pfc_config;
1258 } func_rdata;
1259
1260 /* afex ramrod can not be a part of func_rdata union because these
1261 * events might arrive in parallel to other events from func_rdata.
1262 * Therefore, if they would have been defined in the same union,
1263 * data can get corrupted.
1264 */
1265 union {
1266 struct afex_vif_list_ramrod_data viflist_data;
1267 struct function_update_data func_update;
1268 } func_afex_rdata;
1269
1270 /* used by dmae command executer */
1271 struct dmae_command dmae[MAX_DMAE_C];
1272
1273 u32 stats_comp;
1274 union mac_stats mac_stats;
1275 struct nig_stats nig_stats;
1276 struct host_port_stats port_stats;
1277 struct host_func_stats func_stats;
1278
1279 u32 wb_comp;
1280 u32 wb_data[4];
1281
1282 union drv_info_to_mcp drv_info_to_mcp;
1283 };
1284
1285 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1286 #define bnx2x_sp_mapping(bp, var) \
1287 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1288
1289 /* attn group wiring */
1290 #define MAX_DYNAMIC_ATTN_GRPS 8
1291
1292 struct attn_route {
1293 u32 sig[5];
1294 };
1295
1296 struct iro {
1297 u32 base;
1298 u16 m1;
1299 u16 m2;
1300 u16 m3;
1301 u16 size;
1302 };
1303
1304 struct hw_context {
1305 union cdu_context *vcxt;
1306 dma_addr_t cxt_mapping;
1307 size_t size;
1308 };
1309
1310 /* forward */
1311 struct bnx2x_ilt;
1312
1313 struct bnx2x_vfdb;
1314
1315 enum bnx2x_recovery_state {
1316 BNX2X_RECOVERY_DONE,
1317 BNX2X_RECOVERY_INIT,
1318 BNX2X_RECOVERY_WAIT,
1319 BNX2X_RECOVERY_FAILED,
1320 BNX2X_RECOVERY_NIC_LOADING
1321 };
1322
1323 /*
1324 * Event queue (EQ or event ring) MC hsi
1325 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1326 */
1327 #define NUM_EQ_PAGES 1
1328 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1329 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1330 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1331 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1332 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1333
1334 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1335 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1336 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1337
1338 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1339 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1340
1341 #define BNX2X_EQ_INDEX \
1342 (&bp->def_status_blk->sp_sb.\
1343 index_values[HC_SP_INDEX_EQ_CONS])
1344
1345 /* This is a data that will be used to create a link report message.
1346 * We will keep the data used for the last link report in order
1347 * to prevent reporting the same link parameters twice.
1348 */
1349 struct bnx2x_link_report_data {
1350 u16 line_speed; /* Effective line speed */
1351 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1352 };
1353
1354 enum {
1355 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1356 BNX2X_LINK_REPORT_LINK_DOWN,
1357 BNX2X_LINK_REPORT_RX_FC_ON,
1358 BNX2X_LINK_REPORT_TX_FC_ON,
1359 };
1360
1361 enum {
1362 BNX2X_PORT_QUERY_IDX,
1363 BNX2X_PF_QUERY_IDX,
1364 BNX2X_FCOE_QUERY_IDX,
1365 BNX2X_FIRST_QUEUE_QUERY_IDX,
1366 };
1367
1368 struct bnx2x_fw_stats_req {
1369 struct stats_query_header hdr;
1370 struct stats_query_entry query[FP_SB_MAX_E1x+
1371 BNX2X_FIRST_QUEUE_QUERY_IDX];
1372 };
1373
1374 struct bnx2x_fw_stats_data {
1375 struct stats_counter storm_counters;
1376 struct per_port_stats port;
1377 struct per_pf_stats pf;
1378 struct fcoe_statistics_params fcoe;
1379 struct per_queue_stats queue_stats[1];
1380 };
1381
1382 /* Public slow path states */
1383 enum sp_rtnl_flag {
1384 BNX2X_SP_RTNL_SETUP_TC,
1385 BNX2X_SP_RTNL_TX_TIMEOUT,
1386 BNX2X_SP_RTNL_FAN_FAILURE,
1387 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1388 BNX2X_SP_RTNL_ENABLE_SRIOV,
1389 BNX2X_SP_RTNL_VFPF_MCAST,
1390 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
1391 BNX2X_SP_RTNL_RX_MODE,
1392 BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1393 BNX2X_SP_RTNL_TX_STOP,
1394 BNX2X_SP_RTNL_GET_DRV_VERSION,
1395 BNX2X_SP_RTNL_ADD_VXLAN_PORT,
1396 BNX2X_SP_RTNL_DEL_VXLAN_PORT,
1397 };
1398
1399 enum bnx2x_iov_flag {
1400 BNX2X_IOV_HANDLE_VF_MSG,
1401 BNX2X_IOV_HANDLE_FLR,
1402 };
1403
1404 struct bnx2x_prev_path_list {
1405 struct list_head list;
1406 u8 bus;
1407 u8 slot;
1408 u8 path;
1409 u8 aer;
1410 u8 undi;
1411 };
1412
1413 struct bnx2x_sp_objs {
1414 /* MACs object */
1415 struct bnx2x_vlan_mac_obj mac_obj;
1416
1417 /* Queue State object */
1418 struct bnx2x_queue_sp_obj q_obj;
1419
1420 /* VLANs object */
1421 struct bnx2x_vlan_mac_obj vlan_obj;
1422 };
1423
1424 struct bnx2x_fp_stats {
1425 struct tstorm_per_queue_stats old_tclient;
1426 struct ustorm_per_queue_stats old_uclient;
1427 struct xstorm_per_queue_stats old_xclient;
1428 struct bnx2x_eth_q_stats eth_q_stats;
1429 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1430 };
1431
1432 enum {
1433 SUB_MF_MODE_UNKNOWN = 0,
1434 SUB_MF_MODE_UFP,
1435 SUB_MF_MODE_NPAR1_DOT_5,
1436 SUB_MF_MODE_BD,
1437 };
1438
1439 struct bnx2x_vlan_entry {
1440 struct list_head link;
1441 u16 vid;
1442 bool hw;
1443 };
1444
1445 struct bnx2x {
1446 /* Fields used in the tx and intr/napi performance paths
1447 * are grouped together in the beginning of the structure
1448 */
1449 struct bnx2x_fastpath *fp;
1450 struct bnx2x_sp_objs *sp_objs;
1451 struct bnx2x_fp_stats *fp_stats;
1452 struct bnx2x_fp_txdata *bnx2x_txq;
1453 void __iomem *regview;
1454 void __iomem *doorbells;
1455 u16 db_size;
1456
1457 u8 pf_num; /* absolute PF number */
1458 u8 pfid; /* per-path PF number */
1459 int base_fw_ndsb; /**/
1460 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1461 #define BP_PORT(bp) (bp->pfid & 1)
1462 #define BP_FUNC(bp) (bp->pfid)
1463 #define BP_ABS_FUNC(bp) (bp->pf_num)
1464 #define BP_VN(bp) ((bp)->pfid >> 1)
1465 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1466 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1467 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1468 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1469 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1470
1471 #ifdef CONFIG_BNX2X_SRIOV
1472 /* protects vf2pf mailbox from simultaneous access */
1473 struct mutex vf2pf_mutex;
1474 /* vf pf channel mailbox contains request and response buffers */
1475 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1476 dma_addr_t vf2pf_mbox_mapping;
1477
1478 /* we set aside a copy of the acquire response */
1479 struct pfvf_acquire_resp_tlv acquire_resp;
1480
1481 /* bulletin board for messages from pf to vf */
1482 union pf_vf_bulletin *pf2vf_bulletin;
1483 dma_addr_t pf2vf_bulletin_mapping;
1484
1485 union pf_vf_bulletin shadow_bulletin;
1486 struct pf_vf_bulletin_content old_bulletin;
1487
1488 u16 requested_nr_virtfn;
1489 #endif /* CONFIG_BNX2X_SRIOV */
1490
1491 struct net_device *dev;
1492 struct pci_dev *pdev;
1493
1494 const struct iro *iro_arr;
1495 #define IRO (bp->iro_arr)
1496
1497 enum bnx2x_recovery_state recovery_state;
1498 int is_leader;
1499 struct msix_entry *msix_table;
1500
1501 int tx_ring_size;
1502
1503 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1504 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1505 #define ETH_MIN_PACKET_SIZE 60
1506 #define ETH_MAX_PACKET_SIZE 1500
1507 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1508 /* TCP with Timestamp Option (32) + IPv6 (40) */
1509 #define ETH_MAX_TPA_HEADER_SIZE 72
1510
1511 /* Max supported alignment is 256 (8 shift)
1512 * minimal alignment shift 6 is optimal for 57xxx HW performance
1513 */
1514 #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
1515
1516 /* FW uses 2 Cache lines Alignment for start packet and size
1517 *
1518 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1519 * at the end of skb->data, to avoid wasting a full cache line.
1520 * This reduces memory use (skb->truesize).
1521 */
1522 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1523
1524 #define BNX2X_FW_RX_ALIGN_END \
1525 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1526 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1527
1528 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1529
1530 struct host_sp_status_block *def_status_blk;
1531 #define DEF_SB_IGU_ID 16
1532 #define DEF_SB_ID HC_SP_SB_ID
1533 __le16 def_idx;
1534 __le16 def_att_idx;
1535 u32 attn_state;
1536 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1537
1538 /* slow path ring */
1539 struct eth_spe *spq;
1540 dma_addr_t spq_mapping;
1541 u16 spq_prod_idx;
1542 struct eth_spe *spq_prod_bd;
1543 struct eth_spe *spq_last_bd;
1544 __le16 *dsb_sp_prod;
1545 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1546 /* used to synchronize spq accesses */
1547 spinlock_t spq_lock;
1548
1549 /* event queue */
1550 union event_ring_elem *eq_ring;
1551 dma_addr_t eq_mapping;
1552 u16 eq_prod;
1553 u16 eq_cons;
1554 __le16 *eq_cons_sb;
1555 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1556
1557 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1558 u16 stats_pending;
1559 /* Counter for completed statistics ramrods */
1560 u16 stats_comp;
1561
1562 /* End of fields used in the performance code paths */
1563
1564 int panic;
1565 int msg_enable;
1566
1567 u32 flags;
1568 #define PCIX_FLAG (1 << 0)
1569 #define PCI_32BIT_FLAG (1 << 1)
1570 #define ONE_PORT_FLAG (1 << 2)
1571 #define NO_WOL_FLAG (1 << 3)
1572 #define USING_MSIX_FLAG (1 << 5)
1573 #define USING_MSI_FLAG (1 << 6)
1574 #define DISABLE_MSI_FLAG (1 << 7)
1575 #define NO_MCP_FLAG (1 << 9)
1576 #define MF_FUNC_DIS (1 << 11)
1577 #define OWN_CNIC_IRQ (1 << 12)
1578 #define NO_ISCSI_OOO_FLAG (1 << 13)
1579 #define NO_ISCSI_FLAG (1 << 14)
1580 #define NO_FCOE_FLAG (1 << 15)
1581 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1582 #define TX_SWITCHING (1 << 18)
1583 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1584 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1585 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1586 #define IS_VF_FLAG (1 << 22)
1587 #define BC_SUPPORTS_RMMOD_CMD (1 << 23)
1588 #define HAS_PHYS_PORT_ID (1 << 24)
1589 #define AER_ENABLED (1 << 25)
1590 #define PTP_SUPPORTED (1 << 26)
1591 #define TX_TIMESTAMPING_EN (1 << 27)
1592
1593 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1594
1595 #ifdef CONFIG_BNX2X_SRIOV
1596 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1597 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1598 #else
1599 #define IS_VF(bp) false
1600 #define IS_PF(bp) true
1601 #endif
1602
1603 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1604 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1605 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1606
1607 u8 cnic_support;
1608 bool cnic_enabled;
1609 bool cnic_loaded;
1610 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1611
1612 /* Flag that indicates that we can start looking for FCoE L2 queue
1613 * completions in the default status block.
1614 */
1615 bool fcoe_init;
1616
1617 int mrrs;
1618
1619 struct delayed_work sp_task;
1620 struct delayed_work iov_task;
1621
1622 atomic_t interrupt_occurred;
1623 struct delayed_work sp_rtnl_task;
1624
1625 struct delayed_work period_task;
1626 struct timer_list timer;
1627 int current_interval;
1628
1629 u16 fw_seq;
1630 u16 fw_drv_pulse_wr_seq;
1631 u32 func_stx;
1632
1633 struct link_params link_params;
1634 struct link_vars link_vars;
1635 u32 link_cnt;
1636 struct bnx2x_link_report_data last_reported_link;
1637 bool force_link_down;
1638
1639 struct mdio_if_info mdio;
1640
1641 struct bnx2x_common common;
1642 struct bnx2x_port port;
1643
1644 struct cmng_init cmng;
1645
1646 u32 mf_config[E1HVN_MAX];
1647 u32 mf_ext_config;
1648 u32 path_has_ovlan; /* E3 */
1649 u16 mf_ov;
1650 u8 mf_mode;
1651 #define IS_MF(bp) (bp->mf_mode != 0)
1652 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1653 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1654 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1655 u8 mf_sub_mode;
1656 #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \
1657 bp->mf_sub_mode == SUB_MF_MODE_UFP)
1658 #define IS_MF_BD(bp) (IS_MF_SD(bp) && \
1659 bp->mf_sub_mode == SUB_MF_MODE_BD)
1660
1661 u8 wol;
1662
1663 int rx_ring_size;
1664
1665 u16 tx_quick_cons_trip_int;
1666 u16 tx_quick_cons_trip;
1667 u16 tx_ticks_int;
1668 u16 tx_ticks;
1669
1670 u16 rx_quick_cons_trip_int;
1671 u16 rx_quick_cons_trip;
1672 u16 rx_ticks_int;
1673 u16 rx_ticks;
1674 /* Maximal coalescing timeout in us */
1675 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
1676
1677 u32 lin_cnt;
1678
1679 u16 state;
1680 #define BNX2X_STATE_CLOSED 0
1681 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1682 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1683 #define BNX2X_STATE_OPEN 0x3000
1684 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1685 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1686
1687 #define BNX2X_STATE_DIAG 0xe000
1688 #define BNX2X_STATE_ERROR 0xf000
1689
1690 #define BNX2X_MAX_PRIORITY 8
1691 int num_queues;
1692 uint num_ethernet_queues;
1693 uint num_cnic_queues;
1694 int disable_tpa;
1695
1696 u32 rx_mode;
1697 #define BNX2X_RX_MODE_NONE 0
1698 #define BNX2X_RX_MODE_NORMAL 1
1699 #define BNX2X_RX_MODE_ALLMULTI 2
1700 #define BNX2X_RX_MODE_PROMISC 3
1701 #define BNX2X_MAX_MULTICAST 64
1702
1703 u8 igu_dsb_id;
1704 u8 igu_base_sb;
1705 u8 igu_sb_cnt;
1706 u8 min_msix_vec_cnt;
1707
1708 u32 igu_base_addr;
1709 dma_addr_t def_status_blk_mapping;
1710
1711 struct bnx2x_slowpath *slowpath;
1712 dma_addr_t slowpath_mapping;
1713
1714 /* Mechanism protecting the drv_info_to_mcp */
1715 struct mutex drv_info_mutex;
1716 bool drv_info_mng_owner;
1717
1718 /* Total number of FW statistics requests */
1719 u8 fw_stats_num;
1720
1721 /*
1722 * This is a memory buffer that will contain both statistics
1723 * ramrod request and data.
1724 */
1725 void *fw_stats;
1726 dma_addr_t fw_stats_mapping;
1727
1728 /*
1729 * FW statistics request shortcut (points at the
1730 * beginning of fw_stats buffer).
1731 */
1732 struct bnx2x_fw_stats_req *fw_stats_req;
1733 dma_addr_t fw_stats_req_mapping;
1734 int fw_stats_req_sz;
1735
1736 /*
1737 * FW statistics data shortcut (points at the beginning of
1738 * fw_stats buffer + fw_stats_req_sz).
1739 */
1740 struct bnx2x_fw_stats_data *fw_stats_data;
1741 dma_addr_t fw_stats_data_mapping;
1742 int fw_stats_data_sz;
1743
1744 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
1745 * context size we need 8 ILT entries.
1746 */
1747 #define ILT_MAX_L2_LINES 32
1748 struct hw_context context[ILT_MAX_L2_LINES];
1749
1750 struct bnx2x_ilt *ilt;
1751 #define BP_ILT(bp) ((bp)->ilt)
1752 #define ILT_MAX_LINES 256
1753 /*
1754 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1755 * to CNIC.
1756 */
1757 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1758
1759 /*
1760 * Maximum CID count that might be required by the bnx2x:
1761 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1762 */
1763
1764 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1765 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1766 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1767 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1768 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1769 ILT_PAGE_CIDS))
1770
1771 int qm_cid_count;
1772
1773 bool dropless_fc;
1774
1775 void *t2;
1776 dma_addr_t t2_mapping;
1777 struct cnic_ops __rcu *cnic_ops;
1778 void *cnic_data;
1779 u32 cnic_tag;
1780 struct cnic_eth_dev cnic_eth_dev;
1781 union host_hc_status_block cnic_sb;
1782 dma_addr_t cnic_sb_mapping;
1783 struct eth_spe *cnic_kwq;
1784 struct eth_spe *cnic_kwq_prod;
1785 struct eth_spe *cnic_kwq_cons;
1786 struct eth_spe *cnic_kwq_last;
1787 u16 cnic_kwq_pending;
1788 u16 cnic_spq_pending;
1789 u8 fip_mac[ETH_ALEN];
1790 struct mutex cnic_mutex;
1791 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1792
1793 /* Start index of the "special" (CNIC related) L2 clients */
1794 u8 cnic_base_cl_id;
1795
1796 int dmae_ready;
1797 /* used to synchronize dmae accesses */
1798 spinlock_t dmae_lock;
1799
1800 /* used to protect the FW mail box */
1801 struct mutex fw_mb_mutex;
1802
1803 /* used to synchronize stats collecting */
1804 int stats_state;
1805
1806 /* used for synchronization of concurrent threads statistics handling */
1807 struct semaphore stats_lock;
1808
1809 /* used by dmae command loader */
1810 struct dmae_command stats_dmae;
1811 int executer_idx;
1812
1813 u16 stats_counter;
1814 struct bnx2x_eth_stats eth_stats;
1815 struct host_func_stats func_stats;
1816 struct bnx2x_eth_stats_old eth_stats_old;
1817 struct bnx2x_net_stats_old net_stats_old;
1818 struct bnx2x_fw_port_stats_old fw_stats_old;
1819 bool stats_init;
1820
1821 struct z_stream_s *strm;
1822 void *gunzip_buf;
1823 dma_addr_t gunzip_mapping;
1824 int gunzip_outlen;
1825 #define FW_BUF_SIZE 0x8000
1826 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1827 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1828 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1829
1830 struct raw_op *init_ops;
1831 /* Init blocks offsets inside init_ops */
1832 u16 *init_ops_offsets;
1833 /* Data blob - has 32 bit granularity */
1834 u32 *init_data;
1835 u32 init_mode_flags;
1836 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1837 /* Zipped PRAM blobs - raw data */
1838 const u8 *tsem_int_table_data;
1839 const u8 *tsem_pram_data;
1840 const u8 *usem_int_table_data;
1841 const u8 *usem_pram_data;
1842 const u8 *xsem_int_table_data;
1843 const u8 *xsem_pram_data;
1844 const u8 *csem_int_table_data;
1845 const u8 *csem_pram_data;
1846 #define INIT_OPS(bp) (bp->init_ops)
1847 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1848 #define INIT_DATA(bp) (bp->init_data)
1849 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1850 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1851 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1852 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1853 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1854 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1855 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1856 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1857
1858 #define PHY_FW_VER_LEN 20
1859 char fw_ver[32];
1860 const struct firmware *firmware;
1861
1862 struct bnx2x_vfdb *vfdb;
1863 #define IS_SRIOV(bp) ((bp)->vfdb)
1864
1865 /* DCB support on/off */
1866 u16 dcb_state;
1867 #define BNX2X_DCB_STATE_OFF 0
1868 #define BNX2X_DCB_STATE_ON 1
1869
1870 /* DCBX engine mode */
1871 int dcbx_enabled;
1872 #define BNX2X_DCBX_ENABLED_OFF 0
1873 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1874 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1875 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1876
1877 bool dcbx_mode_uset;
1878
1879 struct bnx2x_config_dcbx_params dcbx_config_params;
1880 struct bnx2x_dcbx_port_params dcbx_port_params;
1881 int dcb_version;
1882
1883 /* CAM credit pools */
1884 struct bnx2x_credit_pool_obj vlans_pool;
1885
1886 struct bnx2x_credit_pool_obj macs_pool;
1887
1888 /* RX_MODE object */
1889 struct bnx2x_rx_mode_obj rx_mode_obj;
1890
1891 /* MCAST object */
1892 struct bnx2x_mcast_obj mcast_obj;
1893
1894 /* RSS configuration object */
1895 struct bnx2x_rss_config_obj rss_conf_obj;
1896
1897 /* Function State controlling object */
1898 struct bnx2x_func_sp_obj func_obj;
1899
1900 unsigned long sp_state;
1901
1902 /* operation indication for the sp_rtnl task */
1903 unsigned long sp_rtnl_state;
1904
1905 /* Indication of the IOV tasks */
1906 unsigned long iov_task_state;
1907
1908 /* DCBX Negotiation results */
1909 struct dcbx_features dcbx_local_feat;
1910 u32 dcbx_error;
1911
1912 #ifdef BCM_DCBNL
1913 struct dcbx_features dcbx_remote_feat;
1914 u32 dcbx_remote_flags;
1915 #endif
1916 /* AFEX: store default vlan used */
1917 int afex_def_vlan_tag;
1918 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1919 u32 pending_max;
1920
1921 /* multiple tx classes of service */
1922 u8 max_cos;
1923
1924 /* priority to cos mapping */
1925 u8 prio_to_cos[8];
1926
1927 int fp_array_size;
1928 u32 dump_preset_idx;
1929
1930 u8 phys_port_id[ETH_ALEN];
1931
1932 /* PTP related context */
1933 struct ptp_clock *ptp_clock;
1934 struct ptp_clock_info ptp_clock_info;
1935 struct work_struct ptp_task;
1936 struct cyclecounter cyclecounter;
1937 struct timecounter timecounter;
1938 bool timecounter_init_done;
1939 struct sk_buff *ptp_tx_skb;
1940 unsigned long ptp_tx_start;
1941 bool hwtstamp_ioctl_called;
1942 u16 tx_type;
1943 u16 rx_filter;
1944
1945 struct bnx2x_link_report_data vf_link_vars;
1946 struct list_head vlan_reg;
1947 u16 vlan_cnt;
1948 u16 vlan_credit;
1949 u16 vxlan_dst_port;
1950 u8 vxlan_dst_port_count;
1951 bool accept_any_vlan;
1952 };
1953
1954 /* Tx queues may be less or equal to Rx queues */
1955 extern int num_queues;
1956 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1957 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1958 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1959 (bp)->num_cnic_queues)
1960 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1961
1962 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1963
1964 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1965 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1966
1967 #define RSS_IPV4_CAP_MASK \
1968 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1969
1970 #define RSS_IPV4_TCP_CAP_MASK \
1971 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1972
1973 #define RSS_IPV6_CAP_MASK \
1974 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1975
1976 #define RSS_IPV6_TCP_CAP_MASK \
1977 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1978
1979 struct bnx2x_func_init_params {
1980 /* dma */
1981 bool spq_active;
1982 dma_addr_t spq_map;
1983 u16 spq_prod;
1984
1985 u16 func_id; /* abs fid */
1986 u16 pf_id;
1987 };
1988
1989 #define for_each_cnic_queue(bp, var) \
1990 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1991 (var)++) \
1992 if (skip_queue(bp, var)) \
1993 continue; \
1994 else
1995
1996 #define for_each_eth_queue(bp, var) \
1997 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1998
1999 #define for_each_nondefault_eth_queue(bp, var) \
2000 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
2001
2002 #define for_each_queue(bp, var) \
2003 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2004 if (skip_queue(bp, var)) \
2005 continue; \
2006 else
2007
2008 /* Skip forwarding FP */
2009 #define for_each_valid_rx_queue(bp, var) \
2010 for ((var) = 0; \
2011 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
2012 BNX2X_NUM_ETH_QUEUES(bp)); \
2013 (var)++) \
2014 if (skip_rx_queue(bp, var)) \
2015 continue; \
2016 else
2017
2018 #define for_each_rx_queue_cnic(bp, var) \
2019 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2020 (var)++) \
2021 if (skip_rx_queue(bp, var)) \
2022 continue; \
2023 else
2024
2025 #define for_each_rx_queue(bp, var) \
2026 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2027 if (skip_rx_queue(bp, var)) \
2028 continue; \
2029 else
2030
2031 /* Skip OOO FP */
2032 #define for_each_valid_tx_queue(bp, var) \
2033 for ((var) = 0; \
2034 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
2035 BNX2X_NUM_ETH_QUEUES(bp)); \
2036 (var)++) \
2037 if (skip_tx_queue(bp, var)) \
2038 continue; \
2039 else
2040
2041 #define for_each_tx_queue_cnic(bp, var) \
2042 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2043 (var)++) \
2044 if (skip_tx_queue(bp, var)) \
2045 continue; \
2046 else
2047
2048 #define for_each_tx_queue(bp, var) \
2049 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2050 if (skip_tx_queue(bp, var)) \
2051 continue; \
2052 else
2053
2054 #define for_each_nondefault_queue(bp, var) \
2055 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2056 if (skip_queue(bp, var)) \
2057 continue; \
2058 else
2059
2060 #define for_each_cos_in_tx_queue(fp, var) \
2061 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
2062
2063 /* skip rx queue
2064 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2065 */
2066 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2067
2068 /* skip tx queue
2069 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2070 */
2071 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2072
2073 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2074
2075 /**
2076 * bnx2x_set_mac_one - configure a single MAC address
2077 *
2078 * @bp: driver handle
2079 * @mac: MAC to configure
2080 * @obj: MAC object handle
2081 * @set: if 'true' add a new MAC, otherwise - delete
2082 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
2083 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
2084 *
2085 * Configures one MAC according to provided parameters or continues the
2086 * execution of previously scheduled commands if RAMROD_CONT is set in
2087 * ramrod_flags.
2088 *
2089 * Returns zero if operation has successfully completed, a positive value if the
2090 * operation has been successfully scheduled and a negative - if a requested
2091 * operations has failed.
2092 */
2093 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
2094 struct bnx2x_vlan_mac_obj *obj, bool set,
2095 int mac_type, unsigned long *ramrod_flags);
2096
2097 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
2098 struct bnx2x_vlan_mac_obj *obj, bool set,
2099 unsigned long *ramrod_flags);
2100
2101 /**
2102 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2103 *
2104 * @bp: driver handle
2105 * @mac_obj: MAC object handle
2106 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
2107 * @wait_for_comp: if 'true' block until completion
2108 *
2109 * Deletes all MACs of the specific type (e.g. ETH, UC list).
2110 *
2111 * Returns zero if operation has successfully completed, a positive value if the
2112 * operation has been successfully scheduled and a negative - if a requested
2113 * operations has failed.
2114 */
2115 int bnx2x_del_all_macs(struct bnx2x *bp,
2116 struct bnx2x_vlan_mac_obj *mac_obj,
2117 int mac_type, bool wait_for_comp);
2118
2119 /* Init Function API */
2120 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2121 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2122 u8 vf_valid, int fw_sb_id, int igu_sb_id);
2123 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2124 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2125 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2126 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2127 void bnx2x_read_mf_cfg(struct bnx2x *bp);
2128
2129 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2130
2131 /* dmae */
2132 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2133 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2134 u32 len32);
2135 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2136 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2137 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2138 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2139 bool with_comp, u8 comp_type);
2140
2141 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2142 u8 src_type, u8 dst_type);
2143 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2144 u32 *comp);
2145
2146 /* FLR related routines */
2147 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2148 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2149 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2150 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
2151 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2152 char *msg, u32 poll_cnt);
2153
2154 void bnx2x_calc_fc_adv(struct bnx2x *bp);
2155 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2156 u32 data_hi, u32 data_lo, int cmd_type);
2157 void bnx2x_update_coalesce(struct bnx2x *bp);
2158 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2159
2160 bool bnx2x_port_after_undi(struct bnx2x *bp);
2161
reg_poll(struct bnx2x * bp,u32 reg,u32 expected,int ms,int wait)2162 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2163 int wait)
2164 {
2165 u32 val;
2166
2167 do {
2168 val = REG_RD(bp, reg);
2169 if (val == expected)
2170 break;
2171 ms -= wait;
2172 msleep(wait);
2173
2174 } while (ms > 0);
2175
2176 return val;
2177 }
2178
2179 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2180 bool is_pf);
2181
2182 #define BNX2X_ILT_ZALLOC(x, y, size) \
2183 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2184
2185 #define BNX2X_ILT_FREE(x, y, size) \
2186 do { \
2187 if (x) { \
2188 dma_free_coherent(&bp->pdev->dev, size, x, y); \
2189 x = NULL; \
2190 y = 0; \
2191 } \
2192 } while (0)
2193
2194 #define ILOG2(x) (ilog2((x)))
2195
2196 #define ILT_NUM_PAGE_ENTRIES (3072)
2197 /* In 57710/11 we use whole table since we have 8 func
2198 * In 57712 we have only 4 func, but use same size per func, then only half of
2199 * the table in use
2200 */
2201 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
2202
2203 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
2204 /*
2205 * the phys address is shifted right 12 bits and has an added
2206 * 1=valid bit added to the 53rd bit
2207 * then since this is a wide register(TM)
2208 * we split it into two 32 bit writes
2209 */
2210 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2211 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
2212
2213 /* load/unload mode */
2214 #define LOAD_NORMAL 0
2215 #define LOAD_OPEN 1
2216 #define LOAD_DIAG 2
2217 #define LOAD_LOOPBACK_EXT 3
2218 #define UNLOAD_NORMAL 0
2219 #define UNLOAD_CLOSE 1
2220 #define UNLOAD_RECOVERY 2
2221
2222 /* DMAE command defines */
2223 #define DMAE_TIMEOUT -1
2224 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2225 #define DMAE_NOT_RDY -3
2226 #define DMAE_PCI_ERR_FLAG 0x80000000
2227
2228 #define DMAE_SRC_PCI 0
2229 #define DMAE_SRC_GRC 1
2230
2231 #define DMAE_DST_NONE 0
2232 #define DMAE_DST_PCI 1
2233 #define DMAE_DST_GRC 2
2234
2235 #define DMAE_COMP_PCI 0
2236 #define DMAE_COMP_GRC 1
2237
2238 /* E2 and onward - PCI error handling in the completion */
2239
2240 #define DMAE_COMP_REGULAR 0
2241 #define DMAE_COM_SET_ERR 1
2242
2243 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2244 DMAE_COMMAND_SRC_SHIFT)
2245 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2246 DMAE_COMMAND_SRC_SHIFT)
2247
2248 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2249 DMAE_COMMAND_DST_SHIFT)
2250 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2251 DMAE_COMMAND_DST_SHIFT)
2252
2253 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2254 DMAE_COMMAND_C_DST_SHIFT)
2255 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2256 DMAE_COMMAND_C_DST_SHIFT)
2257
2258 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2259
2260 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2261 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2262 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2263 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2264
2265 #define DMAE_CMD_PORT_0 0
2266 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2267
2268 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2269 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2270 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2271
2272 #define DMAE_SRC_PF 0
2273 #define DMAE_SRC_VF 1
2274
2275 #define DMAE_DST_PF 0
2276 #define DMAE_DST_VF 1
2277
2278 #define DMAE_C_SRC 0
2279 #define DMAE_C_DST 1
2280
2281 #define DMAE_LEN32_RD_MAX 0x80
2282 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2283
2284 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2285 * indicates error
2286 */
2287
2288 #define MAX_DMAE_C_PER_PORT 8
2289 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2290 BP_VN(bp))
2291 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2292 E1HVN_MAX)
2293
2294 /* Following is the DMAE channel number allocation for the clients.
2295 * MFW: OCBB/OCSD implementations use DMAE channels 14/15 respectively.
2296 * Driver: 0-3 and 8-11 (for PF dmae operations)
2297 * 4 and 12 (for stats requests)
2298 */
2299 #define BNX2X_FW_DMAE_C 13 /* Channel for FW DMAE operations */
2300
2301 /* PCIE link and speed */
2302 #define PCICFG_LINK_WIDTH 0x1f00000
2303 #define PCICFG_LINK_WIDTH_SHIFT 20
2304 #define PCICFG_LINK_SPEED 0xf0000
2305 #define PCICFG_LINK_SPEED_SHIFT 16
2306
2307 #define BNX2X_NUM_TESTS_SF 7
2308 #define BNX2X_NUM_TESTS_MF 3
2309 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2310 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2311
2312 #define BNX2X_PHY_LOOPBACK 0
2313 #define BNX2X_MAC_LOOPBACK 1
2314 #define BNX2X_EXT_LOOPBACK 2
2315 #define BNX2X_PHY_LOOPBACK_FAILED 1
2316 #define BNX2X_MAC_LOOPBACK_FAILED 2
2317 #define BNX2X_EXT_LOOPBACK_FAILED 3
2318 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2319 BNX2X_PHY_LOOPBACK_FAILED)
2320
2321 #define STROM_ASSERT_ARRAY_SIZE 50
2322
2323 /* must be used on a CID before placing it on a HW ring */
2324 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2325 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2326 (x))
2327
2328 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2329 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2330
2331 #define BNX2X_BTR 4
2332 #define MAX_SPQ_PENDING 8
2333
2334 /* CMNG constants, as derived from system spec calculations */
2335 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2336 #define DEF_MIN_RATE 100
2337 /* resolution of the rate shaping timer - 400 usec */
2338 #define RS_PERIODIC_TIMEOUT_USEC 400
2339 /* number of bytes in single QM arbitration cycle -
2340 * coefficient for calculating the fairness timer */
2341 #define QM_ARB_BYTES 160000
2342 /* resolution of Min algorithm 1:100 */
2343 #define MIN_RES 100
2344 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2345 #define MIN_ABOVE_THRESH 32768
2346 /* Fairness algorithm integration time coefficient -
2347 * for calculating the actual Tfair */
2348 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2349 /* Memory of fairness algorithm . 2 cycles */
2350 #define FAIR_MEM 2
2351
2352 #define ATTN_NIG_FOR_FUNC (1L << 8)
2353 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2354 #define GPIO_2_FUNC (1L << 10)
2355 #define GPIO_3_FUNC (1L << 11)
2356 #define GPIO_4_FUNC (1L << 12)
2357 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2358 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2359 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2360 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2361 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2362 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2363
2364 #define ATTN_HARD_WIRED_MASK 0xff00
2365 #define ATTENTION_ID 4
2366
2367 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \
2368 IS_MF_FCOE_AFEX(bp))
2369
2370 /* stuff added to make the code fit 80Col */
2371
2372 #define BNX2X_PMF_LINK_ASSERT \
2373 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2374
2375 #define BNX2X_MC_ASSERT_BITS \
2376 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2377 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2378 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2379 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2380
2381 #define BNX2X_MCP_ASSERT \
2382 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2383
2384 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2385 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2386 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2387 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2388 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2389 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2390 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2391
2392 #define HW_INTERRUT_ASSERT_SET_0 \
2393 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2394 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2395 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2396 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2397 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2398 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2399 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2400 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2401 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2402 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2403 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2404 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2405 #define HW_INTERRUT_ASSERT_SET_1 \
2406 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2407 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2408 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2409 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2410 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2411 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2412 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2413 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2414 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2415 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2416 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2417 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2418 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2419 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2420 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2421 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2422 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2423 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2424 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2425 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2426 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2427 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2428 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2429 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2430 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2431 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2432 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2433 #define HW_INTERRUT_ASSERT_SET_2 \
2434 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2435 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2436 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2437 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2438 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2439 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2440 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2441 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2442 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2443 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2444 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2445 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2446 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2447
2448 #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
2449 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2450 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2451 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
2452
2453 #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
2454 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2455
2456 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2457 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2458
2459 #define MULTI_MASK 0x7f
2460
2461 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2462 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2463 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2464 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2465
2466 #define DEF_USB_IGU_INDEX_OFF \
2467 offsetof(struct cstorm_def_status_block_u, igu_index)
2468 #define DEF_CSB_IGU_INDEX_OFF \
2469 offsetof(struct cstorm_def_status_block_c, igu_index)
2470 #define DEF_XSB_IGU_INDEX_OFF \
2471 offsetof(struct xstorm_def_status_block, igu_index)
2472 #define DEF_TSB_IGU_INDEX_OFF \
2473 offsetof(struct tstorm_def_status_block, igu_index)
2474
2475 #define DEF_USB_SEGMENT_OFF \
2476 offsetof(struct cstorm_def_status_block_u, segment)
2477 #define DEF_CSB_SEGMENT_OFF \
2478 offsetof(struct cstorm_def_status_block_c, segment)
2479 #define DEF_XSB_SEGMENT_OFF \
2480 offsetof(struct xstorm_def_status_block, segment)
2481 #define DEF_TSB_SEGMENT_OFF \
2482 offsetof(struct tstorm_def_status_block, segment)
2483
2484 #define BNX2X_SP_DSB_INDEX \
2485 (&bp->def_status_blk->sp_sb.\
2486 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2487
2488 #define CAM_IS_INVALID(x) \
2489 (GET_FLAG(x.flags, \
2490 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2491 (T_ETH_MAC_COMMAND_INVALIDATE))
2492
2493 /* Number of u32 elements in MC hash array */
2494 #define MC_HASH_SIZE 8
2495 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2496 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2497
2498 #ifndef PXP2_REG_PXP2_INT_STS
2499 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2500 #endif
2501
2502 #ifndef ETH_MAX_RX_CLIENTS_E2
2503 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2504 #endif
2505
2506 #define BNX2X_VPD_LEN 128
2507 #define VENDOR_ID_LEN 4
2508
2509 #define VF_ACQUIRE_THRESH 3
2510 #define VF_ACQUIRE_MAC_FILTERS 1
2511 #define VF_ACQUIRE_MC_FILTERS 10
2512 #define VF_ACQUIRE_VLAN_FILTERS 2 /* VLAN0 + 'real' VLAN */
2513
2514 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2515 (!((me_reg) & ME_REG_VF_ERR)))
2516 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
2517
2518 /* Congestion management fairness mode */
2519 #define CMNG_FNS_NONE 0
2520 #define CMNG_FNS_MINMAX 1
2521
2522 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2523 #define HC_SEG_ACCESS_ATTN 4
2524 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2525
2526 static const u32 dmae_reg_go_c[] = {
2527 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2528 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2529 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2530 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2531 };
2532
2533 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2534 void bnx2x_notify_link_changed(struct bnx2x *bp);
2535
2536 #define BNX2X_MF_SD_PROTOCOL(bp) \
2537 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2538
2539 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2540 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2541
2542 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2543 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2544
2545 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2546 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2547 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp))
2548
2549 #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp))
2550
2551 #define BNX2X_MF_EXT_PROTOCOL_MASK \
2552 (MACP_FUNC_CFG_FLAGS_ETHERNET | \
2553 MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \
2554 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2555
2556 #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \
2557 BNX2X_MF_EXT_PROTOCOL_MASK)
2558
2559 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \
2560 (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2561
2562 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \
2563 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2564
2565 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \
2566 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)
2567
2568 #define IS_MF_FCOE_AFEX(bp) \
2569 (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))
2570
2571 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \
2572 (IS_MF_SD(bp) && \
2573 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2574 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2575
2576 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \
2577 (IS_MF_SI(bp) && \
2578 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \
2579 BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)))
2580
2581 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \
2582 (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \
2583 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp))
2584
2585 /* Determines whether BW configuration arrives in 100Mb units or in
2586 * percentages from actual physical link speed.
2587 */
2588 #define IS_MF_PERCENT_BW(bp) (IS_MF_SI(bp) || IS_MF_UFP(bp) || IS_MF_BD(bp))
2589
2590 #define SET_FLAG(value, mask, flag) \
2591 do {\
2592 (value) &= ~(mask);\
2593 (value) |= ((flag) << (mask##_SHIFT));\
2594 } while (0)
2595
2596 #define GET_FLAG(value, mask) \
2597 (((value) & (mask)) >> (mask##_SHIFT))
2598
2599 #define GET_FIELD(value, fname) \
2600 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2601
2602 enum {
2603 SWITCH_UPDATE,
2604 AFEX_UPDATE,
2605 };
2606
2607 #define NUM_MACS 8
2608
2609 void bnx2x_set_local_cmng(struct bnx2x *bp);
2610
2611 void bnx2x_update_mng_version(struct bnx2x *bp);
2612
2613 void bnx2x_update_mfw_dump(struct bnx2x *bp);
2614
2615 #define MCPR_SCRATCH_BASE(bp) \
2616 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2617
2618 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2619
2620 void bnx2x_init_ptp(struct bnx2x *bp);
2621 int bnx2x_configure_ptp_filters(struct bnx2x *bp);
2622 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
2623
2624 #define BNX2X_MAX_PHC_DRIFT 31000000
2625 #define BNX2X_PTP_TX_TIMEOUT
2626
2627 /* Re-configure all previously configured vlan filters.
2628 * Meant for implicit re-load flows.
2629 */
2630 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp);
2631
2632 #endif /* bnx2x.h */
2633