1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2015 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10 #include <linux/module.h>
11
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
26 #include <linux/io.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
30 #include <asm/page.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
33 #include <linux/if.h>
34 #include <linux/if_vlan.h>
35 #include <net/ip.h>
36 #include <net/tcp.h>
37 #include <net/udp.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
42 #endif
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
45 #endif
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53
54 #include "bnxt_hsi.h"
55 #include "bnxt.h"
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
58
59 #define BNXT_TX_TIMEOUT (5 * HZ)
60
61 static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION);
67
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
71
72 #define BNXT_TX_PUSH_THRESH 92
73
74 enum board_idx {
75 BCM57302,
76 BCM57304,
77 BCM57404,
78 BCM57406,
79 BCM57304_VF,
80 BCM57404_VF,
81 };
82
83 /* indexed by enum above */
84 static const struct {
85 char *name;
86 } board_info[] = {
87 { "Broadcom BCM57302 NetXtreme-C Single-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
88 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
89 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
90 { "Broadcom BCM57406 NetXtreme-E Dual-port 10Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
92 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
93 };
94
95 static const struct pci_device_id bnxt_pci_tbl[] = {
96 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
97 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
98 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
99 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
100 #ifdef CONFIG_BNXT_SRIOV
101 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
102 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
103 #endif
104 { 0 }
105 };
106
107 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
108
109 static const u16 bnxt_vf_req_snif[] = {
110 HWRM_FUNC_CFG,
111 HWRM_PORT_PHY_QCFG,
112 HWRM_CFA_L2_FILTER_ALLOC,
113 };
114
bnxt_vf_pciid(enum board_idx idx)115 static bool bnxt_vf_pciid(enum board_idx idx)
116 {
117 return (idx == BCM57304_VF || idx == BCM57404_VF);
118 }
119
120 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
121 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
122 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
123
124 #define BNXT_CP_DB_REARM(db, raw_cons) \
125 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
126
127 #define BNXT_CP_DB(db, raw_cons) \
128 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
129
130 #define BNXT_CP_DB_IRQ_DIS(db) \
131 writel(DB_CP_IRQ_DIS_FLAGS, db)
132
bnxt_tx_avail(struct bnxt * bp,struct bnxt_tx_ring_info * txr)133 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
134 {
135 /* Tell compiler to fetch tx indices from memory. */
136 barrier();
137
138 return bp->tx_ring_size -
139 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
140 }
141
142 static const u16 bnxt_lhint_arr[] = {
143 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
144 TX_BD_FLAGS_LHINT_512_TO_1023,
145 TX_BD_FLAGS_LHINT_1024_TO_2047,
146 TX_BD_FLAGS_LHINT_1024_TO_2047,
147 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
148 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
149 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
150 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
151 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
152 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
162 };
163
bnxt_start_xmit(struct sk_buff * skb,struct net_device * dev)164 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
165 {
166 struct bnxt *bp = netdev_priv(dev);
167 struct tx_bd *txbd;
168 struct tx_bd_ext *txbd1;
169 struct netdev_queue *txq;
170 int i;
171 dma_addr_t mapping;
172 unsigned int length, pad = 0;
173 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
174 u16 prod, last_frag;
175 struct pci_dev *pdev = bp->pdev;
176 struct bnxt_napi *bnapi;
177 struct bnxt_tx_ring_info *txr;
178 struct bnxt_sw_tx_bd *tx_buf;
179
180 i = skb_get_queue_mapping(skb);
181 if (unlikely(i >= bp->tx_nr_rings)) {
182 dev_kfree_skb_any(skb);
183 return NETDEV_TX_OK;
184 }
185
186 bnapi = bp->bnapi[i];
187 txr = &bnapi->tx_ring;
188 txq = netdev_get_tx_queue(dev, i);
189 prod = txr->tx_prod;
190
191 free_size = bnxt_tx_avail(bp, txr);
192 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
193 netif_tx_stop_queue(txq);
194 return NETDEV_TX_BUSY;
195 }
196
197 length = skb->len;
198 len = skb_headlen(skb);
199 last_frag = skb_shinfo(skb)->nr_frags;
200
201 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
202
203 txbd->tx_bd_opaque = prod;
204
205 tx_buf = &txr->tx_buf_ring[prod];
206 tx_buf->skb = skb;
207 tx_buf->nr_frags = last_frag;
208
209 vlan_tag_flags = 0;
210 cfa_action = 0;
211 if (skb_vlan_tag_present(skb)) {
212 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
213 skb_vlan_tag_get(skb);
214 /* Currently supports 8021Q, 8021AD vlan offloads
215 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
216 */
217 if (skb->vlan_proto == htons(ETH_P_8021Q))
218 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
219 }
220
221 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
222 struct tx_push_bd *push = txr->tx_push;
223 struct tx_bd *tx_push = &push->txbd1;
224 struct tx_bd_ext *tx_push1 = &push->txbd2;
225 void *pdata = tx_push1 + 1;
226 int j;
227
228 /* Set COAL_NOW to be ready quickly for the next push */
229 tx_push->tx_bd_len_flags_type =
230 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
231 TX_BD_TYPE_LONG_TX_BD |
232 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
233 TX_BD_FLAGS_COAL_NOW |
234 TX_BD_FLAGS_PACKET_END |
235 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
236
237 if (skb->ip_summed == CHECKSUM_PARTIAL)
238 tx_push1->tx_bd_hsize_lflags =
239 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
240 else
241 tx_push1->tx_bd_hsize_lflags = 0;
242
243 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
244 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
245
246 skb_copy_from_linear_data(skb, pdata, len);
247 pdata += len;
248 for (j = 0; j < last_frag; j++) {
249 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
250 void *fptr;
251
252 fptr = skb_frag_address_safe(frag);
253 if (!fptr)
254 goto normal_tx;
255
256 memcpy(pdata, fptr, skb_frag_size(frag));
257 pdata += skb_frag_size(frag);
258 }
259
260 memcpy(txbd, tx_push, sizeof(*txbd));
261 prod = NEXT_TX(prod);
262 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
263 memcpy(txbd, tx_push1, sizeof(*txbd));
264 prod = NEXT_TX(prod);
265 push->doorbell =
266 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
267 txr->tx_prod = prod;
268
269 netdev_tx_sent_queue(txq, skb->len);
270
271 __iowrite64_copy(txr->tx_doorbell, push,
272 (length + sizeof(*push) + 8) / 8);
273
274 tx_buf->is_push = 1;
275
276 goto tx_done;
277 }
278
279 normal_tx:
280 if (length < BNXT_MIN_PKT_SIZE) {
281 pad = BNXT_MIN_PKT_SIZE - length;
282 if (skb_pad(skb, pad)) {
283 /* SKB already freed. */
284 tx_buf->skb = NULL;
285 return NETDEV_TX_OK;
286 }
287 length = BNXT_MIN_PKT_SIZE;
288 }
289
290 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
291
292 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
293 dev_kfree_skb_any(skb);
294 tx_buf->skb = NULL;
295 return NETDEV_TX_OK;
296 }
297
298 dma_unmap_addr_set(tx_buf, mapping, mapping);
299 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
300 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
301
302 txbd->tx_bd_haddr = cpu_to_le64(mapping);
303
304 prod = NEXT_TX(prod);
305 txbd1 = (struct tx_bd_ext *)
306 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
307
308 txbd1->tx_bd_hsize_lflags = 0;
309 if (skb_is_gso(skb)) {
310 u32 hdr_len;
311
312 if (skb->encapsulation)
313 hdr_len = skb_inner_network_offset(skb) +
314 skb_inner_network_header_len(skb) +
315 inner_tcp_hdrlen(skb);
316 else
317 hdr_len = skb_transport_offset(skb) +
318 tcp_hdrlen(skb);
319
320 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
321 TX_BD_FLAGS_T_IPID |
322 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
323 length = skb_shinfo(skb)->gso_size;
324 txbd1->tx_bd_mss = cpu_to_le32(length);
325 length += hdr_len;
326 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
327 txbd1->tx_bd_hsize_lflags =
328 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
329 txbd1->tx_bd_mss = 0;
330 }
331
332 length >>= 9;
333 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
334 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
335 skb->len);
336 i = 0;
337 goto tx_dma_error;
338 }
339 flags |= bnxt_lhint_arr[length];
340 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
341
342 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
343 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
344 for (i = 0; i < last_frag; i++) {
345 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
346
347 prod = NEXT_TX(prod);
348 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
349
350 len = skb_frag_size(frag);
351 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
352 DMA_TO_DEVICE);
353
354 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
355 goto tx_dma_error;
356
357 tx_buf = &txr->tx_buf_ring[prod];
358 dma_unmap_addr_set(tx_buf, mapping, mapping);
359
360 txbd->tx_bd_haddr = cpu_to_le64(mapping);
361
362 flags = len << TX_BD_LEN_SHIFT;
363 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
364 }
365
366 flags &= ~TX_BD_LEN;
367 txbd->tx_bd_len_flags_type =
368 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
369 TX_BD_FLAGS_PACKET_END);
370
371 netdev_tx_sent_queue(txq, skb->len);
372
373 /* Sync BD data before updating doorbell */
374 wmb();
375
376 prod = NEXT_TX(prod);
377 txr->tx_prod = prod;
378
379 writel(DB_KEY_TX | prod, txr->tx_doorbell);
380 writel(DB_KEY_TX | prod, txr->tx_doorbell);
381
382 tx_done:
383
384 mmiowb();
385
386 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
387 netif_tx_stop_queue(txq);
388
389 /* netif_tx_stop_queue() must be done before checking
390 * tx index in bnxt_tx_avail() below, because in
391 * bnxt_tx_int(), we update tx index before checking for
392 * netif_tx_queue_stopped().
393 */
394 smp_mb();
395 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
396 netif_tx_wake_queue(txq);
397 }
398 return NETDEV_TX_OK;
399
400 tx_dma_error:
401 last_frag = i;
402
403 /* start back at beginning and unmap skb */
404 prod = txr->tx_prod;
405 tx_buf = &txr->tx_buf_ring[prod];
406 tx_buf->skb = NULL;
407 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
408 skb_headlen(skb), PCI_DMA_TODEVICE);
409 prod = NEXT_TX(prod);
410
411 /* unmap remaining mapped pages */
412 for (i = 0; i < last_frag; i++) {
413 prod = NEXT_TX(prod);
414 tx_buf = &txr->tx_buf_ring[prod];
415 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
416 skb_frag_size(&skb_shinfo(skb)->frags[i]),
417 PCI_DMA_TODEVICE);
418 }
419
420 dev_kfree_skb_any(skb);
421 return NETDEV_TX_OK;
422 }
423
bnxt_tx_int(struct bnxt * bp,struct bnxt_napi * bnapi,int nr_pkts)424 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
425 {
426 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
427 int index = bnapi->index;
428 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
429 u16 cons = txr->tx_cons;
430 struct pci_dev *pdev = bp->pdev;
431 int i;
432 unsigned int tx_bytes = 0;
433
434 for (i = 0; i < nr_pkts; i++) {
435 struct bnxt_sw_tx_bd *tx_buf;
436 struct sk_buff *skb;
437 int j, last;
438
439 tx_buf = &txr->tx_buf_ring[cons];
440 cons = NEXT_TX(cons);
441 skb = tx_buf->skb;
442 tx_buf->skb = NULL;
443
444 if (tx_buf->is_push) {
445 tx_buf->is_push = 0;
446 goto next_tx_int;
447 }
448
449 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
450 skb_headlen(skb), PCI_DMA_TODEVICE);
451 last = tx_buf->nr_frags;
452
453 for (j = 0; j < last; j++) {
454 cons = NEXT_TX(cons);
455 tx_buf = &txr->tx_buf_ring[cons];
456 dma_unmap_page(
457 &pdev->dev,
458 dma_unmap_addr(tx_buf, mapping),
459 skb_frag_size(&skb_shinfo(skb)->frags[j]),
460 PCI_DMA_TODEVICE);
461 }
462
463 next_tx_int:
464 cons = NEXT_TX(cons);
465
466 tx_bytes += skb->len;
467 dev_kfree_skb_any(skb);
468 }
469
470 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
471 txr->tx_cons = cons;
472
473 /* Need to make the tx_cons update visible to bnxt_start_xmit()
474 * before checking for netif_tx_queue_stopped(). Without the
475 * memory barrier, there is a small possibility that bnxt_start_xmit()
476 * will miss it and cause the queue to be stopped forever.
477 */
478 smp_mb();
479
480 if (unlikely(netif_tx_queue_stopped(txq)) &&
481 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
482 __netif_tx_lock(txq, smp_processor_id());
483 if (netif_tx_queue_stopped(txq) &&
484 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
485 txr->dev_state != BNXT_DEV_STATE_CLOSING)
486 netif_tx_wake_queue(txq);
487 __netif_tx_unlock(txq);
488 }
489 }
490
__bnxt_alloc_rx_data(struct bnxt * bp,dma_addr_t * mapping,gfp_t gfp)491 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
492 gfp_t gfp)
493 {
494 u8 *data;
495 struct pci_dev *pdev = bp->pdev;
496
497 data = kmalloc(bp->rx_buf_size, gfp);
498 if (!data)
499 return NULL;
500
501 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
502 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
503
504 if (dma_mapping_error(&pdev->dev, *mapping)) {
505 kfree(data);
506 data = NULL;
507 }
508 return data;
509 }
510
bnxt_alloc_rx_data(struct bnxt * bp,struct bnxt_rx_ring_info * rxr,u16 prod,gfp_t gfp)511 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
512 struct bnxt_rx_ring_info *rxr,
513 u16 prod, gfp_t gfp)
514 {
515 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
516 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
517 u8 *data;
518 dma_addr_t mapping;
519
520 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
521 if (!data)
522 return -ENOMEM;
523
524 rx_buf->data = data;
525 dma_unmap_addr_set(rx_buf, mapping, mapping);
526
527 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
528
529 return 0;
530 }
531
bnxt_reuse_rx_data(struct bnxt_rx_ring_info * rxr,u16 cons,u8 * data)532 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
533 u8 *data)
534 {
535 u16 prod = rxr->rx_prod;
536 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
537 struct rx_bd *cons_bd, *prod_bd;
538
539 prod_rx_buf = &rxr->rx_buf_ring[prod];
540 cons_rx_buf = &rxr->rx_buf_ring[cons];
541
542 prod_rx_buf->data = data;
543
544 dma_unmap_addr_set(prod_rx_buf, mapping,
545 dma_unmap_addr(cons_rx_buf, mapping));
546
547 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
548 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
549
550 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
551 }
552
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info * rxr,u16 idx)553 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
554 {
555 u16 next, max = rxr->rx_agg_bmap_size;
556
557 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
558 if (next >= max)
559 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
560 return next;
561 }
562
bnxt_alloc_rx_page(struct bnxt * bp,struct bnxt_rx_ring_info * rxr,u16 prod,gfp_t gfp)563 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
564 struct bnxt_rx_ring_info *rxr,
565 u16 prod, gfp_t gfp)
566 {
567 struct rx_bd *rxbd =
568 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
569 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
570 struct pci_dev *pdev = bp->pdev;
571 struct page *page;
572 dma_addr_t mapping;
573 u16 sw_prod = rxr->rx_sw_agg_prod;
574
575 page = alloc_page(gfp);
576 if (!page)
577 return -ENOMEM;
578
579 mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
580 PCI_DMA_FROMDEVICE);
581 if (dma_mapping_error(&pdev->dev, mapping)) {
582 __free_page(page);
583 return -EIO;
584 }
585
586 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
587 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
588
589 __set_bit(sw_prod, rxr->rx_agg_bmap);
590 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
591 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
592
593 rx_agg_buf->page = page;
594 rx_agg_buf->mapping = mapping;
595 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
596 rxbd->rx_bd_opaque = sw_prod;
597 return 0;
598 }
599
bnxt_reuse_rx_agg_bufs(struct bnxt_napi * bnapi,u16 cp_cons,u32 agg_bufs)600 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
601 u32 agg_bufs)
602 {
603 struct bnxt *bp = bnapi->bp;
604 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
605 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
606 u16 prod = rxr->rx_agg_prod;
607 u16 sw_prod = rxr->rx_sw_agg_prod;
608 u32 i;
609
610 for (i = 0; i < agg_bufs; i++) {
611 u16 cons;
612 struct rx_agg_cmp *agg;
613 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
614 struct rx_bd *prod_bd;
615 struct page *page;
616
617 agg = (struct rx_agg_cmp *)
618 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
619 cons = agg->rx_agg_cmp_opaque;
620 __clear_bit(cons, rxr->rx_agg_bmap);
621
622 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
623 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
624
625 __set_bit(sw_prod, rxr->rx_agg_bmap);
626 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
627 cons_rx_buf = &rxr->rx_agg_ring[cons];
628
629 /* It is possible for sw_prod to be equal to cons, so
630 * set cons_rx_buf->page to NULL first.
631 */
632 page = cons_rx_buf->page;
633 cons_rx_buf->page = NULL;
634 prod_rx_buf->page = page;
635
636 prod_rx_buf->mapping = cons_rx_buf->mapping;
637
638 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
639
640 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
641 prod_bd->rx_bd_opaque = sw_prod;
642
643 prod = NEXT_RX_AGG(prod);
644 sw_prod = NEXT_RX_AGG(sw_prod);
645 cp_cons = NEXT_CMP(cp_cons);
646 }
647 rxr->rx_agg_prod = prod;
648 rxr->rx_sw_agg_prod = sw_prod;
649 }
650
bnxt_rx_skb(struct bnxt * bp,struct bnxt_rx_ring_info * rxr,u16 cons,u16 prod,u8 * data,dma_addr_t dma_addr,unsigned int len)651 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
652 struct bnxt_rx_ring_info *rxr, u16 cons,
653 u16 prod, u8 *data, dma_addr_t dma_addr,
654 unsigned int len)
655 {
656 int err;
657 struct sk_buff *skb;
658
659 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
660 if (unlikely(err)) {
661 bnxt_reuse_rx_data(rxr, cons, data);
662 return NULL;
663 }
664
665 skb = build_skb(data, 0);
666 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
667 PCI_DMA_FROMDEVICE);
668 if (!skb) {
669 kfree(data);
670 return NULL;
671 }
672
673 skb_reserve(skb, BNXT_RX_OFFSET);
674 skb_put(skb, len);
675 return skb;
676 }
677
bnxt_rx_pages(struct bnxt * bp,struct bnxt_napi * bnapi,struct sk_buff * skb,u16 cp_cons,u32 agg_bufs)678 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
679 struct sk_buff *skb, u16 cp_cons,
680 u32 agg_bufs)
681 {
682 struct pci_dev *pdev = bp->pdev;
683 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
684 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
685 u16 prod = rxr->rx_agg_prod;
686 u32 i;
687
688 for (i = 0; i < agg_bufs; i++) {
689 u16 cons, frag_len;
690 struct rx_agg_cmp *agg;
691 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
692 struct page *page;
693 dma_addr_t mapping;
694
695 agg = (struct rx_agg_cmp *)
696 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
697 cons = agg->rx_agg_cmp_opaque;
698 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
699 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
700
701 cons_rx_buf = &rxr->rx_agg_ring[cons];
702 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
703 __clear_bit(cons, rxr->rx_agg_bmap);
704
705 /* It is possible for bnxt_alloc_rx_page() to allocate
706 * a sw_prod index that equals the cons index, so we
707 * need to clear the cons entry now.
708 */
709 mapping = dma_unmap_addr(cons_rx_buf, mapping);
710 page = cons_rx_buf->page;
711 cons_rx_buf->page = NULL;
712
713 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
714 struct skb_shared_info *shinfo;
715 unsigned int nr_frags;
716
717 shinfo = skb_shinfo(skb);
718 nr_frags = --shinfo->nr_frags;
719 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
720
721 dev_kfree_skb(skb);
722
723 cons_rx_buf->page = page;
724
725 /* Update prod since possibly some pages have been
726 * allocated already.
727 */
728 rxr->rx_agg_prod = prod;
729 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
730 return NULL;
731 }
732
733 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
734 PCI_DMA_FROMDEVICE);
735
736 skb->data_len += frag_len;
737 skb->len += frag_len;
738 skb->truesize += PAGE_SIZE;
739
740 prod = NEXT_RX_AGG(prod);
741 cp_cons = NEXT_CMP(cp_cons);
742 }
743 rxr->rx_agg_prod = prod;
744 return skb;
745 }
746
bnxt_agg_bufs_valid(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,u8 agg_bufs,u32 * raw_cons)747 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
748 u8 agg_bufs, u32 *raw_cons)
749 {
750 u16 last;
751 struct rx_agg_cmp *agg;
752
753 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
754 last = RING_CMP(*raw_cons);
755 agg = (struct rx_agg_cmp *)
756 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
757 return RX_AGG_CMP_VALID(agg, *raw_cons);
758 }
759
bnxt_copy_skb(struct bnxt_napi * bnapi,u8 * data,unsigned int len,dma_addr_t mapping)760 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
761 unsigned int len,
762 dma_addr_t mapping)
763 {
764 struct bnxt *bp = bnapi->bp;
765 struct pci_dev *pdev = bp->pdev;
766 struct sk_buff *skb;
767
768 skb = napi_alloc_skb(&bnapi->napi, len);
769 if (!skb)
770 return NULL;
771
772 dma_sync_single_for_cpu(&pdev->dev, mapping,
773 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
774
775 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
776
777 dma_sync_single_for_device(&pdev->dev, mapping,
778 bp->rx_copy_thresh,
779 PCI_DMA_FROMDEVICE);
780
781 skb_put(skb, len);
782 return skb;
783 }
784
bnxt_tpa_start(struct bnxt * bp,struct bnxt_rx_ring_info * rxr,struct rx_tpa_start_cmp * tpa_start,struct rx_tpa_start_cmp_ext * tpa_start1)785 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
786 struct rx_tpa_start_cmp *tpa_start,
787 struct rx_tpa_start_cmp_ext *tpa_start1)
788 {
789 u8 agg_id = TPA_START_AGG_ID(tpa_start);
790 u16 cons, prod;
791 struct bnxt_tpa_info *tpa_info;
792 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
793 struct rx_bd *prod_bd;
794 dma_addr_t mapping;
795
796 cons = tpa_start->rx_tpa_start_cmp_opaque;
797 prod = rxr->rx_prod;
798 cons_rx_buf = &rxr->rx_buf_ring[cons];
799 prod_rx_buf = &rxr->rx_buf_ring[prod];
800 tpa_info = &rxr->rx_tpa[agg_id];
801
802 prod_rx_buf->data = tpa_info->data;
803
804 mapping = tpa_info->mapping;
805 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
806
807 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
808
809 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
810
811 tpa_info->data = cons_rx_buf->data;
812 cons_rx_buf->data = NULL;
813 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
814
815 tpa_info->len =
816 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
817 RX_TPA_START_CMP_LEN_SHIFT;
818 if (likely(TPA_START_HASH_VALID(tpa_start))) {
819 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
820
821 tpa_info->hash_type = PKT_HASH_TYPE_L4;
822 tpa_info->gso_type = SKB_GSO_TCPV4;
823 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
824 if (hash_type == 3)
825 tpa_info->gso_type = SKB_GSO_TCPV6;
826 tpa_info->rss_hash =
827 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
828 } else {
829 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
830 tpa_info->gso_type = 0;
831 if (netif_msg_rx_err(bp))
832 netdev_warn(bp->dev, "TPA packet without valid hash\n");
833 }
834 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
835 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
836
837 rxr->rx_prod = NEXT_RX(prod);
838 cons = NEXT_RX(cons);
839 cons_rx_buf = &rxr->rx_buf_ring[cons];
840
841 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
842 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
843 cons_rx_buf->data = NULL;
844 }
845
bnxt_abort_tpa(struct bnxt * bp,struct bnxt_napi * bnapi,u16 cp_cons,u32 agg_bufs)846 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
847 u16 cp_cons, u32 agg_bufs)
848 {
849 if (agg_bufs)
850 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
851 }
852
853 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
854 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
855
bnxt_gro_skb(struct bnxt_tpa_info * tpa_info,struct rx_tpa_end_cmp * tpa_end,struct rx_tpa_end_cmp_ext * tpa_end1,struct sk_buff * skb)856 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
857 struct rx_tpa_end_cmp *tpa_end,
858 struct rx_tpa_end_cmp_ext *tpa_end1,
859 struct sk_buff *skb)
860 {
861 #ifdef CONFIG_INET
862 struct tcphdr *th;
863 int payload_off, tcp_opt_len = 0;
864 int len, nw_off;
865
866 NAPI_GRO_CB(skb)->count = TPA_END_TPA_SEGS(tpa_end);
867 skb_shinfo(skb)->gso_size =
868 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
869 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
870 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
871 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
872 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
873 if (TPA_END_GRO_TS(tpa_end))
874 tcp_opt_len = 12;
875
876 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
877 struct iphdr *iph;
878
879 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
880 ETH_HLEN;
881 skb_set_network_header(skb, nw_off);
882 iph = ip_hdr(skb);
883 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
884 len = skb->len - skb_transport_offset(skb);
885 th = tcp_hdr(skb);
886 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
887 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
888 struct ipv6hdr *iph;
889
890 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
891 ETH_HLEN;
892 skb_set_network_header(skb, nw_off);
893 iph = ipv6_hdr(skb);
894 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
895 len = skb->len - skb_transport_offset(skb);
896 th = tcp_hdr(skb);
897 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
898 } else {
899 dev_kfree_skb_any(skb);
900 return NULL;
901 }
902 tcp_gro_complete(skb);
903
904 if (nw_off) { /* tunnel */
905 struct udphdr *uh = NULL;
906
907 if (skb->protocol == htons(ETH_P_IP)) {
908 struct iphdr *iph = (struct iphdr *)skb->data;
909
910 if (iph->protocol == IPPROTO_UDP)
911 uh = (struct udphdr *)(iph + 1);
912 } else {
913 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
914
915 if (iph->nexthdr == IPPROTO_UDP)
916 uh = (struct udphdr *)(iph + 1);
917 }
918 if (uh) {
919 if (uh->check)
920 skb_shinfo(skb)->gso_type |=
921 SKB_GSO_UDP_TUNNEL_CSUM;
922 else
923 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
924 }
925 }
926 #endif
927 return skb;
928 }
929
bnxt_tpa_end(struct bnxt * bp,struct bnxt_napi * bnapi,u32 * raw_cons,struct rx_tpa_end_cmp * tpa_end,struct rx_tpa_end_cmp_ext * tpa_end1,bool * agg_event)930 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
931 struct bnxt_napi *bnapi,
932 u32 *raw_cons,
933 struct rx_tpa_end_cmp *tpa_end,
934 struct rx_tpa_end_cmp_ext *tpa_end1,
935 bool *agg_event)
936 {
937 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
938 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
939 u8 agg_id = TPA_END_AGG_ID(tpa_end);
940 u8 *data, agg_bufs;
941 u16 cp_cons = RING_CMP(*raw_cons);
942 unsigned int len;
943 struct bnxt_tpa_info *tpa_info;
944 dma_addr_t mapping;
945 struct sk_buff *skb;
946
947 tpa_info = &rxr->rx_tpa[agg_id];
948 data = tpa_info->data;
949 prefetch(data);
950 len = tpa_info->len;
951 mapping = tpa_info->mapping;
952
953 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
954 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
955
956 if (agg_bufs) {
957 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
958 return ERR_PTR(-EBUSY);
959
960 *agg_event = true;
961 cp_cons = NEXT_CMP(cp_cons);
962 }
963
964 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
965 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
966 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
967 agg_bufs, (int)MAX_SKB_FRAGS);
968 return NULL;
969 }
970
971 if (len <= bp->rx_copy_thresh) {
972 skb = bnxt_copy_skb(bnapi, data, len, mapping);
973 if (!skb) {
974 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
975 return NULL;
976 }
977 } else {
978 u8 *new_data;
979 dma_addr_t new_mapping;
980
981 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
982 if (!new_data) {
983 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
984 return NULL;
985 }
986
987 tpa_info->data = new_data;
988 tpa_info->mapping = new_mapping;
989
990 skb = build_skb(data, 0);
991 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
992 PCI_DMA_FROMDEVICE);
993
994 if (!skb) {
995 kfree(data);
996 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
997 return NULL;
998 }
999 skb_reserve(skb, BNXT_RX_OFFSET);
1000 skb_put(skb, len);
1001 }
1002
1003 if (agg_bufs) {
1004 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1005 if (!skb) {
1006 /* Page reuse already handled by bnxt_rx_pages(). */
1007 return NULL;
1008 }
1009 }
1010 skb->protocol = eth_type_trans(skb, bp->dev);
1011
1012 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1013 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1014
1015 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1016 netdev_features_t features = skb->dev->features;
1017 u16 vlan_proto = tpa_info->metadata >>
1018 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1019
1020 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1021 vlan_proto == ETH_P_8021Q) ||
1022 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1023 vlan_proto == ETH_P_8021AD)) {
1024 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1025 tpa_info->metadata &
1026 RX_CMP_FLAGS2_METADATA_VID_MASK);
1027 }
1028 }
1029
1030 skb_checksum_none_assert(skb);
1031 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1032 skb->ip_summed = CHECKSUM_UNNECESSARY;
1033 skb->csum_level =
1034 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1035 }
1036
1037 if (TPA_END_GRO(tpa_end))
1038 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1039
1040 return skb;
1041 }
1042
1043 /* returns the following:
1044 * 1 - 1 packet successfully received
1045 * 0 - successful TPA_START, packet not completed yet
1046 * -EBUSY - completion ring does not have all the agg buffers yet
1047 * -ENOMEM - packet aborted due to out of memory
1048 * -EIO - packet aborted due to hw error indicated in BD
1049 */
bnxt_rx_pkt(struct bnxt * bp,struct bnxt_napi * bnapi,u32 * raw_cons,bool * agg_event)1050 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1051 bool *agg_event)
1052 {
1053 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1054 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
1055 struct net_device *dev = bp->dev;
1056 struct rx_cmp *rxcmp;
1057 struct rx_cmp_ext *rxcmp1;
1058 u32 tmp_raw_cons = *raw_cons;
1059 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1060 struct bnxt_sw_rx_bd *rx_buf;
1061 unsigned int len;
1062 u8 *data, agg_bufs, cmp_type;
1063 dma_addr_t dma_addr;
1064 struct sk_buff *skb;
1065 int rc = 0;
1066
1067 rxcmp = (struct rx_cmp *)
1068 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1069
1070 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1071 cp_cons = RING_CMP(tmp_raw_cons);
1072 rxcmp1 = (struct rx_cmp_ext *)
1073 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1074
1075 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1076 return -EBUSY;
1077
1078 cmp_type = RX_CMP_TYPE(rxcmp);
1079
1080 prod = rxr->rx_prod;
1081
1082 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1083 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1084 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1085
1086 goto next_rx_no_prod;
1087
1088 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1089 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1090 (struct rx_tpa_end_cmp *)rxcmp,
1091 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1092 agg_event);
1093
1094 if (unlikely(IS_ERR(skb)))
1095 return -EBUSY;
1096
1097 rc = -ENOMEM;
1098 if (likely(skb)) {
1099 skb_record_rx_queue(skb, bnapi->index);
1100 skb_mark_napi_id(skb, &bnapi->napi);
1101 if (bnxt_busy_polling(bnapi))
1102 netif_receive_skb(skb);
1103 else
1104 napi_gro_receive(&bnapi->napi, skb);
1105 rc = 1;
1106 }
1107 goto next_rx_no_prod;
1108 }
1109
1110 cons = rxcmp->rx_cmp_opaque;
1111 rx_buf = &rxr->rx_buf_ring[cons];
1112 data = rx_buf->data;
1113 prefetch(data);
1114
1115 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1116 RX_CMP_AGG_BUFS_SHIFT;
1117
1118 if (agg_bufs) {
1119 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1120 return -EBUSY;
1121
1122 cp_cons = NEXT_CMP(cp_cons);
1123 *agg_event = true;
1124 }
1125
1126 rx_buf->data = NULL;
1127 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1128 bnxt_reuse_rx_data(rxr, cons, data);
1129 if (agg_bufs)
1130 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1131
1132 rc = -EIO;
1133 goto next_rx;
1134 }
1135
1136 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1137 dma_addr = dma_unmap_addr(rx_buf, mapping);
1138
1139 if (len <= bp->rx_copy_thresh) {
1140 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1141 bnxt_reuse_rx_data(rxr, cons, data);
1142 if (!skb) {
1143 if (agg_bufs)
1144 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1145 rc = -ENOMEM;
1146 goto next_rx;
1147 }
1148 } else {
1149 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1150 if (!skb) {
1151 rc = -ENOMEM;
1152 goto next_rx;
1153 }
1154 }
1155
1156 if (agg_bufs) {
1157 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1158 if (!skb) {
1159 rc = -ENOMEM;
1160 goto next_rx;
1161 }
1162 }
1163
1164 if (RX_CMP_HASH_VALID(rxcmp)) {
1165 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1166 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1167
1168 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1169 if (hash_type != 1 && hash_type != 3)
1170 type = PKT_HASH_TYPE_L3;
1171 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1172 }
1173
1174 skb->protocol = eth_type_trans(skb, dev);
1175
1176 if (rxcmp1->rx_cmp_flags2 &
1177 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1178 netdev_features_t features = skb->dev->features;
1179 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1180 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1181
1182 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1183 vlan_proto == ETH_P_8021Q) ||
1184 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1185 vlan_proto == ETH_P_8021AD))
1186 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1187 meta_data &
1188 RX_CMP_FLAGS2_METADATA_VID_MASK);
1189 }
1190
1191 skb_checksum_none_assert(skb);
1192 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1193 if (dev->features & NETIF_F_RXCSUM) {
1194 skb->ip_summed = CHECKSUM_UNNECESSARY;
1195 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1196 }
1197 } else {
1198 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)
1199 cpr->rx_l4_csum_errors++;
1200 }
1201
1202 skb_record_rx_queue(skb, bnapi->index);
1203 skb_mark_napi_id(skb, &bnapi->napi);
1204 if (bnxt_busy_polling(bnapi))
1205 netif_receive_skb(skb);
1206 else
1207 napi_gro_receive(&bnapi->napi, skb);
1208 rc = 1;
1209
1210 next_rx:
1211 rxr->rx_prod = NEXT_RX(prod);
1212
1213 next_rx_no_prod:
1214 *raw_cons = tmp_raw_cons;
1215
1216 return rc;
1217 }
1218
bnxt_async_event_process(struct bnxt * bp,struct hwrm_async_event_cmpl * cmpl)1219 static int bnxt_async_event_process(struct bnxt *bp,
1220 struct hwrm_async_event_cmpl *cmpl)
1221 {
1222 u16 event_id = le16_to_cpu(cmpl->event_id);
1223
1224 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1225 switch (event_id) {
1226 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1227 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1228 schedule_work(&bp->sp_task);
1229 break;
1230 default:
1231 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1232 event_id);
1233 break;
1234 }
1235 return 0;
1236 }
1237
bnxt_hwrm_handler(struct bnxt * bp,struct tx_cmp * txcmp)1238 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1239 {
1240 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1241 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1242 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1243 (struct hwrm_fwd_req_cmpl *)txcmp;
1244
1245 switch (cmpl_type) {
1246 case CMPL_BASE_TYPE_HWRM_DONE:
1247 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1248 if (seq_id == bp->hwrm_intr_seq_id)
1249 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1250 else
1251 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1252 break;
1253
1254 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1255 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1256
1257 if ((vf_id < bp->pf.first_vf_id) ||
1258 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1259 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1260 vf_id);
1261 return -EINVAL;
1262 }
1263
1264 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1265 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1266 schedule_work(&bp->sp_task);
1267 break;
1268
1269 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1270 bnxt_async_event_process(bp,
1271 (struct hwrm_async_event_cmpl *)txcmp);
1272
1273 default:
1274 break;
1275 }
1276
1277 return 0;
1278 }
1279
bnxt_msix(int irq,void * dev_instance)1280 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1281 {
1282 struct bnxt_napi *bnapi = dev_instance;
1283 struct bnxt *bp = bnapi->bp;
1284 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1285 u32 cons = RING_CMP(cpr->cp_raw_cons);
1286
1287 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1288 napi_schedule(&bnapi->napi);
1289 return IRQ_HANDLED;
1290 }
1291
bnxt_has_work(struct bnxt * bp,struct bnxt_cp_ring_info * cpr)1292 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1293 {
1294 u32 raw_cons = cpr->cp_raw_cons;
1295 u16 cons = RING_CMP(raw_cons);
1296 struct tx_cmp *txcmp;
1297
1298 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1299
1300 return TX_CMP_VALID(txcmp, raw_cons);
1301 }
1302
bnxt_inta(int irq,void * dev_instance)1303 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1304 {
1305 struct bnxt_napi *bnapi = dev_instance;
1306 struct bnxt *bp = bnapi->bp;
1307 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1308 u32 cons = RING_CMP(cpr->cp_raw_cons);
1309 u32 int_status;
1310
1311 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1312
1313 if (!bnxt_has_work(bp, cpr)) {
1314 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1315 /* return if erroneous interrupt */
1316 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1317 return IRQ_NONE;
1318 }
1319
1320 /* disable ring IRQ */
1321 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1322
1323 /* Return here if interrupt is shared and is disabled. */
1324 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1325 return IRQ_HANDLED;
1326
1327 napi_schedule(&bnapi->napi);
1328 return IRQ_HANDLED;
1329 }
1330
bnxt_poll_work(struct bnxt * bp,struct bnxt_napi * bnapi,int budget)1331 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1332 {
1333 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1334 u32 raw_cons = cpr->cp_raw_cons;
1335 u32 cons;
1336 int tx_pkts = 0;
1337 int rx_pkts = 0;
1338 bool rx_event = false;
1339 bool agg_event = false;
1340 struct tx_cmp *txcmp;
1341
1342 while (1) {
1343 int rc;
1344
1345 cons = RING_CMP(raw_cons);
1346 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1347
1348 if (!TX_CMP_VALID(txcmp, raw_cons))
1349 break;
1350
1351 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1352 tx_pkts++;
1353 /* return full budget so NAPI will complete. */
1354 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1355 rx_pkts = budget;
1356 raw_cons = NEXT_RAW_CMP(raw_cons);
1357 break;
1358 }
1359 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1360 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1361 if (likely(rc >= 0))
1362 rx_pkts += rc;
1363 else if (rc == -EBUSY) /* partial completion */
1364 break;
1365 rx_event = true;
1366 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1367 CMPL_BASE_TYPE_HWRM_DONE) ||
1368 (TX_CMP_TYPE(txcmp) ==
1369 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1370 (TX_CMP_TYPE(txcmp) ==
1371 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1372 bnxt_hwrm_handler(bp, txcmp);
1373 }
1374 raw_cons = NEXT_RAW_CMP(raw_cons);
1375
1376 if (rx_pkts && rx_pkts == budget)
1377 break;
1378 }
1379
1380 cpr->cp_raw_cons = raw_cons;
1381 /* ACK completion ring before freeing tx ring and producing new
1382 * buffers in rx/agg rings to prevent overflowing the completion
1383 * ring.
1384 */
1385 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1386
1387 if (tx_pkts)
1388 bnxt_tx_int(bp, bnapi, tx_pkts);
1389
1390 if (rx_event) {
1391 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
1392
1393 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1394 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1395 if (agg_event) {
1396 writel(DB_KEY_RX | rxr->rx_agg_prod,
1397 rxr->rx_agg_doorbell);
1398 writel(DB_KEY_RX | rxr->rx_agg_prod,
1399 rxr->rx_agg_doorbell);
1400 }
1401 }
1402 return rx_pkts;
1403 }
1404
bnxt_poll(struct napi_struct * napi,int budget)1405 static int bnxt_poll(struct napi_struct *napi, int budget)
1406 {
1407 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1408 struct bnxt *bp = bnapi->bp;
1409 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1410 int work_done = 0;
1411
1412 if (!bnxt_lock_napi(bnapi))
1413 return budget;
1414
1415 while (1) {
1416 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1417
1418 if (work_done >= budget) {
1419 if (!budget)
1420 BNXT_CP_DB_REARM(cpr->cp_doorbell,
1421 cpr->cp_raw_cons);
1422 break;
1423 }
1424
1425 if (!bnxt_has_work(bp, cpr)) {
1426 napi_complete(napi);
1427 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1428 break;
1429 }
1430 }
1431 mmiowb();
1432 bnxt_unlock_napi(bnapi);
1433 return work_done;
1434 }
1435
1436 #ifdef CONFIG_NET_RX_BUSY_POLL
bnxt_busy_poll(struct napi_struct * napi)1437 static int bnxt_busy_poll(struct napi_struct *napi)
1438 {
1439 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1440 struct bnxt *bp = bnapi->bp;
1441 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1442 int rx_work, budget = 4;
1443
1444 if (atomic_read(&bp->intr_sem) != 0)
1445 return LL_FLUSH_FAILED;
1446
1447 if (!bnxt_lock_poll(bnapi))
1448 return LL_FLUSH_BUSY;
1449
1450 rx_work = bnxt_poll_work(bp, bnapi, budget);
1451
1452 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1453
1454 bnxt_unlock_poll(bnapi);
1455 return rx_work;
1456 }
1457 #endif
1458
bnxt_free_tx_skbs(struct bnxt * bp)1459 static void bnxt_free_tx_skbs(struct bnxt *bp)
1460 {
1461 int i, max_idx;
1462 struct pci_dev *pdev = bp->pdev;
1463
1464 if (!bp->bnapi)
1465 return;
1466
1467 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1468 for (i = 0; i < bp->tx_nr_rings; i++) {
1469 struct bnxt_napi *bnapi = bp->bnapi[i];
1470 struct bnxt_tx_ring_info *txr;
1471 int j;
1472
1473 if (!bnapi)
1474 continue;
1475
1476 txr = &bnapi->tx_ring;
1477 for (j = 0; j < max_idx;) {
1478 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1479 struct sk_buff *skb = tx_buf->skb;
1480 int k, last;
1481
1482 if (!skb) {
1483 j++;
1484 continue;
1485 }
1486
1487 tx_buf->skb = NULL;
1488
1489 if (tx_buf->is_push) {
1490 dev_kfree_skb(skb);
1491 j += 2;
1492 continue;
1493 }
1494
1495 dma_unmap_single(&pdev->dev,
1496 dma_unmap_addr(tx_buf, mapping),
1497 skb_headlen(skb),
1498 PCI_DMA_TODEVICE);
1499
1500 last = tx_buf->nr_frags;
1501 j += 2;
1502 for (k = 0; k < last; k++, j = NEXT_TX(j)) {
1503 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1504
1505 tx_buf = &txr->tx_buf_ring[j];
1506 dma_unmap_page(
1507 &pdev->dev,
1508 dma_unmap_addr(tx_buf, mapping),
1509 skb_frag_size(frag), PCI_DMA_TODEVICE);
1510 }
1511 dev_kfree_skb(skb);
1512 }
1513 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1514 }
1515 }
1516
bnxt_free_rx_skbs(struct bnxt * bp)1517 static void bnxt_free_rx_skbs(struct bnxt *bp)
1518 {
1519 int i, max_idx, max_agg_idx;
1520 struct pci_dev *pdev = bp->pdev;
1521
1522 if (!bp->bnapi)
1523 return;
1524
1525 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1526 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1527 for (i = 0; i < bp->rx_nr_rings; i++) {
1528 struct bnxt_napi *bnapi = bp->bnapi[i];
1529 struct bnxt_rx_ring_info *rxr;
1530 int j;
1531
1532 if (!bnapi)
1533 continue;
1534
1535 rxr = &bnapi->rx_ring;
1536
1537 if (rxr->rx_tpa) {
1538 for (j = 0; j < MAX_TPA; j++) {
1539 struct bnxt_tpa_info *tpa_info =
1540 &rxr->rx_tpa[j];
1541 u8 *data = tpa_info->data;
1542
1543 if (!data)
1544 continue;
1545
1546 dma_unmap_single(
1547 &pdev->dev,
1548 dma_unmap_addr(tpa_info, mapping),
1549 bp->rx_buf_use_size,
1550 PCI_DMA_FROMDEVICE);
1551
1552 tpa_info->data = NULL;
1553
1554 kfree(data);
1555 }
1556 }
1557
1558 for (j = 0; j < max_idx; j++) {
1559 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1560 u8 *data = rx_buf->data;
1561
1562 if (!data)
1563 continue;
1564
1565 dma_unmap_single(&pdev->dev,
1566 dma_unmap_addr(rx_buf, mapping),
1567 bp->rx_buf_use_size,
1568 PCI_DMA_FROMDEVICE);
1569
1570 rx_buf->data = NULL;
1571
1572 kfree(data);
1573 }
1574
1575 for (j = 0; j < max_agg_idx; j++) {
1576 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1577 &rxr->rx_agg_ring[j];
1578 struct page *page = rx_agg_buf->page;
1579
1580 if (!page)
1581 continue;
1582
1583 dma_unmap_page(&pdev->dev,
1584 dma_unmap_addr(rx_agg_buf, mapping),
1585 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1586
1587 rx_agg_buf->page = NULL;
1588 __clear_bit(j, rxr->rx_agg_bmap);
1589
1590 __free_page(page);
1591 }
1592 }
1593 }
1594
bnxt_free_skbs(struct bnxt * bp)1595 static void bnxt_free_skbs(struct bnxt *bp)
1596 {
1597 bnxt_free_tx_skbs(bp);
1598 bnxt_free_rx_skbs(bp);
1599 }
1600
bnxt_free_ring(struct bnxt * bp,struct bnxt_ring_struct * ring)1601 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1602 {
1603 struct pci_dev *pdev = bp->pdev;
1604 int i;
1605
1606 for (i = 0; i < ring->nr_pages; i++) {
1607 if (!ring->pg_arr[i])
1608 continue;
1609
1610 dma_free_coherent(&pdev->dev, ring->page_size,
1611 ring->pg_arr[i], ring->dma_arr[i]);
1612
1613 ring->pg_arr[i] = NULL;
1614 }
1615 if (ring->pg_tbl) {
1616 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1617 ring->pg_tbl, ring->pg_tbl_map);
1618 ring->pg_tbl = NULL;
1619 }
1620 if (ring->vmem_size && *ring->vmem) {
1621 vfree(*ring->vmem);
1622 *ring->vmem = NULL;
1623 }
1624 }
1625
bnxt_alloc_ring(struct bnxt * bp,struct bnxt_ring_struct * ring)1626 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1627 {
1628 int i;
1629 struct pci_dev *pdev = bp->pdev;
1630
1631 if (ring->nr_pages > 1) {
1632 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1633 ring->nr_pages * 8,
1634 &ring->pg_tbl_map,
1635 GFP_KERNEL);
1636 if (!ring->pg_tbl)
1637 return -ENOMEM;
1638 }
1639
1640 for (i = 0; i < ring->nr_pages; i++) {
1641 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1642 ring->page_size,
1643 &ring->dma_arr[i],
1644 GFP_KERNEL);
1645 if (!ring->pg_arr[i])
1646 return -ENOMEM;
1647
1648 if (ring->nr_pages > 1)
1649 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1650 }
1651
1652 if (ring->vmem_size) {
1653 *ring->vmem = vzalloc(ring->vmem_size);
1654 if (!(*ring->vmem))
1655 return -ENOMEM;
1656 }
1657 return 0;
1658 }
1659
bnxt_free_rx_rings(struct bnxt * bp)1660 static void bnxt_free_rx_rings(struct bnxt *bp)
1661 {
1662 int i;
1663
1664 if (!bp->bnapi)
1665 return;
1666
1667 for (i = 0; i < bp->rx_nr_rings; i++) {
1668 struct bnxt_napi *bnapi = bp->bnapi[i];
1669 struct bnxt_rx_ring_info *rxr;
1670 struct bnxt_ring_struct *ring;
1671
1672 if (!bnapi)
1673 continue;
1674
1675 rxr = &bnapi->rx_ring;
1676
1677 kfree(rxr->rx_tpa);
1678 rxr->rx_tpa = NULL;
1679
1680 kfree(rxr->rx_agg_bmap);
1681 rxr->rx_agg_bmap = NULL;
1682
1683 ring = &rxr->rx_ring_struct;
1684 bnxt_free_ring(bp, ring);
1685
1686 ring = &rxr->rx_agg_ring_struct;
1687 bnxt_free_ring(bp, ring);
1688 }
1689 }
1690
bnxt_alloc_rx_rings(struct bnxt * bp)1691 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1692 {
1693 int i, rc, agg_rings = 0, tpa_rings = 0;
1694
1695 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1696 agg_rings = 1;
1697
1698 if (bp->flags & BNXT_FLAG_TPA)
1699 tpa_rings = 1;
1700
1701 for (i = 0; i < bp->rx_nr_rings; i++) {
1702 struct bnxt_napi *bnapi = bp->bnapi[i];
1703 struct bnxt_rx_ring_info *rxr;
1704 struct bnxt_ring_struct *ring;
1705
1706 if (!bnapi)
1707 continue;
1708
1709 rxr = &bnapi->rx_ring;
1710 ring = &rxr->rx_ring_struct;
1711
1712 rc = bnxt_alloc_ring(bp, ring);
1713 if (rc)
1714 return rc;
1715
1716 if (agg_rings) {
1717 u16 mem_size;
1718
1719 ring = &rxr->rx_agg_ring_struct;
1720 rc = bnxt_alloc_ring(bp, ring);
1721 if (rc)
1722 return rc;
1723
1724 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1725 mem_size = rxr->rx_agg_bmap_size / 8;
1726 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1727 if (!rxr->rx_agg_bmap)
1728 return -ENOMEM;
1729
1730 if (tpa_rings) {
1731 rxr->rx_tpa = kcalloc(MAX_TPA,
1732 sizeof(struct bnxt_tpa_info),
1733 GFP_KERNEL);
1734 if (!rxr->rx_tpa)
1735 return -ENOMEM;
1736 }
1737 }
1738 }
1739 return 0;
1740 }
1741
bnxt_free_tx_rings(struct bnxt * bp)1742 static void bnxt_free_tx_rings(struct bnxt *bp)
1743 {
1744 int i;
1745 struct pci_dev *pdev = bp->pdev;
1746
1747 if (!bp->bnapi)
1748 return;
1749
1750 for (i = 0; i < bp->tx_nr_rings; i++) {
1751 struct bnxt_napi *bnapi = bp->bnapi[i];
1752 struct bnxt_tx_ring_info *txr;
1753 struct bnxt_ring_struct *ring;
1754
1755 if (!bnapi)
1756 continue;
1757
1758 txr = &bnapi->tx_ring;
1759
1760 if (txr->tx_push) {
1761 dma_free_coherent(&pdev->dev, bp->tx_push_size,
1762 txr->tx_push, txr->tx_push_mapping);
1763 txr->tx_push = NULL;
1764 }
1765
1766 ring = &txr->tx_ring_struct;
1767
1768 bnxt_free_ring(bp, ring);
1769 }
1770 }
1771
bnxt_alloc_tx_rings(struct bnxt * bp)1772 static int bnxt_alloc_tx_rings(struct bnxt *bp)
1773 {
1774 int i, j, rc;
1775 struct pci_dev *pdev = bp->pdev;
1776
1777 bp->tx_push_size = 0;
1778 if (bp->tx_push_thresh) {
1779 int push_size;
1780
1781 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1782 bp->tx_push_thresh);
1783
1784 if (push_size > 128) {
1785 push_size = 0;
1786 bp->tx_push_thresh = 0;
1787 }
1788
1789 bp->tx_push_size = push_size;
1790 }
1791
1792 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1793 struct bnxt_napi *bnapi = bp->bnapi[i];
1794 struct bnxt_tx_ring_info *txr;
1795 struct bnxt_ring_struct *ring;
1796
1797 if (!bnapi)
1798 continue;
1799
1800 txr = &bnapi->tx_ring;
1801 ring = &txr->tx_ring_struct;
1802
1803 rc = bnxt_alloc_ring(bp, ring);
1804 if (rc)
1805 return rc;
1806
1807 if (bp->tx_push_size) {
1808 struct tx_bd *txbd;
1809 dma_addr_t mapping;
1810
1811 /* One pre-allocated DMA buffer to backup
1812 * TX push operation
1813 */
1814 txr->tx_push = dma_alloc_coherent(&pdev->dev,
1815 bp->tx_push_size,
1816 &txr->tx_push_mapping,
1817 GFP_KERNEL);
1818
1819 if (!txr->tx_push)
1820 return -ENOMEM;
1821
1822 txbd = &txr->tx_push->txbd1;
1823
1824 mapping = txr->tx_push_mapping +
1825 sizeof(struct tx_push_bd);
1826 txbd->tx_bd_haddr = cpu_to_le64(mapping);
1827
1828 memset(txbd + 1, 0, sizeof(struct tx_bd_ext));
1829 }
1830 ring->queue_id = bp->q_info[j].queue_id;
1831 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1832 j++;
1833 }
1834 return 0;
1835 }
1836
bnxt_free_cp_rings(struct bnxt * bp)1837 static void bnxt_free_cp_rings(struct bnxt *bp)
1838 {
1839 int i;
1840
1841 if (!bp->bnapi)
1842 return;
1843
1844 for (i = 0; i < bp->cp_nr_rings; i++) {
1845 struct bnxt_napi *bnapi = bp->bnapi[i];
1846 struct bnxt_cp_ring_info *cpr;
1847 struct bnxt_ring_struct *ring;
1848
1849 if (!bnapi)
1850 continue;
1851
1852 cpr = &bnapi->cp_ring;
1853 ring = &cpr->cp_ring_struct;
1854
1855 bnxt_free_ring(bp, ring);
1856 }
1857 }
1858
bnxt_alloc_cp_rings(struct bnxt * bp)1859 static int bnxt_alloc_cp_rings(struct bnxt *bp)
1860 {
1861 int i, rc;
1862
1863 for (i = 0; i < bp->cp_nr_rings; i++) {
1864 struct bnxt_napi *bnapi = bp->bnapi[i];
1865 struct bnxt_cp_ring_info *cpr;
1866 struct bnxt_ring_struct *ring;
1867
1868 if (!bnapi)
1869 continue;
1870
1871 cpr = &bnapi->cp_ring;
1872 ring = &cpr->cp_ring_struct;
1873
1874 rc = bnxt_alloc_ring(bp, ring);
1875 if (rc)
1876 return rc;
1877 }
1878 return 0;
1879 }
1880
bnxt_init_ring_struct(struct bnxt * bp)1881 static void bnxt_init_ring_struct(struct bnxt *bp)
1882 {
1883 int i;
1884
1885 for (i = 0; i < bp->cp_nr_rings; i++) {
1886 struct bnxt_napi *bnapi = bp->bnapi[i];
1887 struct bnxt_cp_ring_info *cpr;
1888 struct bnxt_rx_ring_info *rxr;
1889 struct bnxt_tx_ring_info *txr;
1890 struct bnxt_ring_struct *ring;
1891
1892 if (!bnapi)
1893 continue;
1894
1895 cpr = &bnapi->cp_ring;
1896 ring = &cpr->cp_ring_struct;
1897 ring->nr_pages = bp->cp_nr_pages;
1898 ring->page_size = HW_CMPD_RING_SIZE;
1899 ring->pg_arr = (void **)cpr->cp_desc_ring;
1900 ring->dma_arr = cpr->cp_desc_mapping;
1901 ring->vmem_size = 0;
1902
1903 rxr = &bnapi->rx_ring;
1904 ring = &rxr->rx_ring_struct;
1905 ring->nr_pages = bp->rx_nr_pages;
1906 ring->page_size = HW_RXBD_RING_SIZE;
1907 ring->pg_arr = (void **)rxr->rx_desc_ring;
1908 ring->dma_arr = rxr->rx_desc_mapping;
1909 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1910 ring->vmem = (void **)&rxr->rx_buf_ring;
1911
1912 ring = &rxr->rx_agg_ring_struct;
1913 ring->nr_pages = bp->rx_agg_nr_pages;
1914 ring->page_size = HW_RXBD_RING_SIZE;
1915 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1916 ring->dma_arr = rxr->rx_agg_desc_mapping;
1917 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1918 ring->vmem = (void **)&rxr->rx_agg_ring;
1919
1920 txr = &bnapi->tx_ring;
1921 ring = &txr->tx_ring_struct;
1922 ring->nr_pages = bp->tx_nr_pages;
1923 ring->page_size = HW_RXBD_RING_SIZE;
1924 ring->pg_arr = (void **)txr->tx_desc_ring;
1925 ring->dma_arr = txr->tx_desc_mapping;
1926 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1927 ring->vmem = (void **)&txr->tx_buf_ring;
1928 }
1929 }
1930
bnxt_init_rxbd_pages(struct bnxt_ring_struct * ring,u32 type)1931 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1932 {
1933 int i;
1934 u32 prod;
1935 struct rx_bd **rx_buf_ring;
1936
1937 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1938 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1939 int j;
1940 struct rx_bd *rxbd;
1941
1942 rxbd = rx_buf_ring[i];
1943 if (!rxbd)
1944 continue;
1945
1946 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1947 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1948 rxbd->rx_bd_opaque = prod;
1949 }
1950 }
1951 }
1952
bnxt_init_one_rx_ring(struct bnxt * bp,int ring_nr)1953 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1954 {
1955 struct net_device *dev = bp->dev;
1956 struct bnxt_napi *bnapi = bp->bnapi[ring_nr];
1957 struct bnxt_rx_ring_info *rxr;
1958 struct bnxt_ring_struct *ring;
1959 u32 prod, type;
1960 int i;
1961
1962 if (!bnapi)
1963 return -EINVAL;
1964
1965 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1966 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1967
1968 if (NET_IP_ALIGN == 2)
1969 type |= RX_BD_FLAGS_SOP;
1970
1971 rxr = &bnapi->rx_ring;
1972 ring = &rxr->rx_ring_struct;
1973 bnxt_init_rxbd_pages(ring, type);
1974
1975 prod = rxr->rx_prod;
1976 for (i = 0; i < bp->rx_ring_size; i++) {
1977 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1978 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1979 ring_nr, i, bp->rx_ring_size);
1980 break;
1981 }
1982 prod = NEXT_RX(prod);
1983 }
1984 rxr->rx_prod = prod;
1985 ring->fw_ring_id = INVALID_HW_RING_ID;
1986
1987 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1988 return 0;
1989
1990 ring = &rxr->rx_agg_ring_struct;
1991
1992 type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1993 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1994
1995 bnxt_init_rxbd_pages(ring, type);
1996
1997 prod = rxr->rx_agg_prod;
1998 for (i = 0; i < bp->rx_agg_ring_size; i++) {
1999 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2000 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2001 ring_nr, i, bp->rx_ring_size);
2002 break;
2003 }
2004 prod = NEXT_RX_AGG(prod);
2005 }
2006 rxr->rx_agg_prod = prod;
2007 ring->fw_ring_id = INVALID_HW_RING_ID;
2008
2009 if (bp->flags & BNXT_FLAG_TPA) {
2010 if (rxr->rx_tpa) {
2011 u8 *data;
2012 dma_addr_t mapping;
2013
2014 for (i = 0; i < MAX_TPA; i++) {
2015 data = __bnxt_alloc_rx_data(bp, &mapping,
2016 GFP_KERNEL);
2017 if (!data)
2018 return -ENOMEM;
2019
2020 rxr->rx_tpa[i].data = data;
2021 rxr->rx_tpa[i].mapping = mapping;
2022 }
2023 } else {
2024 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2025 return -ENOMEM;
2026 }
2027 }
2028
2029 return 0;
2030 }
2031
bnxt_init_cp_rings(struct bnxt * bp)2032 static void bnxt_init_cp_rings(struct bnxt *bp)
2033 {
2034 int i;
2035
2036 for (i = 0; i < bp->cp_nr_rings; i++) {
2037 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2038 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2039
2040 ring->fw_ring_id = INVALID_HW_RING_ID;
2041 }
2042 }
2043
bnxt_init_rx_rings(struct bnxt * bp)2044 static int bnxt_init_rx_rings(struct bnxt *bp)
2045 {
2046 int i, rc = 0;
2047
2048 for (i = 0; i < bp->rx_nr_rings; i++) {
2049 rc = bnxt_init_one_rx_ring(bp, i);
2050 if (rc)
2051 break;
2052 }
2053
2054 return rc;
2055 }
2056
bnxt_init_tx_rings(struct bnxt * bp)2057 static int bnxt_init_tx_rings(struct bnxt *bp)
2058 {
2059 u16 i;
2060
2061 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2062 MAX_SKB_FRAGS + 1);
2063
2064 for (i = 0; i < bp->tx_nr_rings; i++) {
2065 struct bnxt_napi *bnapi = bp->bnapi[i];
2066 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
2067 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2068
2069 ring->fw_ring_id = INVALID_HW_RING_ID;
2070 }
2071
2072 return 0;
2073 }
2074
bnxt_free_ring_grps(struct bnxt * bp)2075 static void bnxt_free_ring_grps(struct bnxt *bp)
2076 {
2077 kfree(bp->grp_info);
2078 bp->grp_info = NULL;
2079 }
2080
bnxt_init_ring_grps(struct bnxt * bp,bool irq_re_init)2081 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2082 {
2083 int i;
2084
2085 if (irq_re_init) {
2086 bp->grp_info = kcalloc(bp->cp_nr_rings,
2087 sizeof(struct bnxt_ring_grp_info),
2088 GFP_KERNEL);
2089 if (!bp->grp_info)
2090 return -ENOMEM;
2091 }
2092 for (i = 0; i < bp->cp_nr_rings; i++) {
2093 if (irq_re_init)
2094 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2095 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2096 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2097 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2098 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2099 }
2100 return 0;
2101 }
2102
bnxt_free_vnics(struct bnxt * bp)2103 static void bnxt_free_vnics(struct bnxt *bp)
2104 {
2105 kfree(bp->vnic_info);
2106 bp->vnic_info = NULL;
2107 bp->nr_vnics = 0;
2108 }
2109
bnxt_alloc_vnics(struct bnxt * bp)2110 static int bnxt_alloc_vnics(struct bnxt *bp)
2111 {
2112 int num_vnics = 1;
2113
2114 #ifdef CONFIG_RFS_ACCEL
2115 if (bp->flags & BNXT_FLAG_RFS)
2116 num_vnics += bp->rx_nr_rings;
2117 #endif
2118
2119 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2120 GFP_KERNEL);
2121 if (!bp->vnic_info)
2122 return -ENOMEM;
2123
2124 bp->nr_vnics = num_vnics;
2125 return 0;
2126 }
2127
bnxt_init_vnics(struct bnxt * bp)2128 static void bnxt_init_vnics(struct bnxt *bp)
2129 {
2130 int i;
2131
2132 for (i = 0; i < bp->nr_vnics; i++) {
2133 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2134
2135 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2136 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2137 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2138
2139 if (bp->vnic_info[i].rss_hash_key) {
2140 if (i == 0)
2141 prandom_bytes(vnic->rss_hash_key,
2142 HW_HASH_KEY_SIZE);
2143 else
2144 memcpy(vnic->rss_hash_key,
2145 bp->vnic_info[0].rss_hash_key,
2146 HW_HASH_KEY_SIZE);
2147 }
2148 }
2149 }
2150
bnxt_calc_nr_ring_pages(u32 ring_size,int desc_per_pg)2151 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2152 {
2153 int pages;
2154
2155 pages = ring_size / desc_per_pg;
2156
2157 if (!pages)
2158 return 1;
2159
2160 pages++;
2161
2162 while (pages & (pages - 1))
2163 pages++;
2164
2165 return pages;
2166 }
2167
bnxt_set_tpa_flags(struct bnxt * bp)2168 static void bnxt_set_tpa_flags(struct bnxt *bp)
2169 {
2170 bp->flags &= ~BNXT_FLAG_TPA;
2171 if (bp->dev->features & NETIF_F_LRO)
2172 bp->flags |= BNXT_FLAG_LRO;
2173 if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2174 bp->flags |= BNXT_FLAG_GRO;
2175 }
2176
2177 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2178 * be set on entry.
2179 */
bnxt_set_ring_params(struct bnxt * bp)2180 void bnxt_set_ring_params(struct bnxt *bp)
2181 {
2182 u32 ring_size, rx_size, rx_space;
2183 u32 agg_factor = 0, agg_ring_size = 0;
2184
2185 /* 8 for CRC and VLAN */
2186 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2187
2188 rx_space = rx_size + NET_SKB_PAD +
2189 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2190
2191 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2192 ring_size = bp->rx_ring_size;
2193 bp->rx_agg_ring_size = 0;
2194 bp->rx_agg_nr_pages = 0;
2195
2196 if (bp->flags & BNXT_FLAG_TPA)
2197 agg_factor = 4;
2198
2199 bp->flags &= ~BNXT_FLAG_JUMBO;
2200 if (rx_space > PAGE_SIZE) {
2201 u32 jumbo_factor;
2202
2203 bp->flags |= BNXT_FLAG_JUMBO;
2204 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2205 if (jumbo_factor > agg_factor)
2206 agg_factor = jumbo_factor;
2207 }
2208 agg_ring_size = ring_size * agg_factor;
2209
2210 if (agg_ring_size) {
2211 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2212 RX_DESC_CNT);
2213 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2214 u32 tmp = agg_ring_size;
2215
2216 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2217 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2218 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2219 tmp, agg_ring_size);
2220 }
2221 bp->rx_agg_ring_size = agg_ring_size;
2222 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2223 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2224 rx_space = rx_size + NET_SKB_PAD +
2225 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2226 }
2227
2228 bp->rx_buf_use_size = rx_size;
2229 bp->rx_buf_size = rx_space;
2230
2231 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2232 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2233
2234 ring_size = bp->tx_ring_size;
2235 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2236 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2237
2238 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2239 bp->cp_ring_size = ring_size;
2240
2241 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2242 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2243 bp->cp_nr_pages = MAX_CP_PAGES;
2244 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2245 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2246 ring_size, bp->cp_ring_size);
2247 }
2248 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2249 bp->cp_ring_mask = bp->cp_bit - 1;
2250 }
2251
bnxt_free_vnic_attributes(struct bnxt * bp)2252 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2253 {
2254 int i;
2255 struct bnxt_vnic_info *vnic;
2256 struct pci_dev *pdev = bp->pdev;
2257
2258 if (!bp->vnic_info)
2259 return;
2260
2261 for (i = 0; i < bp->nr_vnics; i++) {
2262 vnic = &bp->vnic_info[i];
2263
2264 kfree(vnic->fw_grp_ids);
2265 vnic->fw_grp_ids = NULL;
2266
2267 kfree(vnic->uc_list);
2268 vnic->uc_list = NULL;
2269
2270 if (vnic->mc_list) {
2271 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2272 vnic->mc_list, vnic->mc_list_mapping);
2273 vnic->mc_list = NULL;
2274 }
2275
2276 if (vnic->rss_table) {
2277 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2278 vnic->rss_table,
2279 vnic->rss_table_dma_addr);
2280 vnic->rss_table = NULL;
2281 }
2282
2283 vnic->rss_hash_key = NULL;
2284 vnic->flags = 0;
2285 }
2286 }
2287
bnxt_alloc_vnic_attributes(struct bnxt * bp)2288 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2289 {
2290 int i, rc = 0, size;
2291 struct bnxt_vnic_info *vnic;
2292 struct pci_dev *pdev = bp->pdev;
2293 int max_rings;
2294
2295 for (i = 0; i < bp->nr_vnics; i++) {
2296 vnic = &bp->vnic_info[i];
2297
2298 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2299 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2300
2301 if (mem_size > 0) {
2302 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2303 if (!vnic->uc_list) {
2304 rc = -ENOMEM;
2305 goto out;
2306 }
2307 }
2308 }
2309
2310 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2311 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2312 vnic->mc_list =
2313 dma_alloc_coherent(&pdev->dev,
2314 vnic->mc_list_size,
2315 &vnic->mc_list_mapping,
2316 GFP_KERNEL);
2317 if (!vnic->mc_list) {
2318 rc = -ENOMEM;
2319 goto out;
2320 }
2321 }
2322
2323 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2324 max_rings = bp->rx_nr_rings;
2325 else
2326 max_rings = 1;
2327
2328 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2329 if (!vnic->fw_grp_ids) {
2330 rc = -ENOMEM;
2331 goto out;
2332 }
2333
2334 /* Allocate rss table and hash key */
2335 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2336 &vnic->rss_table_dma_addr,
2337 GFP_KERNEL);
2338 if (!vnic->rss_table) {
2339 rc = -ENOMEM;
2340 goto out;
2341 }
2342
2343 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2344
2345 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2346 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2347 }
2348 return 0;
2349
2350 out:
2351 return rc;
2352 }
2353
bnxt_free_hwrm_resources(struct bnxt * bp)2354 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2355 {
2356 struct pci_dev *pdev = bp->pdev;
2357
2358 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2359 bp->hwrm_cmd_resp_dma_addr);
2360
2361 bp->hwrm_cmd_resp_addr = NULL;
2362 if (bp->hwrm_dbg_resp_addr) {
2363 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2364 bp->hwrm_dbg_resp_addr,
2365 bp->hwrm_dbg_resp_dma_addr);
2366
2367 bp->hwrm_dbg_resp_addr = NULL;
2368 }
2369 }
2370
bnxt_alloc_hwrm_resources(struct bnxt * bp)2371 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2372 {
2373 struct pci_dev *pdev = bp->pdev;
2374
2375 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2376 &bp->hwrm_cmd_resp_dma_addr,
2377 GFP_KERNEL);
2378 if (!bp->hwrm_cmd_resp_addr)
2379 return -ENOMEM;
2380 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2381 HWRM_DBG_REG_BUF_SIZE,
2382 &bp->hwrm_dbg_resp_dma_addr,
2383 GFP_KERNEL);
2384 if (!bp->hwrm_dbg_resp_addr)
2385 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2386
2387 return 0;
2388 }
2389
bnxt_free_stats(struct bnxt * bp)2390 static void bnxt_free_stats(struct bnxt *bp)
2391 {
2392 u32 size, i;
2393 struct pci_dev *pdev = bp->pdev;
2394
2395 if (!bp->bnapi)
2396 return;
2397
2398 size = sizeof(struct ctx_hw_stats);
2399
2400 for (i = 0; i < bp->cp_nr_rings; i++) {
2401 struct bnxt_napi *bnapi = bp->bnapi[i];
2402 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2403
2404 if (cpr->hw_stats) {
2405 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2406 cpr->hw_stats_map);
2407 cpr->hw_stats = NULL;
2408 }
2409 }
2410 }
2411
bnxt_alloc_stats(struct bnxt * bp)2412 static int bnxt_alloc_stats(struct bnxt *bp)
2413 {
2414 u32 size, i;
2415 struct pci_dev *pdev = bp->pdev;
2416
2417 size = sizeof(struct ctx_hw_stats);
2418
2419 for (i = 0; i < bp->cp_nr_rings; i++) {
2420 struct bnxt_napi *bnapi = bp->bnapi[i];
2421 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2422
2423 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2424 &cpr->hw_stats_map,
2425 GFP_KERNEL);
2426 if (!cpr->hw_stats)
2427 return -ENOMEM;
2428
2429 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2430 }
2431 return 0;
2432 }
2433
bnxt_clear_ring_indices(struct bnxt * bp)2434 static void bnxt_clear_ring_indices(struct bnxt *bp)
2435 {
2436 int i;
2437
2438 if (!bp->bnapi)
2439 return;
2440
2441 for (i = 0; i < bp->cp_nr_rings; i++) {
2442 struct bnxt_napi *bnapi = bp->bnapi[i];
2443 struct bnxt_cp_ring_info *cpr;
2444 struct bnxt_rx_ring_info *rxr;
2445 struct bnxt_tx_ring_info *txr;
2446
2447 if (!bnapi)
2448 continue;
2449
2450 cpr = &bnapi->cp_ring;
2451 cpr->cp_raw_cons = 0;
2452
2453 txr = &bnapi->tx_ring;
2454 txr->tx_prod = 0;
2455 txr->tx_cons = 0;
2456
2457 rxr = &bnapi->rx_ring;
2458 rxr->rx_prod = 0;
2459 rxr->rx_agg_prod = 0;
2460 rxr->rx_sw_agg_prod = 0;
2461 }
2462 }
2463
bnxt_free_ntp_fltrs(struct bnxt * bp,bool irq_reinit)2464 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2465 {
2466 #ifdef CONFIG_RFS_ACCEL
2467 int i;
2468
2469 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2470 * safe to delete the hash table.
2471 */
2472 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2473 struct hlist_head *head;
2474 struct hlist_node *tmp;
2475 struct bnxt_ntuple_filter *fltr;
2476
2477 head = &bp->ntp_fltr_hash_tbl[i];
2478 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2479 hlist_del(&fltr->hash);
2480 kfree(fltr);
2481 }
2482 }
2483 if (irq_reinit) {
2484 kfree(bp->ntp_fltr_bmap);
2485 bp->ntp_fltr_bmap = NULL;
2486 }
2487 bp->ntp_fltr_count = 0;
2488 #endif
2489 }
2490
bnxt_alloc_ntp_fltrs(struct bnxt * bp)2491 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2492 {
2493 #ifdef CONFIG_RFS_ACCEL
2494 int i, rc = 0;
2495
2496 if (!(bp->flags & BNXT_FLAG_RFS))
2497 return 0;
2498
2499 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2500 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2501
2502 bp->ntp_fltr_count = 0;
2503 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2504 sizeof(long),
2505 GFP_KERNEL);
2506
2507 if (!bp->ntp_fltr_bmap)
2508 rc = -ENOMEM;
2509
2510 return rc;
2511 #else
2512 return 0;
2513 #endif
2514 }
2515
bnxt_free_mem(struct bnxt * bp,bool irq_re_init)2516 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2517 {
2518 bnxt_free_vnic_attributes(bp);
2519 bnxt_free_tx_rings(bp);
2520 bnxt_free_rx_rings(bp);
2521 bnxt_free_cp_rings(bp);
2522 bnxt_free_ntp_fltrs(bp, irq_re_init);
2523 if (irq_re_init) {
2524 bnxt_free_stats(bp);
2525 bnxt_free_ring_grps(bp);
2526 bnxt_free_vnics(bp);
2527 kfree(bp->bnapi);
2528 bp->bnapi = NULL;
2529 } else {
2530 bnxt_clear_ring_indices(bp);
2531 }
2532 }
2533
bnxt_alloc_mem(struct bnxt * bp,bool irq_re_init)2534 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2535 {
2536 int i, rc, size, arr_size;
2537 void *bnapi;
2538
2539 if (irq_re_init) {
2540 /* Allocate bnapi mem pointer array and mem block for
2541 * all queues
2542 */
2543 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2544 bp->cp_nr_rings);
2545 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2546 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2547 if (!bnapi)
2548 return -ENOMEM;
2549
2550 bp->bnapi = bnapi;
2551 bnapi += arr_size;
2552 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2553 bp->bnapi[i] = bnapi;
2554 bp->bnapi[i]->index = i;
2555 bp->bnapi[i]->bp = bp;
2556 }
2557
2558 rc = bnxt_alloc_stats(bp);
2559 if (rc)
2560 goto alloc_mem_err;
2561
2562 rc = bnxt_alloc_ntp_fltrs(bp);
2563 if (rc)
2564 goto alloc_mem_err;
2565
2566 rc = bnxt_alloc_vnics(bp);
2567 if (rc)
2568 goto alloc_mem_err;
2569 }
2570
2571 bnxt_init_ring_struct(bp);
2572
2573 rc = bnxt_alloc_rx_rings(bp);
2574 if (rc)
2575 goto alloc_mem_err;
2576
2577 rc = bnxt_alloc_tx_rings(bp);
2578 if (rc)
2579 goto alloc_mem_err;
2580
2581 rc = bnxt_alloc_cp_rings(bp);
2582 if (rc)
2583 goto alloc_mem_err;
2584
2585 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2586 BNXT_VNIC_UCAST_FLAG;
2587 rc = bnxt_alloc_vnic_attributes(bp);
2588 if (rc)
2589 goto alloc_mem_err;
2590 return 0;
2591
2592 alloc_mem_err:
2593 bnxt_free_mem(bp, true);
2594 return rc;
2595 }
2596
bnxt_hwrm_cmd_hdr_init(struct bnxt * bp,void * request,u16 req_type,u16 cmpl_ring,u16 target_id)2597 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2598 u16 cmpl_ring, u16 target_id)
2599 {
2600 struct hwrm_cmd_req_hdr *req = request;
2601
2602 req->cmpl_ring_req_type =
2603 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT));
2604 req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT);
2605 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2606 }
2607
_hwrm_send_message(struct bnxt * bp,void * msg,u32 msg_len,int timeout)2608 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2609 {
2610 int i, intr_process, rc;
2611 struct hwrm_cmd_req_hdr *req = msg;
2612 u32 *data = msg;
2613 __le32 *resp_len, *valid;
2614 u16 cp_ring_id, len = 0;
2615 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2616
2617 req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++);
2618 memset(resp, 0, PAGE_SIZE);
2619 cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) &
2620 HWRM_CMPL_RING_MASK) >>
2621 HWRM_CMPL_RING_SFT;
2622 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2623
2624 /* Write request msg to hwrm channel */
2625 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2626
2627 /* currently supports only one outstanding message */
2628 if (intr_process)
2629 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) &
2630 HWRM_SEQ_ID_MASK;
2631
2632 /* Ring channel doorbell */
2633 writel(1, bp->bar0 + 0x100);
2634
2635 i = 0;
2636 if (intr_process) {
2637 /* Wait until hwrm response cmpl interrupt is processed */
2638 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2639 i++ < timeout) {
2640 usleep_range(600, 800);
2641 }
2642
2643 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2644 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2645 req->cmpl_ring_req_type);
2646 return -1;
2647 }
2648 } else {
2649 /* Check if response len is updated */
2650 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2651 for (i = 0; i < timeout; i++) {
2652 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2653 HWRM_RESP_LEN_SFT;
2654 if (len)
2655 break;
2656 usleep_range(600, 800);
2657 }
2658
2659 if (i >= timeout) {
2660 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2661 timeout, req->cmpl_ring_req_type,
2662 req->target_id_seq_id, *resp_len);
2663 return -1;
2664 }
2665
2666 /* Last word of resp contains valid bit */
2667 valid = bp->hwrm_cmd_resp_addr + len - 4;
2668 for (i = 0; i < timeout; i++) {
2669 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2670 break;
2671 usleep_range(600, 800);
2672 }
2673
2674 if (i >= timeout) {
2675 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2676 timeout, req->cmpl_ring_req_type,
2677 req->target_id_seq_id, len, *valid);
2678 return -1;
2679 }
2680 }
2681
2682 rc = le16_to_cpu(resp->error_code);
2683 if (rc) {
2684 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2685 le16_to_cpu(resp->req_type),
2686 le16_to_cpu(resp->seq_id), rc);
2687 return rc;
2688 }
2689 return 0;
2690 }
2691
hwrm_send_message(struct bnxt * bp,void * msg,u32 msg_len,int timeout)2692 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2693 {
2694 int rc;
2695
2696 mutex_lock(&bp->hwrm_cmd_lock);
2697 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2698 mutex_unlock(&bp->hwrm_cmd_lock);
2699 return rc;
2700 }
2701
bnxt_hwrm_func_drv_rgtr(struct bnxt * bp)2702 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2703 {
2704 struct hwrm_func_drv_rgtr_input req = {0};
2705 int i;
2706
2707 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2708
2709 req.enables =
2710 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2711 FUNC_DRV_RGTR_REQ_ENABLES_VER |
2712 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2713
2714 /* TODO: current async event fwd bits are not defined and the firmware
2715 * only checks if it is non-zero to enable async event forwarding
2716 */
2717 req.async_event_fwd[0] |= cpu_to_le32(1);
2718 req.os_type = cpu_to_le16(1);
2719 req.ver_maj = DRV_VER_MAJ;
2720 req.ver_min = DRV_VER_MIN;
2721 req.ver_upd = DRV_VER_UPD;
2722
2723 if (BNXT_PF(bp)) {
2724 DECLARE_BITMAP(vf_req_snif_bmap, 256);
2725 u32 *data = (u32 *)vf_req_snif_bmap;
2726
2727 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
2728 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2729 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2730
2731 for (i = 0; i < 8; i++)
2732 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2733
2734 req.enables |=
2735 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2736 }
2737
2738 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2739 }
2740
bnxt_hwrm_tunnel_dst_port_free(struct bnxt * bp,u8 tunnel_type)2741 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2742 {
2743 u32 rc = 0;
2744 struct hwrm_tunnel_dst_port_free_input req = {0};
2745
2746 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2747 req.tunnel_type = tunnel_type;
2748
2749 switch (tunnel_type) {
2750 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2751 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2752 break;
2753 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2754 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2755 break;
2756 default:
2757 break;
2758 }
2759
2760 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2761 if (rc)
2762 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2763 rc);
2764 return rc;
2765 }
2766
bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt * bp,__be16 port,u8 tunnel_type)2767 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2768 u8 tunnel_type)
2769 {
2770 u32 rc = 0;
2771 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2772 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2773
2774 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2775
2776 req.tunnel_type = tunnel_type;
2777 req.tunnel_dst_port_val = port;
2778
2779 mutex_lock(&bp->hwrm_cmd_lock);
2780 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2781 if (rc) {
2782 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2783 rc);
2784 goto err_out;
2785 }
2786
2787 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2788 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2789
2790 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2791 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2792 err_out:
2793 mutex_unlock(&bp->hwrm_cmd_lock);
2794 return rc;
2795 }
2796
bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt * bp,u16 vnic_id)2797 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2798 {
2799 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2800 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2801
2802 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2803 req.dflt_vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2804
2805 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2806 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2807 req.mask = cpu_to_le32(vnic->rx_mask);
2808 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2809 }
2810
2811 #ifdef CONFIG_RFS_ACCEL
bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt * bp,struct bnxt_ntuple_filter * fltr)2812 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2813 struct bnxt_ntuple_filter *fltr)
2814 {
2815 struct hwrm_cfa_ntuple_filter_free_input req = {0};
2816
2817 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2818 req.ntuple_filter_id = fltr->filter_id;
2819 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2820 }
2821
2822 #define BNXT_NTP_FLTR_FLAGS \
2823 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2824 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2825 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2826 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2827 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2828 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2829 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2830 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2831 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2832 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2833 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2834 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2835 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2836 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID)
2837
bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt * bp,struct bnxt_ntuple_filter * fltr)2838 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2839 struct bnxt_ntuple_filter *fltr)
2840 {
2841 int rc = 0;
2842 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2843 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2844 bp->hwrm_cmd_resp_addr;
2845 struct flow_keys *keys = &fltr->fkeys;
2846 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2847
2848 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2849 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2850
2851 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2852
2853 req.ethertype = htons(ETH_P_IP);
2854 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2855 req.ipaddr_type = 4;
2856 req.ip_protocol = keys->basic.ip_proto;
2857
2858 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2859 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2860 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2861 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2862
2863 req.src_port = keys->ports.src;
2864 req.src_port_mask = cpu_to_be16(0xffff);
2865 req.dst_port = keys->ports.dst;
2866 req.dst_port_mask = cpu_to_be16(0xffff);
2867
2868 req.dst_vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2869 mutex_lock(&bp->hwrm_cmd_lock);
2870 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2871 if (!rc)
2872 fltr->filter_id = resp->ntuple_filter_id;
2873 mutex_unlock(&bp->hwrm_cmd_lock);
2874 return rc;
2875 }
2876 #endif
2877
bnxt_hwrm_set_vnic_filter(struct bnxt * bp,u16 vnic_id,u16 idx,u8 * mac_addr)2878 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2879 u8 *mac_addr)
2880 {
2881 u32 rc = 0;
2882 struct hwrm_cfa_l2_filter_alloc_input req = {0};
2883 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2884
2885 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2886 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2887 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
2888 req.dst_vnic_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
2889 req.enables =
2890 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
2891 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID |
2892 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2893 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2894 req.l2_addr_mask[0] = 0xff;
2895 req.l2_addr_mask[1] = 0xff;
2896 req.l2_addr_mask[2] = 0xff;
2897 req.l2_addr_mask[3] = 0xff;
2898 req.l2_addr_mask[4] = 0xff;
2899 req.l2_addr_mask[5] = 0xff;
2900
2901 mutex_lock(&bp->hwrm_cmd_lock);
2902 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2903 if (!rc)
2904 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2905 resp->l2_filter_id;
2906 mutex_unlock(&bp->hwrm_cmd_lock);
2907 return rc;
2908 }
2909
bnxt_hwrm_clear_vnic_filter(struct bnxt * bp)2910 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2911 {
2912 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2913 int rc = 0;
2914
2915 /* Any associated ntuple filters will also be cleared by firmware. */
2916 mutex_lock(&bp->hwrm_cmd_lock);
2917 for (i = 0; i < num_of_vnics; i++) {
2918 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2919
2920 for (j = 0; j < vnic->uc_filter_count; j++) {
2921 struct hwrm_cfa_l2_filter_free_input req = {0};
2922
2923 bnxt_hwrm_cmd_hdr_init(bp, &req,
2924 HWRM_CFA_L2_FILTER_FREE, -1, -1);
2925
2926 req.l2_filter_id = vnic->fw_l2_filter_id[j];
2927
2928 rc = _hwrm_send_message(bp, &req, sizeof(req),
2929 HWRM_CMD_TIMEOUT);
2930 }
2931 vnic->uc_filter_count = 0;
2932 }
2933 mutex_unlock(&bp->hwrm_cmd_lock);
2934
2935 return rc;
2936 }
2937
bnxt_hwrm_vnic_set_tpa(struct bnxt * bp,u16 vnic_id,u32 tpa_flags)2938 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2939 {
2940 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2941 struct hwrm_vnic_tpa_cfg_input req = {0};
2942
2943 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2944 return 0;
2945
2946 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2947
2948 if (tpa_flags) {
2949 u16 mss = bp->dev->mtu - 40;
2950 u32 nsegs, n, segs = 0, flags;
2951
2952 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2953 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2954 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2955 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2956 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2957 if (tpa_flags & BNXT_FLAG_GRO)
2958 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2959
2960 req.flags = cpu_to_le32(flags);
2961
2962 req.enables =
2963 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
2964 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS);
2965
2966 /* Number of segs are log2 units, and first packet is not
2967 * included as part of this units.
2968 */
2969 if (mss <= PAGE_SIZE) {
2970 n = PAGE_SIZE / mss;
2971 nsegs = (MAX_SKB_FRAGS - 1) * n;
2972 } else {
2973 n = mss / PAGE_SIZE;
2974 if (mss & (PAGE_SIZE - 1))
2975 n++;
2976 nsegs = (MAX_SKB_FRAGS - n) / n;
2977 }
2978
2979 segs = ilog2(nsegs);
2980 req.max_agg_segs = cpu_to_le16(segs);
2981 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
2982 }
2983 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2984
2985 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2986 }
2987
bnxt_hwrm_vnic_set_rss(struct bnxt * bp,u16 vnic_id,bool set_rss)2988 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
2989 {
2990 u32 i, j, max_rings;
2991 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2992 struct hwrm_vnic_rss_cfg_input req = {0};
2993
2994 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
2995 return 0;
2996
2997 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
2998 if (set_rss) {
2999 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3000 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3001 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3002 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3003
3004 req.hash_type = cpu_to_le32(vnic->hash_type);
3005
3006 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3007 max_rings = bp->rx_nr_rings;
3008 else
3009 max_rings = 1;
3010
3011 /* Fill the RSS indirection table with ring group ids */
3012 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3013 if (j == max_rings)
3014 j = 0;
3015 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3016 }
3017
3018 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3019 req.hash_key_tbl_addr =
3020 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3021 }
3022 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3023 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3024 }
3025
bnxt_hwrm_vnic_set_hds(struct bnxt * bp,u16 vnic_id)3026 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3027 {
3028 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3029 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3030
3031 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3032 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3033 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3034 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3035 req.enables =
3036 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3037 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3038 /* thresholds not implemented in firmware yet */
3039 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3040 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3041 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3042 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3043 }
3044
bnxt_hwrm_vnic_ctx_free_one(struct bnxt * bp,u16 vnic_id)3045 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3046 {
3047 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3048
3049 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3050 req.rss_cos_lb_ctx_id =
3051 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3052
3053 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3054 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3055 }
3056
bnxt_hwrm_vnic_ctx_free(struct bnxt * bp)3057 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3058 {
3059 int i;
3060
3061 for (i = 0; i < bp->nr_vnics; i++) {
3062 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3063
3064 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3065 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3066 }
3067 bp->rsscos_nr_ctxs = 0;
3068 }
3069
bnxt_hwrm_vnic_ctx_alloc(struct bnxt * bp,u16 vnic_id)3070 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3071 {
3072 int rc;
3073 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3074 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3075 bp->hwrm_cmd_resp_addr;
3076
3077 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3078 -1);
3079
3080 mutex_lock(&bp->hwrm_cmd_lock);
3081 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3082 if (!rc)
3083 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3084 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3085 mutex_unlock(&bp->hwrm_cmd_lock);
3086
3087 return rc;
3088 }
3089
bnxt_hwrm_vnic_cfg(struct bnxt * bp,u16 vnic_id)3090 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3091 {
3092 int grp_idx = 0;
3093 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3094 struct hwrm_vnic_cfg_input req = {0};
3095
3096 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3097 /* Only RSS support for now TBD: COS & LB */
3098 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3099 VNIC_CFG_REQ_ENABLES_RSS_RULE);
3100 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3101 req.cos_rule = cpu_to_le16(0xffff);
3102 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3103 grp_idx = 0;
3104 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3105 grp_idx = vnic_id - 1;
3106
3107 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3108 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3109
3110 req.lb_rule = cpu_to_le16(0xffff);
3111 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3112 VLAN_HLEN);
3113
3114 if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3115 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3116
3117 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3118 }
3119
bnxt_hwrm_vnic_free_one(struct bnxt * bp,u16 vnic_id)3120 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3121 {
3122 u32 rc = 0;
3123
3124 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3125 struct hwrm_vnic_free_input req = {0};
3126
3127 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3128 req.vnic_id =
3129 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3130
3131 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3132 if (rc)
3133 return rc;
3134 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3135 }
3136 return rc;
3137 }
3138
bnxt_hwrm_vnic_free(struct bnxt * bp)3139 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3140 {
3141 u16 i;
3142
3143 for (i = 0; i < bp->nr_vnics; i++)
3144 bnxt_hwrm_vnic_free_one(bp, i);
3145 }
3146
bnxt_hwrm_vnic_alloc(struct bnxt * bp,u16 vnic_id,u16 start_grp_id,u16 end_grp_id)3147 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, u16 start_grp_id,
3148 u16 end_grp_id)
3149 {
3150 u32 rc = 0, i, j;
3151 struct hwrm_vnic_alloc_input req = {0};
3152 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3153
3154 /* map ring groups to this vnic */
3155 for (i = start_grp_id, j = 0; i < end_grp_id; i++, j++) {
3156 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) {
3157 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3158 j, (end_grp_id - start_grp_id));
3159 break;
3160 }
3161 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3162 bp->grp_info[i].fw_grp_id;
3163 }
3164
3165 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3166 if (vnic_id == 0)
3167 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3168
3169 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3170
3171 mutex_lock(&bp->hwrm_cmd_lock);
3172 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3173 if (!rc)
3174 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3175 mutex_unlock(&bp->hwrm_cmd_lock);
3176 return rc;
3177 }
3178
bnxt_hwrm_ring_grp_alloc(struct bnxt * bp)3179 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3180 {
3181 u16 i;
3182 u32 rc = 0;
3183
3184 mutex_lock(&bp->hwrm_cmd_lock);
3185 for (i = 0; i < bp->rx_nr_rings; i++) {
3186 struct hwrm_ring_grp_alloc_input req = {0};
3187 struct hwrm_ring_grp_alloc_output *resp =
3188 bp->hwrm_cmd_resp_addr;
3189
3190 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3191
3192 req.cr = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3193 req.rr = cpu_to_le16(bp->grp_info[i].rx_fw_ring_id);
3194 req.ar = cpu_to_le16(bp->grp_info[i].agg_fw_ring_id);
3195 req.sc = cpu_to_le16(bp->grp_info[i].fw_stats_ctx);
3196
3197 rc = _hwrm_send_message(bp, &req, sizeof(req),
3198 HWRM_CMD_TIMEOUT);
3199 if (rc)
3200 break;
3201
3202 bp->grp_info[i].fw_grp_id = le32_to_cpu(resp->ring_group_id);
3203 }
3204 mutex_unlock(&bp->hwrm_cmd_lock);
3205 return rc;
3206 }
3207
bnxt_hwrm_ring_grp_free(struct bnxt * bp)3208 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3209 {
3210 u16 i;
3211 u32 rc = 0;
3212 struct hwrm_ring_grp_free_input req = {0};
3213
3214 if (!bp->grp_info)
3215 return 0;
3216
3217 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3218
3219 mutex_lock(&bp->hwrm_cmd_lock);
3220 for (i = 0; i < bp->cp_nr_rings; i++) {
3221 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3222 continue;
3223 req.ring_group_id =
3224 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3225
3226 rc = _hwrm_send_message(bp, &req, sizeof(req),
3227 HWRM_CMD_TIMEOUT);
3228 if (rc)
3229 break;
3230 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3231 }
3232 mutex_unlock(&bp->hwrm_cmd_lock);
3233 return rc;
3234 }
3235
hwrm_ring_alloc_send_msg(struct bnxt * bp,struct bnxt_ring_struct * ring,u32 ring_type,u32 map_index,u32 stats_ctx_id)3236 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3237 struct bnxt_ring_struct *ring,
3238 u32 ring_type, u32 map_index,
3239 u32 stats_ctx_id)
3240 {
3241 int rc = 0, err = 0;
3242 struct hwrm_ring_alloc_input req = {0};
3243 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3244 u16 ring_id;
3245
3246 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3247
3248 req.enables = 0;
3249 if (ring->nr_pages > 1) {
3250 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3251 /* Page size is in log2 units */
3252 req.page_size = BNXT_PAGE_SHIFT;
3253 req.page_tbl_depth = 1;
3254 } else {
3255 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3256 }
3257 req.fbo = 0;
3258 /* Association of ring index with doorbell index and MSIX number */
3259 req.logical_id = cpu_to_le16(map_index);
3260
3261 switch (ring_type) {
3262 case HWRM_RING_ALLOC_TX:
3263 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3264 /* Association of transmit ring with completion ring */
3265 req.cmpl_ring_id =
3266 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3267 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3268 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3269 req.queue_id = cpu_to_le16(ring->queue_id);
3270 break;
3271 case HWRM_RING_ALLOC_RX:
3272 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3273 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3274 break;
3275 case HWRM_RING_ALLOC_AGG:
3276 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3277 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3278 break;
3279 case HWRM_RING_ALLOC_CMPL:
3280 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3281 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3282 if (bp->flags & BNXT_FLAG_USING_MSIX)
3283 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3284 break;
3285 default:
3286 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3287 ring_type);
3288 return -1;
3289 }
3290
3291 mutex_lock(&bp->hwrm_cmd_lock);
3292 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3293 err = le16_to_cpu(resp->error_code);
3294 ring_id = le16_to_cpu(resp->ring_id);
3295 mutex_unlock(&bp->hwrm_cmd_lock);
3296
3297 if (rc || err) {
3298 switch (ring_type) {
3299 case RING_FREE_REQ_RING_TYPE_CMPL:
3300 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3301 rc, err);
3302 return -1;
3303
3304 case RING_FREE_REQ_RING_TYPE_RX:
3305 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3306 rc, err);
3307 return -1;
3308
3309 case RING_FREE_REQ_RING_TYPE_TX:
3310 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3311 rc, err);
3312 return -1;
3313
3314 default:
3315 netdev_err(bp->dev, "Invalid ring\n");
3316 return -1;
3317 }
3318 }
3319 ring->fw_ring_id = ring_id;
3320 return rc;
3321 }
3322
bnxt_hwrm_ring_alloc(struct bnxt * bp)3323 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3324 {
3325 int i, rc = 0;
3326
3327 if (bp->cp_nr_rings) {
3328 for (i = 0; i < bp->cp_nr_rings; i++) {
3329 struct bnxt_napi *bnapi = bp->bnapi[i];
3330 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3331 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3332
3333 rc = hwrm_ring_alloc_send_msg(bp, ring,
3334 HWRM_RING_ALLOC_CMPL, i,
3335 INVALID_STATS_CTX_ID);
3336 if (rc)
3337 goto err_out;
3338 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3339 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3340 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3341 }
3342 }
3343
3344 if (bp->tx_nr_rings) {
3345 for (i = 0; i < bp->tx_nr_rings; i++) {
3346 struct bnxt_napi *bnapi = bp->bnapi[i];
3347 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
3348 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3349 u16 fw_stats_ctx = bp->grp_info[i].fw_stats_ctx;
3350
3351 rc = hwrm_ring_alloc_send_msg(bp, ring,
3352 HWRM_RING_ALLOC_TX, i,
3353 fw_stats_ctx);
3354 if (rc)
3355 goto err_out;
3356 txr->tx_doorbell = bp->bar1 + i * 0x80;
3357 }
3358 }
3359
3360 if (bp->rx_nr_rings) {
3361 for (i = 0; i < bp->rx_nr_rings; i++) {
3362 struct bnxt_napi *bnapi = bp->bnapi[i];
3363 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3364 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3365
3366 rc = hwrm_ring_alloc_send_msg(bp, ring,
3367 HWRM_RING_ALLOC_RX, i,
3368 INVALID_STATS_CTX_ID);
3369 if (rc)
3370 goto err_out;
3371 rxr->rx_doorbell = bp->bar1 + i * 0x80;
3372 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3373 bp->grp_info[i].rx_fw_ring_id = ring->fw_ring_id;
3374 }
3375 }
3376
3377 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3378 for (i = 0; i < bp->rx_nr_rings; i++) {
3379 struct bnxt_napi *bnapi = bp->bnapi[i];
3380 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3381 struct bnxt_ring_struct *ring =
3382 &rxr->rx_agg_ring_struct;
3383
3384 rc = hwrm_ring_alloc_send_msg(bp, ring,
3385 HWRM_RING_ALLOC_AGG,
3386 bp->rx_nr_rings + i,
3387 INVALID_STATS_CTX_ID);
3388 if (rc)
3389 goto err_out;
3390
3391 rxr->rx_agg_doorbell =
3392 bp->bar1 + (bp->rx_nr_rings + i) * 0x80;
3393 writel(DB_KEY_RX | rxr->rx_agg_prod,
3394 rxr->rx_agg_doorbell);
3395 bp->grp_info[i].agg_fw_ring_id = ring->fw_ring_id;
3396 }
3397 }
3398 err_out:
3399 return rc;
3400 }
3401
hwrm_ring_free_send_msg(struct bnxt * bp,struct bnxt_ring_struct * ring,u32 ring_type,int cmpl_ring_id)3402 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3403 struct bnxt_ring_struct *ring,
3404 u32 ring_type, int cmpl_ring_id)
3405 {
3406 int rc;
3407 struct hwrm_ring_free_input req = {0};
3408 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3409 u16 error_code;
3410
3411 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, -1, -1);
3412 req.ring_type = ring_type;
3413 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3414
3415 mutex_lock(&bp->hwrm_cmd_lock);
3416 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3417 error_code = le16_to_cpu(resp->error_code);
3418 mutex_unlock(&bp->hwrm_cmd_lock);
3419
3420 if (rc || error_code) {
3421 switch (ring_type) {
3422 case RING_FREE_REQ_RING_TYPE_CMPL:
3423 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3424 rc);
3425 return rc;
3426 case RING_FREE_REQ_RING_TYPE_RX:
3427 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3428 rc);
3429 return rc;
3430 case RING_FREE_REQ_RING_TYPE_TX:
3431 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3432 rc);
3433 return rc;
3434 default:
3435 netdev_err(bp->dev, "Invalid ring\n");
3436 return -1;
3437 }
3438 }
3439 return 0;
3440 }
3441
bnxt_hwrm_ring_free(struct bnxt * bp,bool close_path)3442 static int bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3443 {
3444 int i, rc = 0;
3445
3446 if (!bp->bnapi)
3447 return 0;
3448
3449 if (bp->tx_nr_rings) {
3450 for (i = 0; i < bp->tx_nr_rings; i++) {
3451 struct bnxt_napi *bnapi = bp->bnapi[i];
3452 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
3453 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3454 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3455
3456 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3457 hwrm_ring_free_send_msg(
3458 bp, ring,
3459 RING_FREE_REQ_RING_TYPE_TX,
3460 close_path ? cmpl_ring_id :
3461 INVALID_HW_RING_ID);
3462 ring->fw_ring_id = INVALID_HW_RING_ID;
3463 }
3464 }
3465 }
3466
3467 if (bp->rx_nr_rings) {
3468 for (i = 0; i < bp->rx_nr_rings; i++) {
3469 struct bnxt_napi *bnapi = bp->bnapi[i];
3470 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3471 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3472 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3473
3474 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3475 hwrm_ring_free_send_msg(
3476 bp, ring,
3477 RING_FREE_REQ_RING_TYPE_RX,
3478 close_path ? cmpl_ring_id :
3479 INVALID_HW_RING_ID);
3480 ring->fw_ring_id = INVALID_HW_RING_ID;
3481 bp->grp_info[i].rx_fw_ring_id =
3482 INVALID_HW_RING_ID;
3483 }
3484 }
3485 }
3486
3487 if (bp->rx_agg_nr_pages) {
3488 for (i = 0; i < bp->rx_nr_rings; i++) {
3489 struct bnxt_napi *bnapi = bp->bnapi[i];
3490 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3491 struct bnxt_ring_struct *ring =
3492 &rxr->rx_agg_ring_struct;
3493 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3494
3495 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3496 hwrm_ring_free_send_msg(
3497 bp, ring,
3498 RING_FREE_REQ_RING_TYPE_RX,
3499 close_path ? cmpl_ring_id :
3500 INVALID_HW_RING_ID);
3501 ring->fw_ring_id = INVALID_HW_RING_ID;
3502 bp->grp_info[i].agg_fw_ring_id =
3503 INVALID_HW_RING_ID;
3504 }
3505 }
3506 }
3507
3508 if (bp->cp_nr_rings) {
3509 for (i = 0; i < bp->cp_nr_rings; i++) {
3510 struct bnxt_napi *bnapi = bp->bnapi[i];
3511 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3512 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3513
3514 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3515 hwrm_ring_free_send_msg(
3516 bp, ring,
3517 RING_FREE_REQ_RING_TYPE_CMPL,
3518 INVALID_HW_RING_ID);
3519 ring->fw_ring_id = INVALID_HW_RING_ID;
3520 bp->grp_info[i].cp_fw_ring_id =
3521 INVALID_HW_RING_ID;
3522 }
3523 }
3524 }
3525
3526 return rc;
3527 }
3528
bnxt_hwrm_set_coal(struct bnxt * bp)3529 int bnxt_hwrm_set_coal(struct bnxt *bp)
3530 {
3531 int i, rc = 0;
3532 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3533 u16 max_buf, max_buf_irq;
3534 u16 buf_tmr, buf_tmr_irq;
3535 u32 flags;
3536
3537 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
3538 -1, -1);
3539
3540 /* Each rx completion (2 records) should be DMAed immediately */
3541 max_buf = min_t(u16, bp->coal_bufs / 4, 2);
3542 /* max_buf must not be zero */
3543 max_buf = clamp_t(u16, max_buf, 1, 63);
3544 max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63);
3545 buf_tmr = max_t(u16, bp->coal_ticks / 4, 1);
3546 buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1);
3547
3548 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3549
3550 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3551 * if coal_ticks is less than 25 us.
3552 */
3553 if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25)
3554 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3555
3556 req.flags = cpu_to_le16(flags);
3557 req.num_cmpl_dma_aggr = cpu_to_le16(max_buf);
3558 req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq);
3559 req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr);
3560 req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq);
3561 req.int_lat_tmr_min = cpu_to_le16(buf_tmr);
3562 req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks);
3563 req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs);
3564
3565 mutex_lock(&bp->hwrm_cmd_lock);
3566 for (i = 0; i < bp->cp_nr_rings; i++) {
3567 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3568
3569 rc = _hwrm_send_message(bp, &req, sizeof(req),
3570 HWRM_CMD_TIMEOUT);
3571 if (rc)
3572 break;
3573 }
3574 mutex_unlock(&bp->hwrm_cmd_lock);
3575 return rc;
3576 }
3577
bnxt_hwrm_stat_ctx_free(struct bnxt * bp)3578 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3579 {
3580 int rc = 0, i;
3581 struct hwrm_stat_ctx_free_input req = {0};
3582
3583 if (!bp->bnapi)
3584 return 0;
3585
3586 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3587
3588 mutex_lock(&bp->hwrm_cmd_lock);
3589 for (i = 0; i < bp->cp_nr_rings; i++) {
3590 struct bnxt_napi *bnapi = bp->bnapi[i];
3591 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3592
3593 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3594 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3595
3596 rc = _hwrm_send_message(bp, &req, sizeof(req),
3597 HWRM_CMD_TIMEOUT);
3598 if (rc)
3599 break;
3600
3601 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3602 }
3603 }
3604 mutex_unlock(&bp->hwrm_cmd_lock);
3605 return rc;
3606 }
3607
bnxt_hwrm_stat_ctx_alloc(struct bnxt * bp)3608 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3609 {
3610 int rc = 0, i;
3611 struct hwrm_stat_ctx_alloc_input req = {0};
3612 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3613
3614 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3615
3616 req.update_period_ms = cpu_to_le32(1000);
3617
3618 mutex_lock(&bp->hwrm_cmd_lock);
3619 for (i = 0; i < bp->cp_nr_rings; i++) {
3620 struct bnxt_napi *bnapi = bp->bnapi[i];
3621 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3622
3623 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3624
3625 rc = _hwrm_send_message(bp, &req, sizeof(req),
3626 HWRM_CMD_TIMEOUT);
3627 if (rc)
3628 break;
3629
3630 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3631
3632 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3633 }
3634 mutex_unlock(&bp->hwrm_cmd_lock);
3635 return 0;
3636 }
3637
bnxt_hwrm_func_qcaps(struct bnxt * bp)3638 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3639 {
3640 int rc = 0;
3641 struct hwrm_func_qcaps_input req = {0};
3642 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3643
3644 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3645 req.fid = cpu_to_le16(0xffff);
3646
3647 mutex_lock(&bp->hwrm_cmd_lock);
3648 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3649 if (rc)
3650 goto hwrm_func_qcaps_exit;
3651
3652 if (BNXT_PF(bp)) {
3653 struct bnxt_pf_info *pf = &bp->pf;
3654
3655 pf->fw_fid = le16_to_cpu(resp->fid);
3656 pf->port_id = le16_to_cpu(resp->port_id);
3657 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3658 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
3659 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3660 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3661 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3662 pf->max_pf_tx_rings = pf->max_tx_rings;
3663 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3664 pf->max_pf_rx_rings = pf->max_rx_rings;
3665 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3666 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3667 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3668 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3669 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3670 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3671 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3672 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3673 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3674 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3675 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3676 } else {
3677 #ifdef CONFIG_BNXT_SRIOV
3678 struct bnxt_vf_info *vf = &bp->vf;
3679
3680 vf->fw_fid = le16_to_cpu(resp->fid);
3681 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3682 if (is_valid_ether_addr(vf->mac_addr))
3683 /* overwrite netdev dev_adr with admin VF MAC */
3684 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3685 else
3686 random_ether_addr(bp->dev->dev_addr);
3687
3688 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3689 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3690 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3691 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3692 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3693 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3694 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3695 #endif
3696 }
3697
3698 bp->tx_push_thresh = 0;
3699 if (resp->flags &
3700 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3701 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3702
3703 hwrm_func_qcaps_exit:
3704 mutex_unlock(&bp->hwrm_cmd_lock);
3705 return rc;
3706 }
3707
bnxt_hwrm_func_reset(struct bnxt * bp)3708 static int bnxt_hwrm_func_reset(struct bnxt *bp)
3709 {
3710 struct hwrm_func_reset_input req = {0};
3711
3712 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3713 req.enables = 0;
3714
3715 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3716 }
3717
bnxt_hwrm_queue_qportcfg(struct bnxt * bp)3718 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3719 {
3720 int rc = 0;
3721 struct hwrm_queue_qportcfg_input req = {0};
3722 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3723 u8 i, *qptr;
3724
3725 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3726
3727 mutex_lock(&bp->hwrm_cmd_lock);
3728 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3729 if (rc)
3730 goto qportcfg_exit;
3731
3732 if (!resp->max_configurable_queues) {
3733 rc = -EINVAL;
3734 goto qportcfg_exit;
3735 }
3736 bp->max_tc = resp->max_configurable_queues;
3737 if (bp->max_tc > BNXT_MAX_QUEUE)
3738 bp->max_tc = BNXT_MAX_QUEUE;
3739
3740 qptr = &resp->queue_id0;
3741 for (i = 0; i < bp->max_tc; i++) {
3742 bp->q_info[i].queue_id = *qptr++;
3743 bp->q_info[i].queue_profile = *qptr++;
3744 }
3745
3746 qportcfg_exit:
3747 mutex_unlock(&bp->hwrm_cmd_lock);
3748 return rc;
3749 }
3750
bnxt_hwrm_ver_get(struct bnxt * bp)3751 static int bnxt_hwrm_ver_get(struct bnxt *bp)
3752 {
3753 int rc;
3754 struct hwrm_ver_get_input req = {0};
3755 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3756
3757 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3758 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3759 req.hwrm_intf_min = HWRM_VERSION_MINOR;
3760 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3761 mutex_lock(&bp->hwrm_cmd_lock);
3762 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3763 if (rc)
3764 goto hwrm_ver_get_exit;
3765
3766 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3767
3768 if (req.hwrm_intf_maj != resp->hwrm_intf_maj ||
3769 req.hwrm_intf_min != resp->hwrm_intf_min ||
3770 req.hwrm_intf_upd != resp->hwrm_intf_upd) {
3771 netdev_warn(bp->dev, "HWRM interface %d.%d.%d does not match driver interface %d.%d.%d.\n",
3772 resp->hwrm_intf_maj, resp->hwrm_intf_min,
3773 resp->hwrm_intf_upd, req.hwrm_intf_maj,
3774 req.hwrm_intf_min, req.hwrm_intf_upd);
3775 netdev_warn(bp->dev, "Please update driver or firmware with matching interface versions.\n");
3776 }
3777 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d",
3778 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3779 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3780
3781 hwrm_ver_get_exit:
3782 mutex_unlock(&bp->hwrm_cmd_lock);
3783 return rc;
3784 }
3785
bnxt_hwrm_free_tunnel_ports(struct bnxt * bp)3786 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3787 {
3788 if (bp->vxlan_port_cnt) {
3789 bnxt_hwrm_tunnel_dst_port_free(
3790 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3791 }
3792 bp->vxlan_port_cnt = 0;
3793 if (bp->nge_port_cnt) {
3794 bnxt_hwrm_tunnel_dst_port_free(
3795 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3796 }
3797 bp->nge_port_cnt = 0;
3798 }
3799
bnxt_set_tpa(struct bnxt * bp,bool set_tpa)3800 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3801 {
3802 int rc, i;
3803 u32 tpa_flags = 0;
3804
3805 if (set_tpa)
3806 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3807 for (i = 0; i < bp->nr_vnics; i++) {
3808 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3809 if (rc) {
3810 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3811 rc, i);
3812 return rc;
3813 }
3814 }
3815 return 0;
3816 }
3817
bnxt_hwrm_clear_vnic_rss(struct bnxt * bp)3818 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3819 {
3820 int i;
3821
3822 for (i = 0; i < bp->nr_vnics; i++)
3823 bnxt_hwrm_vnic_set_rss(bp, i, false);
3824 }
3825
bnxt_hwrm_resource_free(struct bnxt * bp,bool close_path,bool irq_re_init)3826 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3827 bool irq_re_init)
3828 {
3829 if (bp->vnic_info) {
3830 bnxt_hwrm_clear_vnic_filter(bp);
3831 /* clear all RSS setting before free vnic ctx */
3832 bnxt_hwrm_clear_vnic_rss(bp);
3833 bnxt_hwrm_vnic_ctx_free(bp);
3834 /* before free the vnic, undo the vnic tpa settings */
3835 if (bp->flags & BNXT_FLAG_TPA)
3836 bnxt_set_tpa(bp, false);
3837 bnxt_hwrm_vnic_free(bp);
3838 }
3839 bnxt_hwrm_ring_free(bp, close_path);
3840 bnxt_hwrm_ring_grp_free(bp);
3841 if (irq_re_init) {
3842 bnxt_hwrm_stat_ctx_free(bp);
3843 bnxt_hwrm_free_tunnel_ports(bp);
3844 }
3845 }
3846
bnxt_setup_vnic(struct bnxt * bp,u16 vnic_id)3847 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3848 {
3849 int rc;
3850
3851 /* allocate context for vnic */
3852 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3853 if (rc) {
3854 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3855 vnic_id, rc);
3856 goto vnic_setup_err;
3857 }
3858 bp->rsscos_nr_ctxs++;
3859
3860 /* configure default vnic, ring grp */
3861 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3862 if (rc) {
3863 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3864 vnic_id, rc);
3865 goto vnic_setup_err;
3866 }
3867
3868 /* Enable RSS hashing on vnic */
3869 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3870 if (rc) {
3871 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3872 vnic_id, rc);
3873 goto vnic_setup_err;
3874 }
3875
3876 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3877 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3878 if (rc) {
3879 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3880 vnic_id, rc);
3881 }
3882 }
3883
3884 vnic_setup_err:
3885 return rc;
3886 }
3887
bnxt_alloc_rfs_vnics(struct bnxt * bp)3888 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3889 {
3890 #ifdef CONFIG_RFS_ACCEL
3891 int i, rc = 0;
3892
3893 for (i = 0; i < bp->rx_nr_rings; i++) {
3894 u16 vnic_id = i + 1;
3895 u16 ring_id = i;
3896
3897 if (vnic_id >= bp->nr_vnics)
3898 break;
3899
3900 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
3901 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, ring_id + 1);
3902 if (rc) {
3903 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3904 vnic_id, rc);
3905 break;
3906 }
3907 rc = bnxt_setup_vnic(bp, vnic_id);
3908 if (rc)
3909 break;
3910 }
3911 return rc;
3912 #else
3913 return 0;
3914 #endif
3915 }
3916
3917 static int bnxt_cfg_rx_mode(struct bnxt *);
3918
bnxt_init_chip(struct bnxt * bp,bool irq_re_init)3919 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3920 {
3921 int rc = 0;
3922
3923 if (irq_re_init) {
3924 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3925 if (rc) {
3926 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3927 rc);
3928 goto err_out;
3929 }
3930 }
3931
3932 rc = bnxt_hwrm_ring_alloc(bp);
3933 if (rc) {
3934 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3935 goto err_out;
3936 }
3937
3938 rc = bnxt_hwrm_ring_grp_alloc(bp);
3939 if (rc) {
3940 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3941 goto err_out;
3942 }
3943
3944 /* default vnic 0 */
3945 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3946 if (rc) {
3947 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3948 goto err_out;
3949 }
3950
3951 rc = bnxt_setup_vnic(bp, 0);
3952 if (rc)
3953 goto err_out;
3954
3955 if (bp->flags & BNXT_FLAG_RFS) {
3956 rc = bnxt_alloc_rfs_vnics(bp);
3957 if (rc)
3958 goto err_out;
3959 }
3960
3961 if (bp->flags & BNXT_FLAG_TPA) {
3962 rc = bnxt_set_tpa(bp, true);
3963 if (rc)
3964 goto err_out;
3965 }
3966
3967 if (BNXT_VF(bp))
3968 bnxt_update_vf_mac(bp);
3969
3970 /* Filter for default vnic 0 */
3971 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
3972 if (rc) {
3973 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
3974 goto err_out;
3975 }
3976 bp->vnic_info[0].uc_filter_count = 1;
3977
3978 bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_UNICAST |
3979 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
3980
3981 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
3982 bp->vnic_info[0].rx_mask |=
3983 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
3984
3985 rc = bnxt_cfg_rx_mode(bp);
3986 if (rc)
3987 goto err_out;
3988
3989 rc = bnxt_hwrm_set_coal(bp);
3990 if (rc)
3991 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
3992 rc);
3993
3994 return 0;
3995
3996 err_out:
3997 bnxt_hwrm_resource_free(bp, 0, true);
3998
3999 return rc;
4000 }
4001
bnxt_shutdown_nic(struct bnxt * bp,bool irq_re_init)4002 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4003 {
4004 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4005 return 0;
4006 }
4007
bnxt_init_nic(struct bnxt * bp,bool irq_re_init)4008 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4009 {
4010 bnxt_init_cp_rings(bp);
4011 bnxt_init_rx_rings(bp);
4012 bnxt_init_tx_rings(bp);
4013 bnxt_init_ring_grps(bp, irq_re_init);
4014 bnxt_init_vnics(bp);
4015
4016 return bnxt_init_chip(bp, irq_re_init);
4017 }
4018
bnxt_disable_int(struct bnxt * bp)4019 static void bnxt_disable_int(struct bnxt *bp)
4020 {
4021 int i;
4022
4023 if (!bp->bnapi)
4024 return;
4025
4026 for (i = 0; i < bp->cp_nr_rings; i++) {
4027 struct bnxt_napi *bnapi = bp->bnapi[i];
4028 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4029
4030 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4031 }
4032 }
4033
bnxt_enable_int(struct bnxt * bp)4034 static void bnxt_enable_int(struct bnxt *bp)
4035 {
4036 int i;
4037
4038 atomic_set(&bp->intr_sem, 0);
4039 for (i = 0; i < bp->cp_nr_rings; i++) {
4040 struct bnxt_napi *bnapi = bp->bnapi[i];
4041 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4042
4043 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4044 }
4045 }
4046
bnxt_set_real_num_queues(struct bnxt * bp)4047 static int bnxt_set_real_num_queues(struct bnxt *bp)
4048 {
4049 int rc;
4050 struct net_device *dev = bp->dev;
4051
4052 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4053 if (rc)
4054 return rc;
4055
4056 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4057 if (rc)
4058 return rc;
4059
4060 #ifdef CONFIG_RFS_ACCEL
4061 if (bp->rx_nr_rings)
4062 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4063 if (!dev->rx_cpu_rmap)
4064 rc = -ENOMEM;
4065 #endif
4066
4067 return rc;
4068 }
4069
bnxt_setup_msix(struct bnxt * bp)4070 static int bnxt_setup_msix(struct bnxt *bp)
4071 {
4072 struct msix_entry *msix_ent;
4073 struct net_device *dev = bp->dev;
4074 int i, total_vecs, rc = 0;
4075 const int len = sizeof(bp->irq_tbl[0].name);
4076
4077 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4078 total_vecs = bp->cp_nr_rings;
4079
4080 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4081 if (!msix_ent)
4082 return -ENOMEM;
4083
4084 for (i = 0; i < total_vecs; i++) {
4085 msix_ent[i].entry = i;
4086 msix_ent[i].vector = 0;
4087 }
4088
4089 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, 1, total_vecs);
4090 if (total_vecs < 0) {
4091 rc = -ENODEV;
4092 goto msix_setup_exit;
4093 }
4094
4095 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4096 if (bp->irq_tbl) {
4097 int tcs;
4098
4099 /* Trim rings based upon num of vectors allocated */
4100 bp->rx_nr_rings = min_t(int, total_vecs, bp->rx_nr_rings);
4101 bp->tx_nr_rings = min_t(int, total_vecs, bp->tx_nr_rings);
4102 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4103 tcs = netdev_get_num_tc(dev);
4104 if (tcs > 1) {
4105 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4106 if (bp->tx_nr_rings_per_tc == 0) {
4107 netdev_reset_tc(dev);
4108 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4109 } else {
4110 int i, off, count;
4111
4112 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4113 for (i = 0; i < tcs; i++) {
4114 count = bp->tx_nr_rings_per_tc;
4115 off = i * count;
4116 netdev_set_tc_queue(dev, i, count, off);
4117 }
4118 }
4119 }
4120 bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings);
4121
4122 for (i = 0; i < bp->cp_nr_rings; i++) {
4123 bp->irq_tbl[i].vector = msix_ent[i].vector;
4124 snprintf(bp->irq_tbl[i].name, len,
4125 "%s-%s-%d", dev->name, "TxRx", i);
4126 bp->irq_tbl[i].handler = bnxt_msix;
4127 }
4128 rc = bnxt_set_real_num_queues(bp);
4129 if (rc)
4130 goto msix_setup_exit;
4131 } else {
4132 rc = -ENOMEM;
4133 goto msix_setup_exit;
4134 }
4135 bp->flags |= BNXT_FLAG_USING_MSIX;
4136 kfree(msix_ent);
4137 return 0;
4138
4139 msix_setup_exit:
4140 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4141 pci_disable_msix(bp->pdev);
4142 kfree(msix_ent);
4143 return rc;
4144 }
4145
bnxt_setup_inta(struct bnxt * bp)4146 static int bnxt_setup_inta(struct bnxt *bp)
4147 {
4148 int rc;
4149 const int len = sizeof(bp->irq_tbl[0].name);
4150
4151 if (netdev_get_num_tc(bp->dev))
4152 netdev_reset_tc(bp->dev);
4153
4154 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4155 if (!bp->irq_tbl) {
4156 rc = -ENOMEM;
4157 return rc;
4158 }
4159 bp->rx_nr_rings = 1;
4160 bp->tx_nr_rings = 1;
4161 bp->cp_nr_rings = 1;
4162 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4163 bp->irq_tbl[0].vector = bp->pdev->irq;
4164 snprintf(bp->irq_tbl[0].name, len,
4165 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4166 bp->irq_tbl[0].handler = bnxt_inta;
4167 rc = bnxt_set_real_num_queues(bp);
4168 return rc;
4169 }
4170
bnxt_setup_int_mode(struct bnxt * bp)4171 static int bnxt_setup_int_mode(struct bnxt *bp)
4172 {
4173 int rc = 0;
4174
4175 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4176 rc = bnxt_setup_msix(bp);
4177
4178 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4179 /* fallback to INTA */
4180 rc = bnxt_setup_inta(bp);
4181 }
4182 return rc;
4183 }
4184
bnxt_free_irq(struct bnxt * bp)4185 static void bnxt_free_irq(struct bnxt *bp)
4186 {
4187 struct bnxt_irq *irq;
4188 int i;
4189
4190 #ifdef CONFIG_RFS_ACCEL
4191 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4192 bp->dev->rx_cpu_rmap = NULL;
4193 #endif
4194 if (!bp->irq_tbl)
4195 return;
4196
4197 for (i = 0; i < bp->cp_nr_rings; i++) {
4198 irq = &bp->irq_tbl[i];
4199 if (irq->requested)
4200 free_irq(irq->vector, bp->bnapi[i]);
4201 irq->requested = 0;
4202 }
4203 if (bp->flags & BNXT_FLAG_USING_MSIX)
4204 pci_disable_msix(bp->pdev);
4205 kfree(bp->irq_tbl);
4206 bp->irq_tbl = NULL;
4207 }
4208
bnxt_request_irq(struct bnxt * bp)4209 static int bnxt_request_irq(struct bnxt *bp)
4210 {
4211 int i, rc = 0;
4212 unsigned long flags = 0;
4213 #ifdef CONFIG_RFS_ACCEL
4214 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4215 #endif
4216
4217 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4218 flags = IRQF_SHARED;
4219
4220 for (i = 0; i < bp->cp_nr_rings; i++) {
4221 struct bnxt_irq *irq = &bp->irq_tbl[i];
4222 #ifdef CONFIG_RFS_ACCEL
4223 if (rmap && (i < bp->rx_nr_rings)) {
4224 rc = irq_cpu_rmap_add(rmap, irq->vector);
4225 if (rc)
4226 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4227 i);
4228 }
4229 #endif
4230 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4231 bp->bnapi[i]);
4232 if (rc)
4233 break;
4234
4235 irq->requested = 1;
4236 }
4237 return rc;
4238 }
4239
bnxt_del_napi(struct bnxt * bp)4240 static void bnxt_del_napi(struct bnxt *bp)
4241 {
4242 int i;
4243
4244 if (!bp->bnapi)
4245 return;
4246
4247 for (i = 0; i < bp->cp_nr_rings; i++) {
4248 struct bnxt_napi *bnapi = bp->bnapi[i];
4249
4250 napi_hash_del(&bnapi->napi);
4251 netif_napi_del(&bnapi->napi);
4252 }
4253 /* We called napi_hash_del() before netif_napi_del(), we need
4254 * to respect an RCU grace period before freeing napi structures.
4255 */
4256 synchronize_net();
4257 }
4258
bnxt_init_napi(struct bnxt * bp)4259 static void bnxt_init_napi(struct bnxt *bp)
4260 {
4261 int i;
4262 struct bnxt_napi *bnapi;
4263
4264 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4265 for (i = 0; i < bp->cp_nr_rings; i++) {
4266 bnapi = bp->bnapi[i];
4267 netif_napi_add(bp->dev, &bnapi->napi,
4268 bnxt_poll, 64);
4269 napi_hash_add(&bnapi->napi);
4270 }
4271 } else {
4272 bnapi = bp->bnapi[0];
4273 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4274 napi_hash_add(&bnapi->napi);
4275 }
4276 }
4277
bnxt_disable_napi(struct bnxt * bp)4278 static void bnxt_disable_napi(struct bnxt *bp)
4279 {
4280 int i;
4281
4282 if (!bp->bnapi)
4283 return;
4284
4285 for (i = 0; i < bp->cp_nr_rings; i++) {
4286 napi_disable(&bp->bnapi[i]->napi);
4287 bnxt_disable_poll(bp->bnapi[i]);
4288 }
4289 }
4290
bnxt_enable_napi(struct bnxt * bp)4291 static void bnxt_enable_napi(struct bnxt *bp)
4292 {
4293 int i;
4294
4295 for (i = 0; i < bp->cp_nr_rings; i++) {
4296 bnxt_enable_poll(bp->bnapi[i]);
4297 napi_enable(&bp->bnapi[i]->napi);
4298 }
4299 }
4300
bnxt_tx_disable(struct bnxt * bp)4301 static void bnxt_tx_disable(struct bnxt *bp)
4302 {
4303 int i;
4304 struct bnxt_napi *bnapi;
4305 struct bnxt_tx_ring_info *txr;
4306 struct netdev_queue *txq;
4307
4308 if (bp->bnapi) {
4309 for (i = 0; i < bp->tx_nr_rings; i++) {
4310 bnapi = bp->bnapi[i];
4311 txr = &bnapi->tx_ring;
4312 txq = netdev_get_tx_queue(bp->dev, i);
4313 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4314 }
4315 }
4316 /* Drop carrier first to prevent TX timeout */
4317 netif_carrier_off(bp->dev);
4318 /* Stop all TX queues */
4319 netif_tx_disable(bp->dev);
4320 }
4321
bnxt_tx_enable(struct bnxt * bp)4322 static void bnxt_tx_enable(struct bnxt *bp)
4323 {
4324 int i;
4325 struct bnxt_napi *bnapi;
4326 struct bnxt_tx_ring_info *txr;
4327 struct netdev_queue *txq;
4328
4329 for (i = 0; i < bp->tx_nr_rings; i++) {
4330 bnapi = bp->bnapi[i];
4331 txr = &bnapi->tx_ring;
4332 txq = netdev_get_tx_queue(bp->dev, i);
4333 txr->dev_state = 0;
4334 }
4335 netif_tx_wake_all_queues(bp->dev);
4336 if (bp->link_info.link_up)
4337 netif_carrier_on(bp->dev);
4338 }
4339
bnxt_report_link(struct bnxt * bp)4340 static void bnxt_report_link(struct bnxt *bp)
4341 {
4342 if (bp->link_info.link_up) {
4343 const char *duplex;
4344 const char *flow_ctrl;
4345 u16 speed;
4346
4347 netif_carrier_on(bp->dev);
4348 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4349 duplex = "full";
4350 else
4351 duplex = "half";
4352 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4353 flow_ctrl = "ON - receive & transmit";
4354 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4355 flow_ctrl = "ON - transmit";
4356 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4357 flow_ctrl = "ON - receive";
4358 else
4359 flow_ctrl = "none";
4360 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4361 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4362 speed, duplex, flow_ctrl);
4363 } else {
4364 netif_carrier_off(bp->dev);
4365 netdev_err(bp->dev, "NIC Link is Down\n");
4366 }
4367 }
4368
bnxt_update_link(struct bnxt * bp,bool chng_link_state)4369 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4370 {
4371 int rc = 0;
4372 struct bnxt_link_info *link_info = &bp->link_info;
4373 struct hwrm_port_phy_qcfg_input req = {0};
4374 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4375 u8 link_up = link_info->link_up;
4376
4377 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4378
4379 mutex_lock(&bp->hwrm_cmd_lock);
4380 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4381 if (rc) {
4382 mutex_unlock(&bp->hwrm_cmd_lock);
4383 return rc;
4384 }
4385
4386 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4387 link_info->phy_link_status = resp->link;
4388 link_info->duplex = resp->duplex;
4389 link_info->pause = resp->pause;
4390 link_info->auto_mode = resp->auto_mode;
4391 link_info->auto_pause_setting = resp->auto_pause;
4392 link_info->force_pause_setting = resp->force_pause;
4393 link_info->duplex_setting = resp->duplex_setting;
4394 if (link_info->phy_link_status == BNXT_LINK_LINK)
4395 link_info->link_speed = le16_to_cpu(resp->link_speed);
4396 else
4397 link_info->link_speed = 0;
4398 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4399 link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4400 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4401 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4402 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4403 link_info->phy_ver[0] = resp->phy_maj;
4404 link_info->phy_ver[1] = resp->phy_min;
4405 link_info->phy_ver[2] = resp->phy_bld;
4406 link_info->media_type = resp->media_type;
4407 link_info->transceiver = resp->transceiver_type;
4408 link_info->phy_addr = resp->phy_addr;
4409
4410 /* TODO: need to add more logic to report VF link */
4411 if (chng_link_state) {
4412 if (link_info->phy_link_status == BNXT_LINK_LINK)
4413 link_info->link_up = 1;
4414 else
4415 link_info->link_up = 0;
4416 if (link_up != link_info->link_up)
4417 bnxt_report_link(bp);
4418 } else {
4419 /* alwasy link down if not require to update link state */
4420 link_info->link_up = 0;
4421 }
4422 mutex_unlock(&bp->hwrm_cmd_lock);
4423 return 0;
4424 }
4425
4426 static void
bnxt_hwrm_set_pause_common(struct bnxt * bp,struct hwrm_port_phy_cfg_input * req)4427 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4428 {
4429 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4430 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4431 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4432 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4433 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4434 req->enables |=
4435 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4436 } else {
4437 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4438 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4439 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4440 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4441 req->enables |=
4442 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4443 }
4444 }
4445
bnxt_hwrm_set_link_common(struct bnxt * bp,struct hwrm_port_phy_cfg_input * req)4446 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4447 struct hwrm_port_phy_cfg_input *req)
4448 {
4449 u8 autoneg = bp->link_info.autoneg;
4450 u16 fw_link_speed = bp->link_info.req_link_speed;
4451 u32 advertising = bp->link_info.advertising;
4452
4453 if (autoneg & BNXT_AUTONEG_SPEED) {
4454 req->auto_mode |=
4455 PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4456
4457 req->enables |= cpu_to_le32(
4458 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4459 req->auto_link_speed_mask = cpu_to_le16(advertising);
4460
4461 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4462 req->flags |=
4463 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4464 } else {
4465 req->force_link_speed = cpu_to_le16(fw_link_speed);
4466 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4467 }
4468
4469 /* currently don't support half duplex */
4470 req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4471 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4472 /* tell chimp that the setting takes effect immediately */
4473 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4474 }
4475
bnxt_hwrm_set_pause(struct bnxt * bp)4476 int bnxt_hwrm_set_pause(struct bnxt *bp)
4477 {
4478 struct hwrm_port_phy_cfg_input req = {0};
4479 int rc;
4480
4481 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4482 bnxt_hwrm_set_pause_common(bp, &req);
4483
4484 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4485 bp->link_info.force_link_chng)
4486 bnxt_hwrm_set_link_common(bp, &req);
4487
4488 mutex_lock(&bp->hwrm_cmd_lock);
4489 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4490 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4491 /* since changing of pause setting doesn't trigger any link
4492 * change event, the driver needs to update the current pause
4493 * result upon successfully return of the phy_cfg command
4494 */
4495 bp->link_info.pause =
4496 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4497 bp->link_info.auto_pause_setting = 0;
4498 if (!bp->link_info.force_link_chng)
4499 bnxt_report_link(bp);
4500 }
4501 bp->link_info.force_link_chng = false;
4502 mutex_unlock(&bp->hwrm_cmd_lock);
4503 return rc;
4504 }
4505
bnxt_hwrm_set_link_setting(struct bnxt * bp,bool set_pause)4506 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4507 {
4508 struct hwrm_port_phy_cfg_input req = {0};
4509
4510 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4511 if (set_pause)
4512 bnxt_hwrm_set_pause_common(bp, &req);
4513
4514 bnxt_hwrm_set_link_common(bp, &req);
4515 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4516 }
4517
bnxt_update_phy_setting(struct bnxt * bp)4518 static int bnxt_update_phy_setting(struct bnxt *bp)
4519 {
4520 int rc;
4521 bool update_link = false;
4522 bool update_pause = false;
4523 struct bnxt_link_info *link_info = &bp->link_info;
4524
4525 rc = bnxt_update_link(bp, true);
4526 if (rc) {
4527 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4528 rc);
4529 return rc;
4530 }
4531 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4532 link_info->auto_pause_setting != link_info->req_flow_ctrl)
4533 update_pause = true;
4534 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4535 link_info->force_pause_setting != link_info->req_flow_ctrl)
4536 update_pause = true;
4537 if (link_info->req_duplex != link_info->duplex_setting)
4538 update_link = true;
4539 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4540 if (BNXT_AUTO_MODE(link_info->auto_mode))
4541 update_link = true;
4542 if (link_info->req_link_speed != link_info->force_link_speed)
4543 update_link = true;
4544 } else {
4545 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4546 update_link = true;
4547 if (link_info->advertising != link_info->auto_link_speeds)
4548 update_link = true;
4549 if (link_info->req_link_speed != link_info->auto_link_speed)
4550 update_link = true;
4551 }
4552
4553 if (update_link)
4554 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4555 else if (update_pause)
4556 rc = bnxt_hwrm_set_pause(bp);
4557 if (rc) {
4558 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4559 rc);
4560 return rc;
4561 }
4562
4563 return rc;
4564 }
4565
4566 /* Common routine to pre-map certain register block to different GRC window.
4567 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4568 * in PF and 3 windows in VF that can be customized to map in different
4569 * register blocks.
4570 */
bnxt_preset_reg_win(struct bnxt * bp)4571 static void bnxt_preset_reg_win(struct bnxt *bp)
4572 {
4573 if (BNXT_PF(bp)) {
4574 /* CAG registers map to GRC window #4 */
4575 writel(BNXT_CAG_REG_BASE,
4576 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4577 }
4578 }
4579
__bnxt_open_nic(struct bnxt * bp,bool irq_re_init,bool link_re_init)4580 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4581 {
4582 int rc = 0;
4583
4584 bnxt_preset_reg_win(bp);
4585 netif_carrier_off(bp->dev);
4586 if (irq_re_init) {
4587 rc = bnxt_setup_int_mode(bp);
4588 if (rc) {
4589 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4590 rc);
4591 return rc;
4592 }
4593 }
4594 if ((bp->flags & BNXT_FLAG_RFS) &&
4595 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4596 /* disable RFS if falling back to INTA */
4597 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4598 bp->flags &= ~BNXT_FLAG_RFS;
4599 }
4600
4601 rc = bnxt_alloc_mem(bp, irq_re_init);
4602 if (rc) {
4603 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4604 goto open_err_free_mem;
4605 }
4606
4607 if (irq_re_init) {
4608 bnxt_init_napi(bp);
4609 rc = bnxt_request_irq(bp);
4610 if (rc) {
4611 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4612 goto open_err_irq;
4613 }
4614 }
4615
4616 rc = bnxt_init_nic(bp, irq_re_init);
4617 if (rc) {
4618 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4619 goto open_err_irq;
4620 }
4621
4622 bnxt_enable_napi(bp);
4623
4624 if (link_re_init) {
4625 rc = bnxt_update_phy_setting(bp);
4626 if (rc)
4627 netdev_warn(bp->dev, "failed to update phy settings\n");
4628 }
4629
4630 if (irq_re_init) {
4631 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4632 vxlan_get_rx_port(bp->dev);
4633 #endif
4634 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4635 bp, htons(0x17c1),
4636 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4637 bp->nge_port_cnt = 1;
4638 }
4639
4640 set_bit(BNXT_STATE_OPEN, &bp->state);
4641 bnxt_enable_int(bp);
4642 /* Enable TX queues */
4643 bnxt_tx_enable(bp);
4644 mod_timer(&bp->timer, jiffies + bp->current_interval);
4645
4646 return 0;
4647
4648 open_err_irq:
4649 bnxt_del_napi(bp);
4650
4651 open_err_free_mem:
4652 bnxt_free_skbs(bp);
4653 bnxt_free_irq(bp);
4654 bnxt_free_mem(bp, true);
4655 return rc;
4656 }
4657
4658 /* rtnl_lock held */
bnxt_open_nic(struct bnxt * bp,bool irq_re_init,bool link_re_init)4659 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4660 {
4661 int rc = 0;
4662
4663 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4664 if (rc) {
4665 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4666 dev_close(bp->dev);
4667 }
4668 return rc;
4669 }
4670
bnxt_open(struct net_device * dev)4671 static int bnxt_open(struct net_device *dev)
4672 {
4673 struct bnxt *bp = netdev_priv(dev);
4674 int rc = 0;
4675
4676 rc = bnxt_hwrm_func_reset(bp);
4677 if (rc) {
4678 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4679 rc);
4680 rc = -1;
4681 return rc;
4682 }
4683 return __bnxt_open_nic(bp, true, true);
4684 }
4685
bnxt_disable_int_sync(struct bnxt * bp)4686 static void bnxt_disable_int_sync(struct bnxt *bp)
4687 {
4688 int i;
4689
4690 atomic_inc(&bp->intr_sem);
4691 if (!netif_running(bp->dev))
4692 return;
4693
4694 bnxt_disable_int(bp);
4695 for (i = 0; i < bp->cp_nr_rings; i++)
4696 synchronize_irq(bp->irq_tbl[i].vector);
4697 }
4698
bnxt_close_nic(struct bnxt * bp,bool irq_re_init,bool link_re_init)4699 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4700 {
4701 int rc = 0;
4702
4703 #ifdef CONFIG_BNXT_SRIOV
4704 if (bp->sriov_cfg) {
4705 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4706 !bp->sriov_cfg,
4707 BNXT_SRIOV_CFG_WAIT_TMO);
4708 if (rc)
4709 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4710 }
4711 #endif
4712 /* Change device state to avoid TX queue wake up's */
4713 bnxt_tx_disable(bp);
4714
4715 clear_bit(BNXT_STATE_OPEN, &bp->state);
4716 smp_mb__after_atomic();
4717 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4718 msleep(20);
4719
4720 /* Flush rings before disabling interrupts */
4721 bnxt_shutdown_nic(bp, irq_re_init);
4722
4723 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4724
4725 bnxt_disable_napi(bp);
4726 bnxt_disable_int_sync(bp);
4727 del_timer_sync(&bp->timer);
4728 bnxt_free_skbs(bp);
4729
4730 if (irq_re_init) {
4731 bnxt_free_irq(bp);
4732 bnxt_del_napi(bp);
4733 }
4734 bnxt_free_mem(bp, irq_re_init);
4735 return rc;
4736 }
4737
bnxt_close(struct net_device * dev)4738 static int bnxt_close(struct net_device *dev)
4739 {
4740 struct bnxt *bp = netdev_priv(dev);
4741
4742 bnxt_close_nic(bp, true, true);
4743 return 0;
4744 }
4745
4746 /* rtnl_lock held */
bnxt_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)4747 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4748 {
4749 switch (cmd) {
4750 case SIOCGMIIPHY:
4751 /* fallthru */
4752 case SIOCGMIIREG: {
4753 if (!netif_running(dev))
4754 return -EAGAIN;
4755
4756 return 0;
4757 }
4758
4759 case SIOCSMIIREG:
4760 if (!netif_running(dev))
4761 return -EAGAIN;
4762
4763 return 0;
4764
4765 default:
4766 /* do nothing */
4767 break;
4768 }
4769 return -EOPNOTSUPP;
4770 }
4771
4772 static struct rtnl_link_stats64 *
bnxt_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)4773 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4774 {
4775 u32 i;
4776 struct bnxt *bp = netdev_priv(dev);
4777
4778 memset(stats, 0, sizeof(struct rtnl_link_stats64));
4779
4780 if (!bp->bnapi)
4781 return stats;
4782
4783 /* TODO check if we need to synchronize with bnxt_close path */
4784 for (i = 0; i < bp->cp_nr_rings; i++) {
4785 struct bnxt_napi *bnapi = bp->bnapi[i];
4786 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4787 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4788
4789 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4790 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4791 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4792
4793 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4794 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4795 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4796
4797 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4798 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4799 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4800
4801 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4802 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4803 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4804
4805 stats->rx_missed_errors +=
4806 le64_to_cpu(hw_stats->rx_discard_pkts);
4807
4808 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4809
4810 stats->rx_dropped += le64_to_cpu(hw_stats->rx_drop_pkts);
4811
4812 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4813 }
4814
4815 return stats;
4816 }
4817
bnxt_mc_list_updated(struct bnxt * bp,u32 * rx_mask)4818 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4819 {
4820 struct net_device *dev = bp->dev;
4821 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4822 struct netdev_hw_addr *ha;
4823 u8 *haddr;
4824 int mc_count = 0;
4825 bool update = false;
4826 int off = 0;
4827
4828 netdev_for_each_mc_addr(ha, dev) {
4829 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4830 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4831 vnic->mc_list_count = 0;
4832 return false;
4833 }
4834 haddr = ha->addr;
4835 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4836 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4837 update = true;
4838 }
4839 off += ETH_ALEN;
4840 mc_count++;
4841 }
4842 if (mc_count)
4843 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4844
4845 if (mc_count != vnic->mc_list_count) {
4846 vnic->mc_list_count = mc_count;
4847 update = true;
4848 }
4849 return update;
4850 }
4851
bnxt_uc_list_updated(struct bnxt * bp)4852 static bool bnxt_uc_list_updated(struct bnxt *bp)
4853 {
4854 struct net_device *dev = bp->dev;
4855 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4856 struct netdev_hw_addr *ha;
4857 int off = 0;
4858
4859 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4860 return true;
4861
4862 netdev_for_each_uc_addr(ha, dev) {
4863 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4864 return true;
4865
4866 off += ETH_ALEN;
4867 }
4868 return false;
4869 }
4870
bnxt_set_rx_mode(struct net_device * dev)4871 static void bnxt_set_rx_mode(struct net_device *dev)
4872 {
4873 struct bnxt *bp = netdev_priv(dev);
4874 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4875 u32 mask = vnic->rx_mask;
4876 bool mc_update = false;
4877 bool uc_update;
4878
4879 if (!netif_running(dev))
4880 return;
4881
4882 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4883 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4884 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4885
4886 /* Only allow PF to be in promiscuous mode */
4887 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4888 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4889
4890 uc_update = bnxt_uc_list_updated(bp);
4891
4892 if (dev->flags & IFF_ALLMULTI) {
4893 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4894 vnic->mc_list_count = 0;
4895 } else {
4896 mc_update = bnxt_mc_list_updated(bp, &mask);
4897 }
4898
4899 if (mask != vnic->rx_mask || uc_update || mc_update) {
4900 vnic->rx_mask = mask;
4901
4902 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4903 schedule_work(&bp->sp_task);
4904 }
4905 }
4906
bnxt_cfg_rx_mode(struct bnxt * bp)4907 static int bnxt_cfg_rx_mode(struct bnxt *bp)
4908 {
4909 struct net_device *dev = bp->dev;
4910 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4911 struct netdev_hw_addr *ha;
4912 int i, off = 0, rc;
4913 bool uc_update;
4914
4915 netif_addr_lock_bh(dev);
4916 uc_update = bnxt_uc_list_updated(bp);
4917 netif_addr_unlock_bh(dev);
4918
4919 if (!uc_update)
4920 goto skip_uc;
4921
4922 mutex_lock(&bp->hwrm_cmd_lock);
4923 for (i = 1; i < vnic->uc_filter_count; i++) {
4924 struct hwrm_cfa_l2_filter_free_input req = {0};
4925
4926 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
4927 -1);
4928
4929 req.l2_filter_id = vnic->fw_l2_filter_id[i];
4930
4931 rc = _hwrm_send_message(bp, &req, sizeof(req),
4932 HWRM_CMD_TIMEOUT);
4933 }
4934 mutex_unlock(&bp->hwrm_cmd_lock);
4935
4936 vnic->uc_filter_count = 1;
4937
4938 netif_addr_lock_bh(dev);
4939 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
4940 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4941 } else {
4942 netdev_for_each_uc_addr(ha, dev) {
4943 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
4944 off += ETH_ALEN;
4945 vnic->uc_filter_count++;
4946 }
4947 }
4948 netif_addr_unlock_bh(dev);
4949
4950 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
4951 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
4952 if (rc) {
4953 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
4954 rc);
4955 vnic->uc_filter_count = i;
4956 return rc;
4957 }
4958 }
4959
4960 skip_uc:
4961 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4962 if (rc && vnic->mc_list_count) {
4963 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
4964 rc);
4965 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4966 vnic->mc_list_count = 0;
4967 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4968 }
4969 if (rc)
4970 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
4971 rc);
4972
4973 return rc;
4974 }
4975
bnxt_fix_features(struct net_device * dev,netdev_features_t features)4976 static netdev_features_t bnxt_fix_features(struct net_device *dev,
4977 netdev_features_t features)
4978 {
4979 return features;
4980 }
4981
bnxt_set_features(struct net_device * dev,netdev_features_t features)4982 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
4983 {
4984 struct bnxt *bp = netdev_priv(dev);
4985 u32 flags = bp->flags;
4986 u32 changes;
4987 int rc = 0;
4988 bool re_init = false;
4989 bool update_tpa = false;
4990
4991 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
4992 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
4993 flags |= BNXT_FLAG_GRO;
4994 if (features & NETIF_F_LRO)
4995 flags |= BNXT_FLAG_LRO;
4996
4997 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4998 flags |= BNXT_FLAG_STRIP_VLAN;
4999
5000 if (features & NETIF_F_NTUPLE)
5001 flags |= BNXT_FLAG_RFS;
5002
5003 changes = flags ^ bp->flags;
5004 if (changes & BNXT_FLAG_TPA) {
5005 update_tpa = true;
5006 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5007 (flags & BNXT_FLAG_TPA) == 0)
5008 re_init = true;
5009 }
5010
5011 if (changes & ~BNXT_FLAG_TPA)
5012 re_init = true;
5013
5014 if (flags != bp->flags) {
5015 u32 old_flags = bp->flags;
5016
5017 bp->flags = flags;
5018
5019 if (!netif_running(dev)) {
5020 if (update_tpa)
5021 bnxt_set_ring_params(bp);
5022 return rc;
5023 }
5024
5025 if (re_init) {
5026 bnxt_close_nic(bp, false, false);
5027 if (update_tpa)
5028 bnxt_set_ring_params(bp);
5029
5030 return bnxt_open_nic(bp, false, false);
5031 }
5032 if (update_tpa) {
5033 rc = bnxt_set_tpa(bp,
5034 (flags & BNXT_FLAG_TPA) ?
5035 true : false);
5036 if (rc)
5037 bp->flags = old_flags;
5038 }
5039 }
5040 return rc;
5041 }
5042
bnxt_dbg_dump_states(struct bnxt * bp)5043 static void bnxt_dbg_dump_states(struct bnxt *bp)
5044 {
5045 int i;
5046 struct bnxt_napi *bnapi;
5047 struct bnxt_tx_ring_info *txr;
5048 struct bnxt_rx_ring_info *rxr;
5049 struct bnxt_cp_ring_info *cpr;
5050
5051 for (i = 0; i < bp->cp_nr_rings; i++) {
5052 bnapi = bp->bnapi[i];
5053 txr = &bnapi->tx_ring;
5054 rxr = &bnapi->rx_ring;
5055 cpr = &bnapi->cp_ring;
5056 if (netif_msg_drv(bp)) {
5057 netdev_info(bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5058 i, txr->tx_ring_struct.fw_ring_id,
5059 txr->tx_prod, txr->tx_cons);
5060 netdev_info(bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5061 i, rxr->rx_ring_struct.fw_ring_id,
5062 rxr->rx_prod,
5063 rxr->rx_agg_ring_struct.fw_ring_id,
5064 rxr->rx_agg_prod, rxr->rx_sw_agg_prod);
5065 netdev_info(bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5066 i, cpr->cp_ring_struct.fw_ring_id,
5067 cpr->cp_raw_cons);
5068 }
5069 }
5070 }
5071
bnxt_reset_task(struct bnxt * bp)5072 static void bnxt_reset_task(struct bnxt *bp)
5073 {
5074 bnxt_dbg_dump_states(bp);
5075 if (netif_running(bp->dev)) {
5076 bnxt_close_nic(bp, false, false);
5077 bnxt_open_nic(bp, false, false);
5078 }
5079 }
5080
bnxt_tx_timeout(struct net_device * dev)5081 static void bnxt_tx_timeout(struct net_device *dev)
5082 {
5083 struct bnxt *bp = netdev_priv(dev);
5084
5085 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5086 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5087 schedule_work(&bp->sp_task);
5088 }
5089
5090 #ifdef CONFIG_NET_POLL_CONTROLLER
bnxt_poll_controller(struct net_device * dev)5091 static void bnxt_poll_controller(struct net_device *dev)
5092 {
5093 struct bnxt *bp = netdev_priv(dev);
5094 int i;
5095
5096 for (i = 0; i < bp->cp_nr_rings; i++) {
5097 struct bnxt_irq *irq = &bp->irq_tbl[i];
5098
5099 disable_irq(irq->vector);
5100 irq->handler(irq->vector, bp->bnapi[i]);
5101 enable_irq(irq->vector);
5102 }
5103 }
5104 #endif
5105
bnxt_timer(unsigned long data)5106 static void bnxt_timer(unsigned long data)
5107 {
5108 struct bnxt *bp = (struct bnxt *)data;
5109 struct net_device *dev = bp->dev;
5110
5111 if (!netif_running(dev))
5112 return;
5113
5114 if (atomic_read(&bp->intr_sem) != 0)
5115 goto bnxt_restart_timer;
5116
5117 bnxt_restart_timer:
5118 mod_timer(&bp->timer, jiffies + bp->current_interval);
5119 }
5120
5121 static void bnxt_cfg_ntp_filters(struct bnxt *);
5122
bnxt_sp_task(struct work_struct * work)5123 static void bnxt_sp_task(struct work_struct *work)
5124 {
5125 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5126 int rc;
5127
5128 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5129 smp_mb__after_atomic();
5130 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5131 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5132 return;
5133 }
5134
5135 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5136 bnxt_cfg_rx_mode(bp);
5137
5138 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5139 bnxt_cfg_ntp_filters(bp);
5140 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5141 rc = bnxt_update_link(bp, true);
5142 if (rc)
5143 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5144 rc);
5145 }
5146 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5147 bnxt_hwrm_exec_fwd_req(bp);
5148 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5149 bnxt_hwrm_tunnel_dst_port_alloc(
5150 bp, bp->vxlan_port,
5151 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5152 }
5153 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5154 bnxt_hwrm_tunnel_dst_port_free(
5155 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5156 }
5157 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5158 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5159 * for BNXT_STATE_IN_SP_TASK to clear.
5160 */
5161 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5162 rtnl_lock();
5163 bnxt_reset_task(bp);
5164 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5165 rtnl_unlock();
5166 }
5167
5168 smp_mb__before_atomic();
5169 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5170 }
5171
bnxt_init_board(struct pci_dev * pdev,struct net_device * dev)5172 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5173 {
5174 int rc;
5175 struct bnxt *bp = netdev_priv(dev);
5176
5177 SET_NETDEV_DEV(dev, &pdev->dev);
5178
5179 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5180 rc = pci_enable_device(pdev);
5181 if (rc) {
5182 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5183 goto init_err;
5184 }
5185
5186 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5187 dev_err(&pdev->dev,
5188 "Cannot find PCI device base address, aborting\n");
5189 rc = -ENODEV;
5190 goto init_err_disable;
5191 }
5192
5193 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5194 if (rc) {
5195 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5196 goto init_err_disable;
5197 }
5198
5199 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5200 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5201 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5202 rc = -EIO;
5203 goto init_err_release;
5204 }
5205
5206 pci_set_master(pdev);
5207
5208 bp->dev = dev;
5209 bp->pdev = pdev;
5210
5211 bp->bar0 = pci_ioremap_bar(pdev, 0);
5212 if (!bp->bar0) {
5213 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5214 rc = -ENOMEM;
5215 goto init_err_release;
5216 }
5217
5218 bp->bar1 = pci_ioremap_bar(pdev, 2);
5219 if (!bp->bar1) {
5220 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5221 rc = -ENOMEM;
5222 goto init_err_release;
5223 }
5224
5225 bp->bar2 = pci_ioremap_bar(pdev, 4);
5226 if (!bp->bar2) {
5227 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5228 rc = -ENOMEM;
5229 goto init_err_release;
5230 }
5231
5232 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5233
5234 spin_lock_init(&bp->ntp_fltr_lock);
5235
5236 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5237 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5238
5239 bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4);
5240 bp->coal_bufs = 20;
5241 bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1);
5242 bp->coal_bufs_irq = 2;
5243
5244 init_timer(&bp->timer);
5245 bp->timer.data = (unsigned long)bp;
5246 bp->timer.function = bnxt_timer;
5247 bp->current_interval = BNXT_TIMER_INTERVAL;
5248
5249 clear_bit(BNXT_STATE_OPEN, &bp->state);
5250
5251 return 0;
5252
5253 init_err_release:
5254 if (bp->bar2) {
5255 pci_iounmap(pdev, bp->bar2);
5256 bp->bar2 = NULL;
5257 }
5258
5259 if (bp->bar1) {
5260 pci_iounmap(pdev, bp->bar1);
5261 bp->bar1 = NULL;
5262 }
5263
5264 if (bp->bar0) {
5265 pci_iounmap(pdev, bp->bar0);
5266 bp->bar0 = NULL;
5267 }
5268
5269 pci_release_regions(pdev);
5270
5271 init_err_disable:
5272 pci_disable_device(pdev);
5273
5274 init_err:
5275 return rc;
5276 }
5277
5278 /* rtnl_lock held */
bnxt_change_mac_addr(struct net_device * dev,void * p)5279 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5280 {
5281 struct sockaddr *addr = p;
5282 struct bnxt *bp = netdev_priv(dev);
5283 int rc = 0;
5284
5285 if (!is_valid_ether_addr(addr->sa_data))
5286 return -EADDRNOTAVAIL;
5287
5288 #ifdef CONFIG_BNXT_SRIOV
5289 if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5290 return -EADDRNOTAVAIL;
5291 #endif
5292
5293 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5294 return 0;
5295
5296 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5297 if (netif_running(dev)) {
5298 bnxt_close_nic(bp, false, false);
5299 rc = bnxt_open_nic(bp, false, false);
5300 }
5301
5302 return rc;
5303 }
5304
5305 /* rtnl_lock held */
bnxt_change_mtu(struct net_device * dev,int new_mtu)5306 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5307 {
5308 struct bnxt *bp = netdev_priv(dev);
5309
5310 if (new_mtu < 60 || new_mtu > 9000)
5311 return -EINVAL;
5312
5313 if (netif_running(dev))
5314 bnxt_close_nic(bp, true, false);
5315
5316 dev->mtu = new_mtu;
5317 bnxt_set_ring_params(bp);
5318
5319 if (netif_running(dev))
5320 return bnxt_open_nic(bp, true, false);
5321
5322 return 0;
5323 }
5324
bnxt_setup_tc(struct net_device * dev,u8 tc)5325 static int bnxt_setup_tc(struct net_device *dev, u8 tc)
5326 {
5327 struct bnxt *bp = netdev_priv(dev);
5328
5329 if (tc > bp->max_tc) {
5330 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5331 tc, bp->max_tc);
5332 return -EINVAL;
5333 }
5334
5335 if (netdev_get_num_tc(dev) == tc)
5336 return 0;
5337
5338 if (tc) {
5339 int max_rx_rings, max_tx_rings;
5340
5341 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings);
5342 if (bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5343 return -ENOMEM;
5344 }
5345
5346 /* Needs to close the device and do hw resource re-allocations */
5347 if (netif_running(bp->dev))
5348 bnxt_close_nic(bp, true, false);
5349
5350 if (tc) {
5351 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5352 netdev_set_num_tc(dev, tc);
5353 } else {
5354 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5355 netdev_reset_tc(dev);
5356 }
5357 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5358 bp->num_stat_ctxs = bp->cp_nr_rings;
5359
5360 if (netif_running(bp->dev))
5361 return bnxt_open_nic(bp, true, false);
5362
5363 return 0;
5364 }
5365
5366 #ifdef CONFIG_RFS_ACCEL
bnxt_fltr_match(struct bnxt_ntuple_filter * f1,struct bnxt_ntuple_filter * f2)5367 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5368 struct bnxt_ntuple_filter *f2)
5369 {
5370 struct flow_keys *keys1 = &f1->fkeys;
5371 struct flow_keys *keys2 = &f2->fkeys;
5372
5373 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5374 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5375 keys1->ports.ports == keys2->ports.ports &&
5376 keys1->basic.ip_proto == keys2->basic.ip_proto &&
5377 keys1->basic.n_proto == keys2->basic.n_proto &&
5378 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5379 return true;
5380
5381 return false;
5382 }
5383
bnxt_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)5384 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5385 u16 rxq_index, u32 flow_id)
5386 {
5387 struct bnxt *bp = netdev_priv(dev);
5388 struct bnxt_ntuple_filter *fltr, *new_fltr;
5389 struct flow_keys *fkeys;
5390 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
5391 int rc = 0, idx, bit_id;
5392 struct hlist_head *head;
5393
5394 if (skb->encapsulation)
5395 return -EPROTONOSUPPORT;
5396
5397 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5398 if (!new_fltr)
5399 return -ENOMEM;
5400
5401 fkeys = &new_fltr->fkeys;
5402 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5403 rc = -EPROTONOSUPPORT;
5404 goto err_free;
5405 }
5406
5407 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5408 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5409 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5410 rc = -EPROTONOSUPPORT;
5411 goto err_free;
5412 }
5413
5414 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5415
5416 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5417 head = &bp->ntp_fltr_hash_tbl[idx];
5418 rcu_read_lock();
5419 hlist_for_each_entry_rcu(fltr, head, hash) {
5420 if (bnxt_fltr_match(fltr, new_fltr)) {
5421 rcu_read_unlock();
5422 rc = 0;
5423 goto err_free;
5424 }
5425 }
5426 rcu_read_unlock();
5427
5428 spin_lock_bh(&bp->ntp_fltr_lock);
5429 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5430 BNXT_NTP_FLTR_MAX_FLTR, 0);
5431 if (bit_id < 0) {
5432 spin_unlock_bh(&bp->ntp_fltr_lock);
5433 rc = -ENOMEM;
5434 goto err_free;
5435 }
5436
5437 new_fltr->sw_id = (u16)bit_id;
5438 new_fltr->flow_id = flow_id;
5439 new_fltr->rxq = rxq_index;
5440 hlist_add_head_rcu(&new_fltr->hash, head);
5441 bp->ntp_fltr_count++;
5442 spin_unlock_bh(&bp->ntp_fltr_lock);
5443
5444 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5445 schedule_work(&bp->sp_task);
5446
5447 return new_fltr->sw_id;
5448
5449 err_free:
5450 kfree(new_fltr);
5451 return rc;
5452 }
5453
bnxt_cfg_ntp_filters(struct bnxt * bp)5454 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5455 {
5456 int i;
5457
5458 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5459 struct hlist_head *head;
5460 struct hlist_node *tmp;
5461 struct bnxt_ntuple_filter *fltr;
5462 int rc;
5463
5464 head = &bp->ntp_fltr_hash_tbl[i];
5465 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5466 bool del = false;
5467
5468 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5469 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5470 fltr->flow_id,
5471 fltr->sw_id)) {
5472 bnxt_hwrm_cfa_ntuple_filter_free(bp,
5473 fltr);
5474 del = true;
5475 }
5476 } else {
5477 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5478 fltr);
5479 if (rc)
5480 del = true;
5481 else
5482 set_bit(BNXT_FLTR_VALID, &fltr->state);
5483 }
5484
5485 if (del) {
5486 spin_lock_bh(&bp->ntp_fltr_lock);
5487 hlist_del_rcu(&fltr->hash);
5488 bp->ntp_fltr_count--;
5489 spin_unlock_bh(&bp->ntp_fltr_lock);
5490 synchronize_rcu();
5491 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5492 kfree(fltr);
5493 }
5494 }
5495 }
5496 }
5497
5498 #else
5499
bnxt_cfg_ntp_filters(struct bnxt * bp)5500 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5501 {
5502 }
5503
5504 #endif /* CONFIG_RFS_ACCEL */
5505
bnxt_add_vxlan_port(struct net_device * dev,sa_family_t sa_family,__be16 port)5506 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5507 __be16 port)
5508 {
5509 struct bnxt *bp = netdev_priv(dev);
5510
5511 if (!netif_running(dev))
5512 return;
5513
5514 if (sa_family != AF_INET6 && sa_family != AF_INET)
5515 return;
5516
5517 if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5518 return;
5519
5520 bp->vxlan_port_cnt++;
5521 if (bp->vxlan_port_cnt == 1) {
5522 bp->vxlan_port = port;
5523 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5524 schedule_work(&bp->sp_task);
5525 }
5526 }
5527
bnxt_del_vxlan_port(struct net_device * dev,sa_family_t sa_family,__be16 port)5528 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5529 __be16 port)
5530 {
5531 struct bnxt *bp = netdev_priv(dev);
5532
5533 if (!netif_running(dev))
5534 return;
5535
5536 if (sa_family != AF_INET6 && sa_family != AF_INET)
5537 return;
5538
5539 if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5540 bp->vxlan_port_cnt--;
5541
5542 if (bp->vxlan_port_cnt == 0) {
5543 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5544 schedule_work(&bp->sp_task);
5545 }
5546 }
5547 }
5548
5549 static const struct net_device_ops bnxt_netdev_ops = {
5550 .ndo_open = bnxt_open,
5551 .ndo_start_xmit = bnxt_start_xmit,
5552 .ndo_stop = bnxt_close,
5553 .ndo_get_stats64 = bnxt_get_stats64,
5554 .ndo_set_rx_mode = bnxt_set_rx_mode,
5555 .ndo_do_ioctl = bnxt_ioctl,
5556 .ndo_validate_addr = eth_validate_addr,
5557 .ndo_set_mac_address = bnxt_change_mac_addr,
5558 .ndo_change_mtu = bnxt_change_mtu,
5559 .ndo_fix_features = bnxt_fix_features,
5560 .ndo_set_features = bnxt_set_features,
5561 .ndo_tx_timeout = bnxt_tx_timeout,
5562 #ifdef CONFIG_BNXT_SRIOV
5563 .ndo_get_vf_config = bnxt_get_vf_config,
5564 .ndo_set_vf_mac = bnxt_set_vf_mac,
5565 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
5566 .ndo_set_vf_rate = bnxt_set_vf_bw,
5567 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
5568 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
5569 #endif
5570 #ifdef CONFIG_NET_POLL_CONTROLLER
5571 .ndo_poll_controller = bnxt_poll_controller,
5572 #endif
5573 .ndo_setup_tc = bnxt_setup_tc,
5574 #ifdef CONFIG_RFS_ACCEL
5575 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
5576 #endif
5577 .ndo_add_vxlan_port = bnxt_add_vxlan_port,
5578 .ndo_del_vxlan_port = bnxt_del_vxlan_port,
5579 #ifdef CONFIG_NET_RX_BUSY_POLL
5580 .ndo_busy_poll = bnxt_busy_poll,
5581 #endif
5582 };
5583
bnxt_remove_one(struct pci_dev * pdev)5584 static void bnxt_remove_one(struct pci_dev *pdev)
5585 {
5586 struct net_device *dev = pci_get_drvdata(pdev);
5587 struct bnxt *bp = netdev_priv(dev);
5588
5589 if (BNXT_PF(bp))
5590 bnxt_sriov_disable(bp);
5591
5592 unregister_netdev(dev);
5593 cancel_work_sync(&bp->sp_task);
5594 bp->sp_event = 0;
5595
5596 bnxt_free_hwrm_resources(bp);
5597 pci_iounmap(pdev, bp->bar2);
5598 pci_iounmap(pdev, bp->bar1);
5599 pci_iounmap(pdev, bp->bar0);
5600 free_netdev(dev);
5601
5602 pci_release_regions(pdev);
5603 pci_disable_device(pdev);
5604 }
5605
bnxt_probe_phy(struct bnxt * bp)5606 static int bnxt_probe_phy(struct bnxt *bp)
5607 {
5608 int rc = 0;
5609 struct bnxt_link_info *link_info = &bp->link_info;
5610 char phy_ver[PHY_VER_STR_LEN];
5611
5612 rc = bnxt_update_link(bp, false);
5613 if (rc) {
5614 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5615 rc);
5616 return rc;
5617 }
5618
5619 /*initialize the ethool setting copy with NVM settings */
5620 if (BNXT_AUTO_MODE(link_info->auto_mode))
5621 link_info->autoneg |= BNXT_AUTONEG_SPEED;
5622
5623 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5624 if (link_info->auto_pause_setting == BNXT_LINK_PAUSE_BOTH)
5625 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
5626 link_info->req_flow_ctrl = link_info->auto_pause_setting;
5627 } else if (link_info->force_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5628 link_info->req_flow_ctrl = link_info->force_pause_setting;
5629 }
5630 link_info->req_duplex = link_info->duplex_setting;
5631 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5632 link_info->req_link_speed = link_info->auto_link_speed;
5633 else
5634 link_info->req_link_speed = link_info->force_link_speed;
5635 link_info->advertising = link_info->auto_link_speeds;
5636 snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d",
5637 link_info->phy_ver[0],
5638 link_info->phy_ver[1],
5639 link_info->phy_ver[2]);
5640 strcat(bp->fw_ver_str, phy_ver);
5641 return rc;
5642 }
5643
bnxt_get_max_irq(struct pci_dev * pdev)5644 static int bnxt_get_max_irq(struct pci_dev *pdev)
5645 {
5646 u16 ctrl;
5647
5648 if (!pdev->msix_cap)
5649 return 1;
5650
5651 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5652 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5653 }
5654
bnxt_get_max_rings(struct bnxt * bp,int * max_rx,int * max_tx)5655 void bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx)
5656 {
5657 int max_rings = 0;
5658
5659 if (BNXT_PF(bp)) {
5660 *max_tx = bp->pf.max_pf_tx_rings;
5661 *max_rx = bp->pf.max_pf_rx_rings;
5662 max_rings = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5663 max_rings = min_t(int, max_rings, bp->pf.max_stat_ctxs);
5664 } else {
5665 #ifdef CONFIG_BNXT_SRIOV
5666 *max_tx = bp->vf.max_tx_rings;
5667 *max_rx = bp->vf.max_rx_rings;
5668 max_rings = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5669 max_rings = min_t(int, max_rings, bp->vf.max_stat_ctxs);
5670 #endif
5671 }
5672 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5673 *max_rx >>= 1;
5674
5675 *max_rx = min_t(int, *max_rx, max_rings);
5676 *max_tx = min_t(int, *max_tx, max_rings);
5677 }
5678
bnxt_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)5679 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5680 {
5681 static int version_printed;
5682 struct net_device *dev;
5683 struct bnxt *bp;
5684 int rc, max_rx_rings, max_tx_rings, max_irqs, dflt_rings;
5685
5686 if (version_printed++ == 0)
5687 pr_info("%s", version);
5688
5689 max_irqs = bnxt_get_max_irq(pdev);
5690 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5691 if (!dev)
5692 return -ENOMEM;
5693
5694 bp = netdev_priv(dev);
5695
5696 if (bnxt_vf_pciid(ent->driver_data))
5697 bp->flags |= BNXT_FLAG_VF;
5698
5699 if (pdev->msix_cap) {
5700 bp->flags |= BNXT_FLAG_MSIX_CAP;
5701 if (BNXT_PF(bp))
5702 bp->flags |= BNXT_FLAG_RFS;
5703 }
5704
5705 rc = bnxt_init_board(pdev, dev);
5706 if (rc < 0)
5707 goto init_err_free;
5708
5709 dev->netdev_ops = &bnxt_netdev_ops;
5710 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5711 dev->ethtool_ops = &bnxt_ethtool_ops;
5712
5713 pci_set_drvdata(pdev, dev);
5714
5715 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5716 NETIF_F_TSO | NETIF_F_TSO6 |
5717 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5718 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5719 NETIF_F_RXHASH |
5720 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5721
5722 if (bp->flags & BNXT_FLAG_RFS)
5723 dev->hw_features |= NETIF_F_NTUPLE;
5724
5725 dev->hw_enc_features =
5726 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5727 NETIF_F_TSO | NETIF_F_TSO6 |
5728 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5729 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5730 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5731 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5732 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5733 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5734 dev->priv_flags |= IFF_UNICAST_FLT;
5735
5736 #ifdef CONFIG_BNXT_SRIOV
5737 init_waitqueue_head(&bp->sriov_cfg_wait);
5738 #endif
5739 rc = bnxt_alloc_hwrm_resources(bp);
5740 if (rc)
5741 goto init_err;
5742
5743 mutex_init(&bp->hwrm_cmd_lock);
5744 bnxt_hwrm_ver_get(bp);
5745
5746 rc = bnxt_hwrm_func_drv_rgtr(bp);
5747 if (rc)
5748 goto init_err;
5749
5750 /* Get the MAX capabilities for this function */
5751 rc = bnxt_hwrm_func_qcaps(bp);
5752 if (rc) {
5753 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5754 rc);
5755 rc = -1;
5756 goto init_err;
5757 }
5758
5759 rc = bnxt_hwrm_queue_qportcfg(bp);
5760 if (rc) {
5761 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5762 rc);
5763 rc = -1;
5764 goto init_err;
5765 }
5766
5767 bnxt_set_tpa_flags(bp);
5768 bnxt_set_ring_params(bp);
5769 dflt_rings = netif_get_num_default_rss_queues();
5770 if (BNXT_PF(bp))
5771 bp->pf.max_irqs = max_irqs;
5772 #if defined(CONFIG_BNXT_SRIOV)
5773 else
5774 bp->vf.max_irqs = max_irqs;
5775 #endif
5776 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings);
5777 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5778 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5779 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5780 bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings);
5781 bp->num_stat_ctxs = bp->cp_nr_rings;
5782
5783 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5784 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5785
5786 rc = bnxt_probe_phy(bp);
5787 if (rc)
5788 goto init_err;
5789
5790 rc = register_netdev(dev);
5791 if (rc)
5792 goto init_err;
5793
5794 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5795 board_info[ent->driver_data].name,
5796 (long)pci_resource_start(pdev, 0), dev->dev_addr);
5797
5798 return 0;
5799
5800 init_err:
5801 pci_iounmap(pdev, bp->bar0);
5802 pci_release_regions(pdev);
5803 pci_disable_device(pdev);
5804
5805 init_err_free:
5806 free_netdev(dev);
5807 return rc;
5808 }
5809
5810 static struct pci_driver bnxt_pci_driver = {
5811 .name = DRV_MODULE_NAME,
5812 .id_table = bnxt_pci_tbl,
5813 .probe = bnxt_init_one,
5814 .remove = bnxt_remove_one,
5815 #if defined(CONFIG_BNXT_SRIOV)
5816 .sriov_configure = bnxt_sriov_configure,
5817 #endif
5818 };
5819
5820 module_pci_driver(bnxt_pci_driver);
5821